diff --git a/fuzzers/060-bram-cascades/Makefile b/fuzzers/060-bram-cascades/Makefile
index ce1713ac..2b8d61bc 100644
--- a/fuzzers/060-bram-cascades/Makefile
+++ b/fuzzers/060-bram-cascades/Makefile
@@ -4,28 +4,29 @@ PIPLIST_TCL=$(FUZDIR)/bram_pip_list.tcl
 PIP_TYPE?=bram_pips_int
 SEG_TYPE?=bram
 N = 50
-SEGMATCH_FLAGS=-m 20 -M 45
+# These PIPs all appear to be either a 0 or 2 bit solution.
+SEGMATCH_FLAGS=-m 20 -M 45 -c 2
 include ../pip_loop.mk
 #
 # Specimens from current run must complete, but previous iterations may exist
 database: $(SPECIMENS_OK)
-	${XRAY_SEGMATCH} $(SEGMATCH_FLAGS) -o build/segbits_bram_l.rdb $(shell find build -name segdata_bram_l.txt)
-	${XRAY_SEGMATCH} $(SEGMATCH_FLAGS) -o build/segbits_bram_r.rdb $(shell find build -name segdata_bram_r.txt)
+	${XRAY_SEGMATCH} $(SEGMATCH_FLAGS) -o build/segbits_bram_x.rdb \
+		$(shell find build -name segdata_bram_l.txt) \
+		$(shell find build -name segdata_bram_r.txt)
 
 	# Keep a copy to track iter progress
 	# Also is pre-fixup, which drops and converts
-	cp build/segbits_bram_l.rdb build/$(ITER)/segbits_bram_l.rdb
-	cp build/segbits_bram_r.rdb build/$(ITER)/segbits_bram_r.rdb
+	cp build/segbits_bram_x.rdb build/$(ITER)/segbits_bram_x.rdb
 	${XRAY_DBFIXUP} --db-root build \
 		--verbose \
 		--zero-db bits.dbf \
-		--seg-fn-in build/segbits_bram_l.rdb \
-		--seg-fn-out build/segbits_bram_l.db
-	${XRAY_DBFIXUP} --db-root build \
-		--verbose \
-		--zero-db bits.dbf \
-		--seg-fn-in build/segbits_bram_r.rdb \
-		--seg-fn-out build/segbits_bram_r.db
+		--seg-fn-in build/segbits_bram_x.rdb \
+		--seg-fn-out build/segbits_bram_x.db
+
+	python3 unmanagle_pips.py \
+		--bram_x build/segbits_bram_x.db \
+		--bram_l build/segbits_bram_l.db \
+		--bram_r build/segbits_bram_r.db
 
 	# Clobber existing .db to eliminate potential conflicts
 	cp ${XRAY_DATABASE_DIR}/${XRAY_DATABASE}/segbits*.db build/database/${XRAY_DATABASE}
diff --git a/fuzzers/060-bram-cascades/generate.py b/fuzzers/060-bram-cascades/generate.py
index efeda1a5..82b30d46 100644
--- a/fuzzers/060-bram-cascades/generate.py
+++ b/fuzzers/060-bram-cascades/generate.py
@@ -60,13 +60,25 @@ for tile, pips_srcs_dsts in tiledata.items():
 
     for pip, src_dst in pipdata[tile_type].items():
         src, dst = src_dst
+
+        # BRAM_R has some _R_ added to some pips.  Because BRAM_L and BRAM_R
+        # appears to shares all bits, overlap the names during fuzzing to avoid
+        # extra work.
+        #
+        # BRAM.BRAM_ADDRARDADDRL0.BRAM_IMUX_R_ADDRARDADDRL0
+        #
+        # becomes
+        #
+        # BRAM.BRAM_ADDRARDADDRL0.BRAM_IMUX_ADDRARDADDRL0
+        src_no_r = src.replace('BRAM_R_IMUX_ADDR', 'BRAM_IMUX_ADDR')
+
         if pip in ignpip:
             pass
 
         elif pip in pips:
-            segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 1)
+            segmk.add_tile_tag(tile, "%s.%s" % (dst, src_no_r), 1)
         elif src_dst[1] not in dsts:
-            segmk.add_tile_tag(tile, "%s.%s" % (dst, src), 0)
+            segmk.add_tile_tag(tile, "%s.%s" % (dst, src_no_r), 0)
 
 segmk.compile()
 segmk.write()
diff --git a/fuzzers/060-bram-cascades/unmanagle_pips.py b/fuzzers/060-bram-cascades/unmanagle_pips.py
new file mode 100644
index 00000000..5f5034f6
--- /dev/null
+++ b/fuzzers/060-bram-cascades/unmanagle_pips.py
@@ -0,0 +1,33 @@
+import argparse
+
+
+def main():
+    parser = argparse.ArgumentParser(
+        description="Converts generic BRAM pips to BRAM_L and BRAM_R pips.")
+
+    parser.add_argument('--bram_x', required=True)
+    parser.add_argument('--bram_l', required=True)
+    parser.add_argument('--bram_r', required=True)
+
+    args = parser.parse_args()
+
+    with open(args.bram_x, 'r') as f_in, open(
+            args.bram_l, 'w') as f_l_out, open(args.bram_r, 'w') as f_r_out:
+        for l in f_in:
+            # BRAM_L has the same pip names as BRAM_X
+            print(l.strip(), file=f_l_out)
+
+            # BRAM_R has some _R_ added to some pips.
+            #
+            # BRAM.BRAM_ADDRARDADDRL0.BRAM_IMUX_ADDRARDADDRL0
+            #
+            # becomes
+            #
+            # BRAM.BRAM_ADDRARDADDRL0.BRAM_IMUX_R_ADDRARDADDRL0
+            print(
+                l.strip().replace('BRAM_IMUX_ADDR', 'BRAM_R_IMUX_ADDR'),
+                file=f_r_out)
+
+
+if __name__ == '__main__':
+    main()
diff --git a/fuzzers/pip_loop.mk b/fuzzers/pip_loop.mk
index 768f62ec..e2a14a26 100644
--- a/fuzzers/pip_loop.mk
+++ b/fuzzers/pip_loop.mk
@@ -3,11 +3,11 @@ TODO_N ?= 50
 ifeq ($(QUICK),Y)
 N = 1
 TODO_N = 3
-SEGMATCH_FLAGS=
+SEGMATCH_FLAGS?=
 else
 # Should be at least the -m value
 N ?= 20
-SEGMATCH_FLAGS=-m 15 -M 45
+SEGMATCH_FLAGS?=-m 15 -M 45
 endif
 # Iteration number (each containing N specimens)
 # Driven by int_loop.sh
diff --git a/utils/dbfixup.py b/utils/dbfixup.py
index 17cdd30a..48a5e797 100755
--- a/utils/dbfixup.py
+++ b/utils/dbfixup.py
@@ -153,7 +153,9 @@ def add_zero_bits(fn_in, zero_db, clb_int=False, strict=True, verbose=False):
                     zero_range(tag, bits, 22, 25)
                 zero_groups(tag, bits, zero_db, strict=strict, verbose=verbose)
 
-                if len(bits) == 0:
+                if strict:
+                    assert len(bits) > 0, 'Line {} found no bits.'.format(line)
+                elif len(bits) == 0:
                     verbose and print(
                         "WARNING: dropping unresolved line: %s" % line)
                     drops += 1