diff --git a/minitests/fixedpnr/runme.sh b/minitests/fixedpnr/runme.sh
index 951db4c8..c2f1fb47 100755
--- a/minitests/fixedpnr/runme.sh
+++ b/minitests/fixedpnr/runme.sh
@@ -2,9 +2,9 @@
 
 set -ex
 vivado -mode batch -source runme.tcl
-for ff in fdre fdse fdce fdce_inv fdpe; do
+for ff in fdre fdse fdce fdce_inv fdpe ldce ldpe; do
     ${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design_$ff.bits -z -y design_$ff.bit
-    ${XRAY_SEGPRINT} design_$ff.bits >design_$ff.seg
+    ${XRAY_SEGPRINT} -z design_$ff.bits >design_$ff.seg
 done
 
 diff -u design_fdre.bits design_fdse.bits
diff --git a/minitests/fixedpnr/runme.tcl b/minitests/fixedpnr/runme.tcl
index b79bfb6b..abc3d2de 100644
--- a/minitests/fixedpnr/runme.tcl
+++ b/minitests/fixedpnr/runme.tcl
@@ -29,7 +29,7 @@ write_bitstream -force design_fdre.bit
 
 close_project
 
-foreach variant {fdse fdce fdce_inv fdpe} {}
+foreach variant {fdse fdce fdce_inv fdpe ldce ldpe} {
 	create_project -force -part $::env(XRAY_PART) design_${variant} design_${variant}
 	read_verilog top_${variant}.v
 	read_xdc fixed.xdc
diff --git a/minitests/fixedpnr/top_ldce.v b/minitests/fixedpnr/top_ldce.v
new file mode 100644
index 00000000..d1708512
--- /dev/null
+++ b/minitests/fixedpnr/top_ldce.v
@@ -0,0 +1,12 @@
+
+module top(input clk, ce, sr, d, output q);
+	(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
+	LDCE ff (
+		.G(clk),
+		.GE(ce),
+		.CLR(sr),
+		.D(d),
+		.Q(q)
+	);
+endmodule
+
diff --git a/minitests/fixedpnr/top_ldpe.v b/minitests/fixedpnr/top_ldpe.v
new file mode 100644
index 00000000..b068a09f
--- /dev/null
+++ b/minitests/fixedpnr/top_ldpe.v
@@ -0,0 +1,12 @@
+
+module top(input clk, ce, sr, d, output q);
+	(* LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH *)
+	LDPE ff (
+		.G(clk),
+		.GE(ce),
+		.PRE(sr),
+		.D(d),
+		.Q(q)
+	);
+endmodule
+