From 6d17580752877409b15129edd711b40e4b470eb4 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Wed, 31 Jul 2019 11:27:10 -0700 Subject: [PATCH] Add some missing ISERDES features. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- fuzzers/035-iob-ilogic/generate.py | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/fuzzers/035-iob-ilogic/generate.py b/fuzzers/035-iob-ilogic/generate.py index ced4d6bd..de5b2672 100644 --- a/fuzzers/035-iob-ilogic/generate.py +++ b/fuzzers/035-iob-ilogic/generate.py @@ -82,6 +82,10 @@ def main(): handle_data_rate(segmk, d) segmk.add_site_tag(site, 'ISERDES.IN_USE', d['use_iserdese2']) + + if 'NUM_CE' in d: + segmk.add_site_tag(site, 'ISERDES.NUM_CE.N2', d['NUM_CE'] == 2) + segmk.add_site_tag( site, 'IDDR_OR_ISERDES.IN_USE', d['use_iserdese2'] or d['iddr_mux_config'] != 'none') @@ -109,6 +113,16 @@ def main(): segmk.add_site_tag(site, 'IFF.ZINIT_Q1', not d['INIT_Q1']) segmk.add_site_tag(site, 'IFF.ZINIT_Q2', not d['INIT_Q2']) + if 'DYN_CLKDIV_INV_EN' in d: + segmk.add_site_tag( + site, 'DYN_CLKDIV_INV_EN', + verilog.unquote(d['DYN_CLKDIV_INV_EN']) == 'TRUE') + + if 'DYN_CLK_INV_EN' in d: + segmk.add_site_tag( + site, 'DYN_CLK_INV_EN', + verilog.unquote(d['DYN_CLK_INV_EN']) == 'TRUE') + if 'INIT_Q3' in d: segmk.add_site_tag(site, 'IFF.ZINIT_Q3', not d['INIT_Q3']) segmk.add_site_tag(site, 'IFF.ZINIT_Q4', not d['INIT_Q4'])