From 6caa47202b44f98daf29a522edc1adc1ac4904ef Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Fri, 1 Feb 2019 13:47:25 -0800
Subject: [PATCH] Output FIFO bits at tile instead of site.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 fuzzers/027-bram36-config/Makefile  |  2 +-
 fuzzers/028-fifo-config/generate.py | 15 +++++----------
 fuzzers/028-fifo-config/top.py      |  1 +
 3 files changed, 7 insertions(+), 11 deletions(-)

diff --git a/fuzzers/027-bram36-config/Makefile b/fuzzers/027-bram36-config/Makefile
index 33d1cf14..1449c154 100644
--- a/fuzzers/027-bram36-config/Makefile
+++ b/fuzzers/027-bram36-config/Makefile
@@ -13,7 +13,7 @@ build/segbits_bramx.db: build/segbits_bramx.rdb
 	${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in $^ --seg-fn-out $@
 	${XRAY_MASKMERGE} build/mask_bramx.db $(addsuffix /segdata_bram_[lr].txt,$(SPECIMENS))
 
-pushdb:
+pushdb: database
 	${XRAY_MERGEDB} bram_l build/segbits_bramx.db
 	${XRAY_MERGEDB} bram_r build/segbits_bramx.db
 	${XRAY_MERGEDB} mask_bram_l build/mask_bramx.db
diff --git a/fuzzers/028-fifo-config/generate.py b/fuzzers/028-fifo-config/generate.py
index 5e904f9b..1e7091eb 100644
--- a/fuzzers/028-fifo-config/generate.py
+++ b/fuzzers/028-fifo-config/generate.py
@@ -8,16 +8,16 @@ from prjxray import verilog
 
 def add_enum_bits(segmk, params, key, options):
     for opt in options:
-        segmk.add_site_tag(params['site'], '{}_{}'.format(key, opt), params[key] == opt)
+        segmk.add_site_tag(params['tile'], '{}_{}'.format(key, opt), params[key] == opt)
 
 def output_integer_tags(segmk, params, key, invert=False):
-    site = params['site']
+    tile = params['tile']
     bits = verilog.parse_bitstr(params[key])
     for bit, tag_val in enumerate(bits):
         if not invert:
-            segmk.add_site_tag(site, "{}[{}]".format(key, len(bits)-bit-1), tag_val)
+            segmk.add_tile_tag(tile, "{}[{}]".format(key, len(bits)-bit-1), tag_val)
         else:
-            segmk.add_site_tag(site, "Z{}[{}]".format(key, len(bits)-bit-1), 0 if tag_val else 1)
+            segmk.add_tile_tag(tile, "Z{}[{}]".format(key, len(bits)-bit-1), 0 if tag_val else 1)
 
 def main():
     segmk = Segmaker("design.bits")
@@ -27,17 +27,12 @@ def main():
         params = json.load(f)
 
     for tile_param in params:
-        #add_enum_bits(segmk, tile_param, 'DATA_WIDTH', [4, 9, 18, 36])
-        #add_enum_bits(segmk, tile_param, 'FIFO_MODE', ['FIFO18', 'FIFO18_36'])
         if tile_param['EN_SYN'] and tile_param['DATA_WIDTH'] == 4:
             output_integer_tags(segmk, tile_param, 'ALMOST_EMPTY_OFFSET', invert=True)
             output_integer_tags(segmk, tile_param, 'ALMOST_FULL_OFFSET', invert=True)
-        #output_integer_tags(segmk, tile_param, 'INIT', 36, invert=True)
-        #output_integer_tags(segmk, tile_param, 'SRVAL', 36, invert=True)
 
         for param in ('EN_SYN', 'FIRST_WORD_FALL_THROUGH'):
-            segmk.add_site_tag(
-                tile_param['site'], param, tile_param[param])
+            segmk.add_tile_tag(tile_param['tile'], param, tile_param[param])
 
     segmk.compile()
     segmk.write()
diff --git a/fuzzers/028-fifo-config/top.py b/fuzzers/028-fifo-config/top.py
index 83d179b9..667a5028 100644
--- a/fuzzers/028-fifo-config/top.py
+++ b/fuzzers/028-fifo-config/top.py
@@ -96,6 +96,7 @@ module top();
     params_list = []
     for tile_name, sites in gen_sites():
         params = {}
+        params['tile'] = tile_name
         params['site'] = sites['RAMBFIFO36E1']
 
         params['DATA_WIDTH'] = random.choice([4, 9, 18, 36, 72])