From 6c2b04a7bf3af6cd7597801718a3cb8cfb6fcc26 Mon Sep 17 00:00:00 2001 From: John McMaster Date: Tue, 30 Oct 2018 10:51:23 -0700 Subject: [PATCH] bram: TDP minitest Signed-off-by: John McMaster --- minitests/bram_basic/Makefile | 2 ++ minitests/bram_basic/runme.tcl | 2 ++ minitests/bram_basic/top.v | 28 +++++++++++++++++++++++++++- 3 files changed, 31 insertions(+), 1 deletion(-) diff --git a/minitests/bram_basic/Makefile b/minitests/bram_basic/Makefile index ac3e4eed..8d9675f9 100644 --- a/minitests/bram_basic/Makefile +++ b/minitests/bram_basic/Makefile @@ -44,4 +44,6 @@ build/roi_bram18_width.diff: build/roi_bram18_write_mode.diff: $(MAKE) -f diff.mk OUT_DIFF=build/roi_bram18_write_mode.diff PRJL=roi_bram18_write_mode_a PRJR=roi_bram18_write_mode_b +build/roi_bram18_ram_mode.diff: + $(MAKE) -f diff.mk OUT_DIFF=build/roi_bram18_ram_mode.diff PRJL=roi_bram18_ram_mode_tdp PRJR=roi_bram18_ram_mode_sdp diff --git a/minitests/bram_basic/runme.tcl b/minitests/bram_basic/runme.tcl index 9674265d..6aa1f9eb 100644 --- a/minitests/bram_basic/runme.tcl +++ b/minitests/bram_basic/runme.tcl @@ -25,5 +25,7 @@ route_design write_checkpoint -force design.dcp # set_property BITSTREAM.GENERAL.DEBUGBITSTREAM Yes [current_design] +# BRAM SDP WEA check, to make test slightly easier to write +set_property IS_ENABLED 0 [get_drc_checks {REQP-1931}] write_bitstream -force design.bit diff --git a/minitests/bram_basic/top.v b/minitests/bram_basic/top.v index b8e07ea7..5369d065 100644 --- a/minitests/bram_basic/top.v +++ b/minitests/bram_basic/top.v @@ -266,7 +266,7 @@ module roi_hck(input clk, input [255:0] din, output [255:0] dout); endmodule /****************************************************************************** -Misc ROI +READ_WIDTH ******************************************************************************/ module roi_bram18_width_a(input clk, input [255:0] din, output [255:0] dout); @@ -281,6 +281,9 @@ module roi_bram18_width_b(input clk, input [255:0] din, output [255:0] dout); endmodule +/****************************************************************************** +WRITE_MODE +******************************************************************************/ module roi_bram18_write_mode_a(input clk, input [255:0] din, output [255:0] dout); ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .WRITE_MODE_A("WRITE_FIRST")) @@ -293,6 +296,29 @@ module roi_bram18_write_mode_b(input clk, input [255:0] din, output [255:0] dout r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); endmodule +/****************************************************************************** +RAM_MODE +******************************************************************************/ + +module roi_bram18_ram_mode_tdp(input clk, input [255:0] din, output [255:0] dout); + ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .RAM_MODE("TDP")) + r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); +endmodule + +/* +ERROR: [DRC REQP-1931] RAMB18E1_WEA_NO_CONNECT_OR_TIED_GND: +roi/r0/ram programming per UG473 requires that for SDP mode the WEA bus must be unconnected +or tied to GND. + +Are these routing bits are real bits we need to look at? +> bit_0002031b_002_00 +> bit_0002031b_002_04 +*/ +module roi_bram18_ram_mode_sdp(input clk, input [255:0] din, output [255:0] dout); + ram_RAMB18E1 #(.LOC("RAMB18_X0Y40"), .RAM_MODE("SDP")) + r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); +endmodule + /****************************************************************************** Library ******************************************************************************/