From f2fb1fd145aac0f68e0091ec7b8e6aa7fb1e5135 Mon Sep 17 00:00:00 2001 From: Davide Date: Mon, 19 Feb 2018 17:14:50 +0100 Subject: [PATCH 1/2] added database development process to FAQ Signed-off-by: Davide --- .../database development process/overview.rst | 31 +++++++++++++++++++ docs/index.rst | 6 ++++ 2 files changed, 37 insertions(+) create mode 100644 docs/database development process/overview.rst diff --git a/docs/database development process/overview.rst b/docs/database development process/overview.rst new file mode 100644 index 00000000..35f56b82 --- /dev/null +++ b/docs/database development process/overview.rst @@ -0,0 +1,31 @@ +Overview +========= + +SymbiFlow/prjxray/fuzzers/ +^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Fuzzers are things that generate a design, feed it to Vivado, and look at the resulting bitstream to make some conclusion. +This is how the contents of the database are generated. + +The general idea behind fuzzers is to pick some element in the device (say a block RAM or IOB) to target. +If you picked the IOB (no one is working on that yet), you'd write a design that is implemented in a specific IOB. +Then you'd create a program that creates variations of the design (called specimens) that vary the design parameters, for example, changing the configuration of a single pin. + +A lot of this program is TCL that runs inside Vivado to change the design parameters, because it is a bit faster to load in one Verilog model and use TCL to replicate it with varying inputs instead of having different models and loading them individually. + +By looking at all the resulting specimens, you can correlate which bits in which frame correspond to a particular choice in the design. + +Looking at the implemented design in Vivado with "Show Routing Resources" turned on is quite helpful in understanding what all choices exist. + +SymbiFlow/symbiflow-arch-defs +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +This is where we describe the logical components in a device to VPR. +VPR stands for place and route software. + +SymbiFlow/prjxray/tools/ +^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Here, you can find various programs to work with bitstreams, mainly to assist building fuzzers. + +SymbiFlow/minitests/roi_harness +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +Shows how to use a bunch of tools together to patch an existing bitstream with hand-crafted FASM (FPGA assembler). + diff --git a/docs/index.rst b/docs/index.rst index 81041af0..b03a7a24 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -21,3 +21,9 @@ to develop a free and open Verilog to bitstream toolchain for these devices. architecture/configuration architecture/bitstream_format architecture/glossary + +.. toctree:: + :maxdepth: 2 + :caption: Database Development Process + + database development process/overview From ad4580d8ed55d29b3fe0bf97d6ae8c94bbf39a3e Mon Sep 17 00:00:00 2001 From: Davide Date: Mon, 19 Feb 2018 22:10:09 +0100 Subject: [PATCH 2/2] Changed folder name for the 'database development process' of the docs and updated the index.rst page accordingly. Also a few minor changes as requested by @mithro regarding the content itself and rearranged the paragraphs. Signed-off-by: Davide --- .../overview.rst | 18 +++++++++++------- docs/index.rst | 2 +- 2 files changed, 12 insertions(+), 8 deletions(-) rename docs/{database development process => db_dev_process}/overview.rst (82%) diff --git a/docs/database development process/overview.rst b/docs/db_dev_process/overview.rst similarity index 82% rename from docs/database development process/overview.rst rename to docs/db_dev_process/overview.rst index 35f56b82..08e26a8d 100644 --- a/docs/database development process/overview.rst +++ b/docs/db_dev_process/overview.rst @@ -1,6 +1,15 @@ Overview ========= +SymbiFlow/symbiflow-arch-defs +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +This is where we describe the logical components in a device to VPR. + +* VtR stands for `Verilog to Routing `_, +* VPR stands for VtR Place and Route. +* VtR also has its own synthesis tool called ODIN-II, but we are using `Yosys `_ instead of that. + + SymbiFlow/prjxray/fuzzers/ ^^^^^^^^^^^^^^^^^^^^^^^^^^^ Fuzzers are things that generate a design, feed it to Vivado, and look at the resulting bitstream to make some conclusion. @@ -16,16 +25,11 @@ By looking at all the resulting specimens, you can correlate which bits in which Looking at the implemented design in Vivado with "Show Routing Resources" turned on is quite helpful in understanding what all choices exist. -SymbiFlow/symbiflow-arch-defs -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -This is where we describe the logical components in a device to VPR. -VPR stands for place and route software. - SymbiFlow/prjxray/tools/ ^^^^^^^^^^^^^^^^^^^^^^^^^^^ Here, you can find various programs to work with bitstreams, mainly to assist building fuzzers. -SymbiFlow/minitests/roi_harness -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +SymbiFlow/prjxray/minitests/roi_harness +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Shows how to use a bunch of tools together to patch an existing bitstream with hand-crafted FASM (FPGA assembler). diff --git a/docs/index.rst b/docs/index.rst index b03a7a24..0a607e3c 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -26,4 +26,4 @@ to develop a free and open Verilog to bitstream toolchain for these devices. :maxdepth: 2 :caption: Database Development Process - database development process/overview + db_dev_process/overview