diff --git a/fuzzers/016-clb-noutmux/Makefile b/fuzzers/016-clb-noutmux/Makefile
index 8ebcd2c2..15886b91 100644
--- a/fuzzers/016-clb-noutmux/Makefile
+++ b/fuzzers/016-clb-noutmux/Makefile
@@ -1,4 +1,4 @@
-N := 3
+N := 4
 CLB_DBFIXUP=Y
 include ../clb.mk
 
diff --git a/fuzzers/016-clb-noutmux/generate.py b/fuzzers/016-clb-noutmux/generate.py
index 78a6ab86..197c6206 100644
--- a/fuzzers/016-clb-noutmux/generate.py
+++ b/fuzzers/016-clb-noutmux/generate.py
@@ -62,7 +62,8 @@ for l in f:
 # create 0-tags for all sources on the remaining (unused) MUXes
 for loc, muxes in cache.items():
     for which in muxes:
-        for src in "F7 F8 CY O5 XOR 5Q".split():
+        for src in "F7 F8 CY O5 XOR 5Q AMC31".split():
+            if src == "AMC31" and which is not "D": continue
             if src == "F7" and which not in "AC": continue
             if src == "F8" and which not in "B": continue
             if src == "5Q": src = which + "5Q"
@@ -74,6 +75,10 @@ def bitfilter(frame_idx, bit_idx):
     # locations of A5MA, B5MA, C5MA, D5MA bits. because of the way we generate specimens
     # in this fuzzer we get some aliasing with those bits, so we have to manually exclude
     # them. (Maybe FIXME: read the bit locations from the database files)
+
+    # Since the SRL32 is enabled along with DOUTMUX.AMC31, bits related to
+    # SRL32 features are masked out.
+
     if (frame_idx, bit_idx) in [
         (30, 55),
         (31, 55),  # D5MA
@@ -83,6 +88,8 @@ def bitfilter(frame_idx, bit_idx):
         (31, 19),  # B5MA
         (30, 9),
         (31, 8),  # A5MA
+        (30, 16),  # ALUT.SRL
+        (1, 23),  # WEMUX.CE
     ]:
         return False
 
diff --git a/fuzzers/016-clb-noutmux/top.py b/fuzzers/016-clb-noutmux/top.py
index 808ef73c..ca104024 100644
--- a/fuzzers/016-clb-noutmux/top.py
+++ b/fuzzers/016-clb-noutmux/top.py
@@ -10,9 +10,15 @@ CLBN = 400 + int(INCREMENT)
 print('//Requested CLBs: %s' % str(CLBN))
 
 
-def gen_slices():
+def gen_slicels():
     for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
-        ['SLICEL', 'SLICEM']):
+        ['SLICEL']):
+        yield site_name
+
+
+def gen_slicems():
+    for _tile_name, site_name, _site_type in util.get_roi().gen_sites(
+        ['SLICEM']):
         yield site_name
 
 
@@ -23,21 +29,32 @@ verilog.top_harness(DIN_N, DOUT_N)
 
 f = open('params.csv', 'w')
 f.write('module,loc,n\n')
-slices = gen_slices()
+slicels = gen_slicels()
+slicems = gen_slicems()
 print(
     'module roi(input clk, input [%d:0] din, output [%d:0] dout);' %
     (DIN_N - 1, DOUT_N - 1))
 for i in range(CLBN):
+
+    use_slicem = (i % 2) == 0
+
+    if use_slicem:
+        loc = next(slicems)
+        variants = ['CY', 'F78', 'O5', 'XOR', 'B5Q', 'AMC31']
+    else:
+        loc = next(slicels)
+        variants = ['CY', 'F78', 'O5', 'XOR', 'B5Q']
+
     # Don't have an O6 example
-    modules = ['clb_NOUTMUX_' + x for x in ['CY', 'F78', 'O5', 'XOR', 'B5Q']]
+    modules = ['clb_NOUTMUX_' + x for x in variants]
     module = random.choice(modules)
 
-    if module == 'clb_NOUTMUX_F78':
+    if module == 'clb_NOUTMUX_AMC31':
+        n = 3  # Only DOUTMUX has AMC31 input
+    elif module == 'clb_NOUTMUX_F78':
         n = random.randint(0, 2)
     else:
         n = random.randint(0, 3)
-    #n = 0
-    loc = next(slices)
 
     print('    %s' % module)
     print('            #(.LOC("%s"), .N(%d))' % (loc, n))
@@ -64,10 +81,13 @@ module myLUT8 (input clk, input [7:0] din,
         output bo5, output bo6,
         //Note: b5ff_q requires the mux and will conflict with other wires
         //Otherwise this FF drops out
-        output wire ff_q);
         //output wire [3:0] n5ff_q);
+        output wire ff_q,
+        output wire amc31);
+
     parameter N=-1;
     parameter LOC="SLICE_FIXME";
+    parameter ALUT_SRL=0;
 
     wire [3:0] caro_all;
     assign caro = caro_all[N];
@@ -126,7 +146,24 @@ module myLUT8 (input clk, input [7:0] din,
 		.O5(lutno5[1]),
 		.O6(lutno6[1]));
 
-	(* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
+    generate if (ALUT_SRL != 0) begin
+    
+    (* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
+	SRLC32E #(
+		.INIT(64'h8000_1CE0_0000_0001)
+	) srla (
+        .CLK(clk),
+        .CE(din[6]),
+        .D(din[5]),
+		.A(din[4:0]),
+		.Q(lutno6[0]),
+        .Q31(amc31));
+
+    assign lutno5[0] = din[6];
+
+    end else begin
+	
+    (* LOC=LOC, BEL="A6LUT", KEEP, DONT_TOUCH *)
 	LUT6_2 #(
 		.INIT(64'h8000_1CE0_0000_0001)
 	) luta (
@@ -139,6 +176,8 @@ module myLUT8 (input clk, input [7:0] din,
 		.O5(lutno5[0]),
 		.O6(lutno6[0]));
 
+    end endgenerate
+
     //Outputs do not have to be used, will stay without them
 	(* LOC=LOC, KEEP, DONT_TOUCH *)
     CARRY4 carry4(.O(caro_all), .CO(carco_all), .DI(lutno5), .S(lutno6), .CYINIT(1'b0), .CI());
@@ -273,4 +312,16 @@ module clb_NOUTMUX_B5Q (input clk, input [7:0] din, output [7:0] dout);
             .bo5(), .bo6(),
             .ff_q(dout[0]));
 endmodule
+
+module clb_NOUTMUX_AMC31 (input clk, input [7:0] din, output [7:0] dout);
+    parameter LOC="SLICE_FIXME";
+    parameter N=0; // Dummy
+
+    myLUT8 #(.LOC(LOC), .N(0), .ALUT_SRL(1))
+            myLUT8(.clk(clk), .din(din),
+            .lut8o(),
+            .caro(), .carco(),
+            .bo5(), .bo6(),
+            .ff_q(), .amc31(dout[0]));
+endmodule
 ''')