diff --git a/fuzzers/005-tilegrid/generate_full.py b/fuzzers/005-tilegrid/generate_full.py
index 2ff76a5b..7492ea4e 100644
--- a/fuzzers/005-tilegrid/generate_full.py
+++ b/fuzzers/005-tilegrid/generate_full.py
@@ -223,13 +223,17 @@ def propagate_INT_bits_in_column(database, tiles_by_grid):
 
 def propagate_INT_INTERFACE_bits_in_column(
         database, tiles_by_grid, int_interface_name):
-    """ Propigate INT offsets up and down INT columns.
+    """ Propagate INT_INTERFACE column for a given INT_INTERFACE tile name.
 
-    INT columns appear to be fairly regular, where starting from offset 0,
-    INT tiles next to INT tiles increase the word offset by 2.  The HCLK tile
-    is surrounded above and sometimes below by an INT tile.  Because the HCLK
-    tile only useds one word, the offset increase by one at the HCLK.
+    INT_INTERFACE tiles do not usually have any PIPs or baseaddresses,
+    except for a few cases such as PCIE or GTP INTERFACE tiles.
 
+    These are very regular tiles, except for the horizontal clock line,
+    which adds a one-word offset.
+
+    This function replicates the baseaddress and calculates the correct offset
+    for each INT INTERFACE tile in a column, starting from a tile in the column
+    that has the baseaddress calculated from the corresponding tilegrid fuzzer.
     """
 
     seen_int = set()
diff --git a/fuzzers/005-tilegrid/gtp_int_interface/generate.tcl b/fuzzers/005-tilegrid/gtp_int_interface/generate.tcl
index c682d573..ec8d5b84 100644
--- a/fuzzers/005-tilegrid/gtp_int_interface/generate.tcl
+++ b/fuzzers/005-tilegrid/gtp_int_interface/generate.tcl
@@ -23,12 +23,16 @@ proc parse_csv {} {
             continue
         }
 
+        # Skip empty lines
+        if { $line == "" } {
+            continue
+        }
+
         set parts [split $line ","]
 
         dict lappend params_map [lindex $parts 2] [lindex $parts 1]
     }
 
-    puts $params_map
     return $params_map
 }
 
@@ -41,11 +45,6 @@ proc route_through_delay {} {
             continue
         }
 
-        if { $key == "" } {
-            puts "Dictionary key is incorrect, continuing"
-            continue
-        }
-
         set net_name "PLL0LOCKEN_$key"
         set net [get_nets $net_name]
 
diff --git a/fuzzers/005-tilegrid/pcie_int_interface/generate.tcl b/fuzzers/005-tilegrid/pcie_int_interface/generate.tcl
index 6391c1c8..86b08a1e 100644
--- a/fuzzers/005-tilegrid/pcie_int_interface/generate.tcl
+++ b/fuzzers/005-tilegrid/pcie_int_interface/generate.tcl
@@ -23,12 +23,16 @@ proc parse_csv {} {
             continue
         }
 
+        # Skip empty lines
+        if { $line == "" } {
+            continue
+        }
+
         set parts [split $line ","]
 
         dict lappend params_map [lindex $parts 0] [lindex $parts 1]
     }
 
-    puts $params_map
     return $params_map
 }
 
@@ -42,11 +46,6 @@ proc route_through_delay {} {
             continue
         }
 
-        if { $key == "" } {
-            puts "Dictionary key is incorrect, continuing"
-            continue
-        }
-
         foreach net $nets {
             set wire [get_wires -of_objects $net -filter {TILE_NAME =~ "*PCIE_INT_INTERFACE*" && NAME =~ "*OUT0*"}]