From 675af0728c7f3ede45d7e61ba6ab452e05f34ad8 Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Wed, 26 Feb 2020 11:54:54 +0100 Subject: [PATCH] Fix warnings in documentation This commit resolves all warnings in the project documentation Signed-off-by: Robert Winkler --- docs/architecture/interconnect.rst | 2 +- docs/conf.py | 15 +++++++++++++-- docs/db_dev_process/fuzzers/index.rst | 16 +--------------- docs/db_dev_process/minitests/index.rst | 20 +------------------- docs/index.rst | 1 - fuzzers/038-cfg/README.md | 2 ++ 6 files changed, 18 insertions(+), 38 deletions(-) diff --git a/docs/architecture/interconnect.rst b/docs/architecture/interconnect.rst index 87ef675f..1be8b512 100644 --- a/docs/architecture/interconnect.rst +++ b/docs/architecture/interconnect.rst @@ -17,7 +17,7 @@ Regular :term:`PIPs ` correspond to a bit pattern that is present in the bi .. warning:: FIXME: Check if the above is true for PIPs outside of the INT switch box. -For example, when the bits 05_57 and 11_56 are set then SR1END3->SE2BEG3 is enabled, but when 08_56 and 11_56 are set then ER1END3->SE2BEG3 is enabled (in an :term:`INT_L `s tile paired with a CLBLL_L tile). A configuration in which all three bits are set is invalid. See `segbits_int_[lr].db` for a complete list of bit pattern for configuring :term:`PIPs `. +For example, when the bits 05_57 and 11_56 are set then SR1END3->SE2BEG3 is enabled, but when 08_56 and 11_56 are set then ER1END3->SE2BEG3 is enabled (in an :term:`INT_L ` tile paired with a CLBLL_L tile). A configuration in which all three bits are set is invalid. See `segbits_int_[lr].db` for a complete list of bit pattern for configuring :term:`PIPs `. VCC Drivers ----------- diff --git a/docs/conf.py b/docs/conf.py index df6615ce..795c4ef4 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -35,6 +35,8 @@ from markdown_code_symlinks import LinkParser, MarkdownSymlinksDomain # Add any Sphinx extension module names here, as strings. They can be # extensions coming with Sphinx (named 'sphinx.ext.*') or your custom # ones. + +# yapf: disable extensions = [ 'sphinx.ext.autodoc', 'sphinx.ext.autosummary', @@ -42,8 +44,9 @@ extensions = [ 'sphinx.ext.imgmath', 'sphinx.ext.napoleon', 'sphinx.ext.todo', - 'sphinx_markdown_tables', + 'sphinx_markdown_tables' ] +# yapf: enable # Add any paths that contain templates here, relative to this directory. templates_path = ['_templates'] @@ -100,7 +103,15 @@ language = None # List of patterns, relative to source directory, that match files and # directories to ignore when looking for source files. # This patterns also effect to html_static_path and html_extra_path -exclude_patterns = ['_build', 'Thumbs.db', '.DS_Store'] + +# yapf: disable +exclude_patterns = [ + '_build', + 'architecture/copying.md', + 'db_dev_process/minitests/index/**', + 'db_dev_process/fuzzers/index/**' +] +# yapf: enable # The name of the Pygments (syntax highlighting) style to use. pygments_style = 'default' diff --git a/docs/db_dev_process/fuzzers/index.rst b/docs/db_dev_process/fuzzers/index.rst index d45fb1d1..fe6f8599 100644 --- a/docs/db_dev_process/fuzzers/index.rst +++ b/docs/db_dev_process/fuzzers/index.rst @@ -57,7 +57,6 @@ Programmable Interconnect Points (PIPs) :maxdepth: 1 :glob: - *int* *pip* Hard Block Fuzzers @@ -67,7 +66,7 @@ Hard Block Fuzzers :maxdepth: 1 :glob: - *xadc + *xadc* Grid and Wire ------------- @@ -77,19 +76,6 @@ Grid and Wire :glob: tilegrid - tileconn - ordered_wires - get_counts - dump_all - -Timing ------- - -.. toctree:: - :maxdepth: 1 - :glob: - - timing All Fuzzers ----------- diff --git a/docs/db_dev_process/minitests/index.rst b/docs/db_dev_process/minitests/index.rst index d97f6ba8..b6666968 100644 --- a/docs/db_dev_process/minitests/index.rst +++ b/docs/db_dev_process/minitests/index.rst @@ -7,22 +7,4 @@ Minitests are experiments to figure out how things work. They allow us to unders :maxdepth: 1 :glob: - clb-bused - clb-carry_cin_cyinit - clb-configs - clb-muxf8 - clkbuf - eccbits - fixedpnr - litex - lvb_long_mux - nodes_wires_list - partial_reconfig_flow - picorv32-v - picorv32-y - pip-switchboxes - roi_harness - srl - tiles_wires_pips - timing - util + * diff --git a/docs/index.rst b/docs/index.rst index 25ef7215..a933d114 100644 --- a/docs/index.rst +++ b/docs/index.rst @@ -26,7 +26,6 @@ to develop a free and open Verilog to bitstream toolchain for these devices. architecture/reference architecture/code_of_conduct architecture/updating_the_docs - architecture/copying .. toctree:: :maxdepth: 2 diff --git a/fuzzers/038-cfg/README.md b/fuzzers/038-cfg/README.md index 04769fba..5dc0353e 100644 --- a/fuzzers/038-cfg/README.md +++ b/fuzzers/038-cfg/README.md @@ -1,3 +1,5 @@ +# cfg fuzzer + This fuzzer solves some of the bits in the CFG_CENTER_MID tile The tile contains sites of the following types: BSCAN, USR_ACCESS, CAPTURE, STARTUP, FRAME_ECC, DCIRESET and ICAP. DCIRESET and USR_ACCESS don't really have any parameters.