diff --git a/fuzzers/007-timing/bel/pin_alias_map.json b/fuzzers/007-timing/bel/pin_alias_map.json index 02465c83..d984d6c4 100644 --- a/fuzzers/007-timing/bel/pin_alias_map.json +++ b/fuzzers/007-timing/bel/pin_alias_map.json @@ -2,59 +2,59 @@ "ff_init": { "Q": { "names" : ["QL", "QH"], - "property" : true + "is_property_related" : true } }, "reg_init": { "Q": { "names" : ["QL", "QH"], - "property" : true + "is_property_related" : true } }, "rambfifo36e1" : { "RSTRAMARSTRAMLRST" : { "names" : ["rstramarstl"], - "property" : false + "is_property_related" : false }, "ADDRARDADDRU0" : { "names" : ["addrau"], - "property" : false + "is_property_related" : false }, "ADDRARDADDRL15" : { "names" : ["addra15l"], - "property" : false + "is_property_related" : false }, "RSTRAMARSTRAMU" : { "names" : ["rstramau"], - "property" : false + "is_property_related" : false }, "ADDRBWRADDRU0" : { "names" : ["addrbu"], - "property" : false + "is_property_related" : false }, "ADDRBWRADDRL15" : { "names" : ["addrb15l"], - "property" : false + "is_property_related" : false }, "WEBWEU0" : { "names" : ["webu"], - "property" : false + "is_property_related" : false }, "DOADO0" : { "names" : ["doadol", "doadou"], - "property" : false + "is_property_related" : false }, "DOBDO0" : { "names" : ["dobdol", "dobdou"], - "property" : false + "is_property_related" : false }, "DOPADOP0" : { "names" : ["dopadopl", "dopadopu"], - "property" : false + "is_property_related" : false }, "DOPBDOP0" : { "names" : ["dopbdopl", "dopbdopu"], - "property" : false + "is_property_related" : false } } } diff --git a/fuzzers/007-timing/bel/tim2json.py b/fuzzers/007-timing/bel/tim2json.py index 280cd74c..ac020092 100644 --- a/fuzzers/007-timing/bel/tim2json.py +++ b/fuzzers/007-timing/bel/tim2json.py @@ -63,13 +63,13 @@ def find_aliased_pin(pin, model, pin_aliases): >>> find_aliased_pin("a", "a_b_some_test_string", None) (False, None) - >>> find_aliased_pin("d", "din_dout_setup", {"D": {"names" : ["din"], "property" : False}}) + >>> find_aliased_pin("d", "din_dout_setup", {"D": {"names" : ["din"], "is_property_related" : False}}) (True, 'din') - >>> find_aliased_pin("d", "din_dout_setup", {"D": {"names" : ["din"], "property" : True}}) + >>> find_aliased_pin("d", "din_dout_setup", {"D": {"names" : ["din"], "is_property_related" : True}}) (True, 'd') - >>> find_aliased_pin("d", "din_dout_setup", {"D": {"names" : ["notdin"], "property" : True}}) + >>> find_aliased_pin("d", "din_dout_setup", {"D": {"names" : ["notdin"], "is_property_related" : True}}) (False, None) """ if (pin_aliases is not None) and (pin.upper() in pin_aliases): @@ -81,7 +81,7 @@ def find_aliased_pin(pin, model, pin_aliases): else: model_to_check = model if pin_alias in model_to_check: - if pin_aliases[pin.upper()]['property']: + if pin_aliases[pin.upper()]['is_property_related']: return True, pin.lower() else: return True, pin_alias @@ -108,16 +108,16 @@ def pin_in_model(pin, pin_aliases, model, direction=None): >>> pin_in_model("q", None, "ff_init_clk_q", None) (True, 'q') - >>> pin_in_model("q", {"Q": {"names" : ["QL", "QH"], "property" : True}}, "ff_init_clk_ql", None) + >>> pin_in_model("q", {"Q": {"names" : ["QL", "QH"], "is_property_related" : True}}, "ff_init_clk_ql", None) (True, 'q') >>> pin_in_model("logic_out", None, "my_cell_i_logic_out", None) (True, 'logic_out') - >>> pin_in_model("logic_out", {"LOGIC_OUT": {"names" : ["LOGIC_O", "O"], "property" : False}}, "my_cell_i_logic_o", None) + >>> pin_in_model("logic_out", {"LOGIC_OUT": {"names" : ["LOGIC_O", "O"], "is_property_related" : False}}, "my_cell_i_logic_o", None) (True, 'logic_o') - >>> pin_in_model("logic_out", {"LOGIC_OUT": {"names" : ["LOGIC_O", "O"], "property" : False}}, "my_cell_i_o", None) + >>> pin_in_model("logic_out", {"LOGIC_OUT": {"names" : ["LOGIC_O", "O"], "is_property_related" : False}}, "my_cell_i_o", None) (True, 'o') """