diff --git a/fuzzers/051-imuxlout/.gitignore b/fuzzers/051-imuxlout/.gitignore index 145bd747..a747a2b4 100644 --- a/fuzzers/051-imuxlout/.gitignore +++ b/fuzzers/051-imuxlout/.gitignore @@ -1,14 +1,3 @@ -/filtered_seg_int_l.segbits -/filtered_seg_int_r.segbits -/pattern_l.txt -/pattern_r.txt -/piplist.dcp -/piplist/ -/pips_int_l.txt -/pips_int_r.txt -/seg_int_l.segbits -/seg_int_r.segbits -/specimen_[0-9][0-9][0-9]/ -/todo.txt -/vivado* -/run.ok +build +run.ok +todo diff --git a/fuzzers/051-imuxlout/Makefile b/fuzzers/051-imuxlout/Makefile index 1053082b..09d27498 100644 --- a/fuzzers/051-imuxlout/Makefile +++ b/fuzzers/051-imuxlout/Makefile @@ -1,33 +1,2 @@ - -N := 10 -SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N))) -SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS)) - -database: $(SPECIMENS_OK) - ${XRAY_SEGMATCH} -m 5 -M 15 -o segbits_int_l.db $(addsuffix /segdata_int_l.txt,$(SPECIMENS)) - ${XRAY_SEGMATCH} -m 5 -M 15 -o segbits_int_r.db $(addsuffix /segdata_int_r.txt,$(SPECIMENS)) - -pushdb: - ${XRAY_DBFIXUP} --db-root . --clb-int - ${XRAY_MERGEDB} int_l segbits_int_l.db - ${XRAY_MERGEDB} int_r segbits_int_r.db - -$(SPECIMENS_OK): todo.txt - bash generate.sh $(subst /OK,,$@) - touch $@ - -todo.txt: - vivado -mode batch -source piplist.tcl - python3 maketodo.py > todo.txt - -run: - +set -ex; while make clean; make todo.txt; test -s todo.txt; do make database; make pushdb; done; true - touch run.ok - -clean: - rm -rf .Xil/ .cache/ run.ok - rm -rf todo.txt vivado* piplist/ piplist.dcp pattern_[lr].txt pips_int_[lr].txt - rm -rf specimen_[0-9][0-9][0-9]/ segbits_int_[lr].db mask_clbl[lm]_[lr].segbits - -.PHONY: database pushdb run clean +include ../int_loop.mk diff --git a/fuzzers/051-imuxlout/generate.tcl b/fuzzers/051-imuxlout/generate.tcl index ec5255f1..36c5abbb 100644 --- a/fuzzers/051-imuxlout/generate.tcl +++ b/fuzzers/051-imuxlout/generate.tcl @@ -1,6 +1,8 @@ +source "$::env(XRAY_DIR)/utils/utils.tcl" + create_project -force -part $::env(XRAY_PART) design design -read_verilog ../top.v +read_verilog $::env(FUZDIR)/top.v synth_design -top top set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i] @@ -19,7 +21,6 @@ route_design # write_checkpoint -force design.dcp -source ../../../utils/utils.tcl set fp [open "../todo.txt" r] set todo_lines {} diff --git a/fuzzers/051-imuxlout/maketodo.py b/fuzzers/051-imuxlout/maketodo.py index 65ded28f..f1b018ed 100644 --- a/fuzzers/051-imuxlout/maketodo.py +++ b/fuzzers/051-imuxlout/maketodo.py @@ -20,8 +20,8 @@ def maketodo(pipfile, dbfile): maketodo( - "pips_int_l.txt", "%s/%s/segbits_int_l.db" % + "build/pips_int_l.txt", "%s/%s/segbits_int_l.db" % (os.getenv("XRAY_DATABASE_DIR"), os.getenv("XRAY_DATABASE"))) maketodo( - "pips_int_r.txt", "%s/%s/segbits_int_r.db" % + "build/pips_int_r.txt", "%s/%s/segbits_int_r.db" % (os.getenv("XRAY_DATABASE_DIR"), os.getenv("XRAY_DATABASE"))) diff --git a/fuzzers/051-imuxlout/piplist.tcl b/fuzzers/051-imuxlout/piplist.tcl deleted file mode 100644 index 4b2c87cc..00000000 --- a/fuzzers/051-imuxlout/piplist.tcl +++ /dev/null @@ -1,39 +0,0 @@ -create_project -force -part $::env(XRAY_PART) piplist piplist - -read_verilog top.v -synth_design -top top - -set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i] -set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o] - -create_pblock roi -resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" - -set_property CFGBVS VCCO [current_design] -set_property CONFIG_VOLTAGE 3.3 [current_design] -set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] - -place_design -route_design - -write_checkpoint -force piplist.dcp - -source ../../utils/utils.tcl - -proc print_tile_pips {tile_type filename} { - set tile [lindex [get_tiles -filter "TYPE == $tile_type"] 0] - puts "Dumping PIPs for tile $tile ($tile_type) to $filename." - set fp [open $filename w] - foreach pip [lsort [get_pips -filter {IS_DIRECTIONAL} -of_objects [get_tiles $tile]]] { - set src [get_wires -uphill -of_objects $pip] - set dst [get_wires -downhill -of_objects $pip] - if {[llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst]]] != 1} { - puts $fp "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]" - } - } - close $fp -} - -print_tile_pips INT_L pips_int_l.txt -print_tile_pips INT_R pips_int_r.txt - diff --git a/fuzzers/052-clkin/.gitignore b/fuzzers/052-clkin/.gitignore index 145bd747..a747a2b4 100644 --- a/fuzzers/052-clkin/.gitignore +++ b/fuzzers/052-clkin/.gitignore @@ -1,14 +1,3 @@ -/filtered_seg_int_l.segbits -/filtered_seg_int_r.segbits -/pattern_l.txt -/pattern_r.txt -/piplist.dcp -/piplist/ -/pips_int_l.txt -/pips_int_r.txt -/seg_int_l.segbits -/seg_int_r.segbits -/specimen_[0-9][0-9][0-9]/ -/todo.txt -/vivado* -/run.ok +build +run.ok +todo diff --git a/fuzzers/052-clkin/Makefile b/fuzzers/052-clkin/Makefile index fec8a87a..09d27498 100644 --- a/fuzzers/052-clkin/Makefile +++ b/fuzzers/052-clkin/Makefile @@ -1,33 +1,2 @@ - -N := 10 -SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N))) -SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS)) - -database: $(SPECIMENS_OK) - ${XRAY_SEGMATCH} -m 5 -M 15 -o segbits_int_l.db $(addsuffix /segdata_int_l.txt,$(SPECIMENS)) - ${XRAY_SEGMATCH} -m 5 -M 15 -o segbits_int_r.db $(addsuffix /segdata_int_r.txt,$(SPECIMENS)) - -pushdb: - ${XRAY_DBFIXUP} --db-root . --clb-int - ${XRAY_MERGEDB} int_l segbits_int_l.db - ${XRAY_MERGEDB} int_r segbits_int_r.db - -$(SPECIMENS_OK): todo.txt - bash generate.sh $(subst /OK,,$@) - touch $@ - -todo.txt: - vivado -mode batch -source piplist.tcl - python3 maketodo.py | sort -R | head -n10 > todo.txt - -run: - +set -ex; while make clean; make todo.txt; test -s todo.txt; do make database; make pushdb; done; true - touch run.ok - -clean: - rm -rf .Xil/ .cache/ filtered_seg_int_[lr].db run.ok - rm -rf todo.txt vivado* piplist/ piplist.dcp pattern_[lr].txt pips_int_[lr].txt - rm -rf specimen_[0-9][0-9][0-9]/ segbits_int_[lr].db mask_clbl[lm]_[lr].segbits - -.PHONY: database pushdb run clean +include ../int_loop.mk diff --git a/fuzzers/052-clkin/generate.tcl b/fuzzers/052-clkin/generate.tcl index d4aaa065..a1b70724 100644 --- a/fuzzers/052-clkin/generate.tcl +++ b/fuzzers/052-clkin/generate.tcl @@ -1,6 +1,8 @@ +source "$::env(XRAY_DIR)/utils/utils.tcl" + create_project -force -part $::env(XRAY_PART) design design -read_verilog ../top.v +read_verilog $::env(FUZDIR)/top.v synth_design -top top set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i] @@ -19,7 +21,6 @@ route_design # write_checkpoint -force design.dcp -source ../../../utils/utils.tcl set fp [open "../todo.txt" r] set todo_lines {} diff --git a/fuzzers/052-clkin/maketodo.py b/fuzzers/052-clkin/maketodo.py index 3c5dc523..111ecaba 100644 --- a/fuzzers/052-clkin/maketodo.py +++ b/fuzzers/052-clkin/maketodo.py @@ -19,8 +19,8 @@ def maketodo(pipfile, dbfile): maketodo( - "pips_int_l.txt", "%s/%s/segbits_int_l.db" % + "build/pips_int_l.txt", "%s/%s/segbits_int_l.db" % (os.getenv("XRAY_DATABASE_DIR"), os.getenv("XRAY_DATABASE"))) maketodo( - "pips_int_r.txt", "%s/%s/segbits_int_r.db" % + "build/pips_int_r.txt", "%s/%s/segbits_int_r.db" % (os.getenv("XRAY_DATABASE_DIR"), os.getenv("XRAY_DATABASE"))) diff --git a/fuzzers/052-clkin/piplist.tcl b/fuzzers/052-clkin/piplist.tcl deleted file mode 100644 index 4b2c87cc..00000000 --- a/fuzzers/052-clkin/piplist.tcl +++ /dev/null @@ -1,39 +0,0 @@ -create_project -force -part $::env(XRAY_PART) piplist piplist - -read_verilog top.v -synth_design -top top - -set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i] -set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o] - -create_pblock roi -resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" - -set_property CFGBVS VCCO [current_design] -set_property CONFIG_VOLTAGE 3.3 [current_design] -set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] - -place_design -route_design - -write_checkpoint -force piplist.dcp - -source ../../utils/utils.tcl - -proc print_tile_pips {tile_type filename} { - set tile [lindex [get_tiles -filter "TYPE == $tile_type"] 0] - puts "Dumping PIPs for tile $tile ($tile_type) to $filename." - set fp [open $filename w] - foreach pip [lsort [get_pips -filter {IS_DIRECTIONAL} -of_objects [get_tiles $tile]]] { - set src [get_wires -uphill -of_objects $pip] - set dst [get_wires -downhill -of_objects $pip] - if {[llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst]]] != 1} { - puts $fp "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]" - } - } - close $fp -} - -print_tile_pips INT_L pips_int_l.txt -print_tile_pips INT_R pips_int_r.txt - diff --git a/fuzzers/053-ctrlin/.gitignore b/fuzzers/053-ctrlin/.gitignore index 145bd747..a747a2b4 100644 --- a/fuzzers/053-ctrlin/.gitignore +++ b/fuzzers/053-ctrlin/.gitignore @@ -1,14 +1,3 @@ -/filtered_seg_int_l.segbits -/filtered_seg_int_r.segbits -/pattern_l.txt -/pattern_r.txt -/piplist.dcp -/piplist/ -/pips_int_l.txt -/pips_int_r.txt -/seg_int_l.segbits -/seg_int_r.segbits -/specimen_[0-9][0-9][0-9]/ -/todo.txt -/vivado* -/run.ok +build +run.ok +todo diff --git a/fuzzers/053-ctrlin/Makefile b/fuzzers/053-ctrlin/Makefile index fec8a87a..09d27498 100644 --- a/fuzzers/053-ctrlin/Makefile +++ b/fuzzers/053-ctrlin/Makefile @@ -1,33 +1,2 @@ - -N := 10 -SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N))) -SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS)) - -database: $(SPECIMENS_OK) - ${XRAY_SEGMATCH} -m 5 -M 15 -o segbits_int_l.db $(addsuffix /segdata_int_l.txt,$(SPECIMENS)) - ${XRAY_SEGMATCH} -m 5 -M 15 -o segbits_int_r.db $(addsuffix /segdata_int_r.txt,$(SPECIMENS)) - -pushdb: - ${XRAY_DBFIXUP} --db-root . --clb-int - ${XRAY_MERGEDB} int_l segbits_int_l.db - ${XRAY_MERGEDB} int_r segbits_int_r.db - -$(SPECIMENS_OK): todo.txt - bash generate.sh $(subst /OK,,$@) - touch $@ - -todo.txt: - vivado -mode batch -source piplist.tcl - python3 maketodo.py | sort -R | head -n10 > todo.txt - -run: - +set -ex; while make clean; make todo.txt; test -s todo.txt; do make database; make pushdb; done; true - touch run.ok - -clean: - rm -rf .Xil/ .cache/ filtered_seg_int_[lr].db run.ok - rm -rf todo.txt vivado* piplist/ piplist.dcp pattern_[lr].txt pips_int_[lr].txt - rm -rf specimen_[0-9][0-9][0-9]/ segbits_int_[lr].db mask_clbl[lm]_[lr].segbits - -.PHONY: database pushdb run clean +include ../int_loop.mk diff --git a/fuzzers/053-ctrlin/generate.tcl b/fuzzers/053-ctrlin/generate.tcl index 75301594..dd7e2245 100644 --- a/fuzzers/053-ctrlin/generate.tcl +++ b/fuzzers/053-ctrlin/generate.tcl @@ -1,6 +1,8 @@ +source "$::env(XRAY_DIR)/utils/utils.tcl" + create_project -force -part $::env(XRAY_PART) design design -read_verilog ../top.v +read_verilog $::env(FUZDIR)/top.v synth_design -top top set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i] @@ -19,7 +21,6 @@ route_design # write_checkpoint -force design.dcp -source ../../../utils/utils.tcl set fp [open "../todo.txt" r] set todo_lines {} diff --git a/fuzzers/053-ctrlin/maketodo.py b/fuzzers/053-ctrlin/maketodo.py index 26311e34..d66cb3a5 100644 --- a/fuzzers/053-ctrlin/maketodo.py +++ b/fuzzers/053-ctrlin/maketodo.py @@ -19,8 +19,8 @@ def maketodo(pipfile, dbfile): maketodo( - "pips_int_l.txt", "%s/%s/segbits_int_l.db" % + "build/pips_int_l.txt", "%s/%s/segbits_int_l.db" % (os.getenv("XRAY_DATABASE_DIR"), os.getenv("XRAY_DATABASE"))) maketodo( - "pips_int_r.txt", "%s/%s/segbits_int_r.db" % + "build/pips_int_r.txt", "%s/%s/segbits_int_r.db" % (os.getenv("XRAY_DATABASE_DIR"), os.getenv("XRAY_DATABASE"))) diff --git a/fuzzers/053-ctrlin/piplist.tcl b/fuzzers/053-ctrlin/piplist.tcl deleted file mode 100644 index 4b2c87cc..00000000 --- a/fuzzers/053-ctrlin/piplist.tcl +++ /dev/null @@ -1,39 +0,0 @@ -create_project -force -part $::env(XRAY_PART) piplist piplist - -read_verilog top.v -synth_design -top top - -set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i] -set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o] - -create_pblock roi -resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" - -set_property CFGBVS VCCO [current_design] -set_property CONFIG_VOLTAGE 3.3 [current_design] -set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] - -place_design -route_design - -write_checkpoint -force piplist.dcp - -source ../../utils/utils.tcl - -proc print_tile_pips {tile_type filename} { - set tile [lindex [get_tiles -filter "TYPE == $tile_type"] 0] - puts "Dumping PIPs for tile $tile ($tile_type) to $filename." - set fp [open $filename w] - foreach pip [lsort [get_pips -filter {IS_DIRECTIONAL} -of_objects [get_tiles $tile]]] { - set src [get_wires -uphill -of_objects $pip] - set dst [get_wires -downhill -of_objects $pip] - if {[llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst]]] != 1} { - puts $fp "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]" - } - } - close $fp -} - -print_tile_pips INT_L pips_int_l.txt -print_tile_pips INT_R pips_int_r.txt - diff --git a/fuzzers/054-gfan/.gitignore b/fuzzers/054-gfan/.gitignore index 9c926485..a747a2b4 100644 --- a/fuzzers/054-gfan/.gitignore +++ b/fuzzers/054-gfan/.gitignore @@ -1,13 +1,3 @@ -/filtered_seg_int_l.segbits -/filtered_seg_int_r.segbits -/pattern_l.txt -/pattern_r.txt -/piplist.dcp -/piplist/ -/pips_int_l.txt -/pips_int_r.txt -/seg_int_l.segbits -/seg_int_r.segbits -/specimen_[0-9][0-9][0-9]/ -/todo.txt -/vivado* +build +run.ok +todo diff --git a/fuzzers/054-gfan/Makefile b/fuzzers/054-gfan/Makefile index fec8a87a..09d27498 100644 --- a/fuzzers/054-gfan/Makefile +++ b/fuzzers/054-gfan/Makefile @@ -1,33 +1,2 @@ - -N := 10 -SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N))) -SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS)) - -database: $(SPECIMENS_OK) - ${XRAY_SEGMATCH} -m 5 -M 15 -o segbits_int_l.db $(addsuffix /segdata_int_l.txt,$(SPECIMENS)) - ${XRAY_SEGMATCH} -m 5 -M 15 -o segbits_int_r.db $(addsuffix /segdata_int_r.txt,$(SPECIMENS)) - -pushdb: - ${XRAY_DBFIXUP} --db-root . --clb-int - ${XRAY_MERGEDB} int_l segbits_int_l.db - ${XRAY_MERGEDB} int_r segbits_int_r.db - -$(SPECIMENS_OK): todo.txt - bash generate.sh $(subst /OK,,$@) - touch $@ - -todo.txt: - vivado -mode batch -source piplist.tcl - python3 maketodo.py | sort -R | head -n10 > todo.txt - -run: - +set -ex; while make clean; make todo.txt; test -s todo.txt; do make database; make pushdb; done; true - touch run.ok - -clean: - rm -rf .Xil/ .cache/ filtered_seg_int_[lr].db run.ok - rm -rf todo.txt vivado* piplist/ piplist.dcp pattern_[lr].txt pips_int_[lr].txt - rm -rf specimen_[0-9][0-9][0-9]/ segbits_int_[lr].db mask_clbl[lm]_[lr].segbits - -.PHONY: database pushdb run clean +include ../int_loop.mk diff --git a/fuzzers/054-gfan/generate.sh b/fuzzers/054-gfan/generate.sh index 9f904105..d7640d94 100644 --- a/fuzzers/054-gfan/generate.sh +++ b/fuzzers/054-gfan/generate.sh @@ -1,5 +1,7 @@ #!/bin/bash +echo "test: $PWD" +FUZDIR=$PWD source ${XRAY_GENHEADER} vivado -mode batch -source ../generate.tcl diff --git a/fuzzers/054-gfan/generate.tcl b/fuzzers/054-gfan/generate.tcl index 71d7e8a8..a85dd633 100644 --- a/fuzzers/054-gfan/generate.tcl +++ b/fuzzers/054-gfan/generate.tcl @@ -1,79 +1,97 @@ -create_project -force -part $::env(XRAY_PART) design design +source "$::env(XRAY_DIR)/utils/utils.tcl" -read_verilog ../top.v -synth_design -top top +proc base_project {} { + create_project -force -part $::env(XRAY_PART) design design -set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i] -set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o] + read_verilog $::env(FUZDIR)/top.v + synth_design -top top -create_pblock roi -resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" + set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i] + set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o] -set_property CFGBVS VCCO [current_design] -set_property CONFIG_VOLTAGE 3.3 [current_design] -set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] -set_param tcl.collectionResultDisplayLimit 0 + create_pblock roi + resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" -place_design -route_design + set_property CFGBVS VCCO [current_design] + set_property CONFIG_VOLTAGE 3.3 [current_design] + set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] + set_param tcl.collectionResultDisplayLimit 0 -# write_checkpoint -force design.dcp - -source ../../../utils/utils.tcl - -set fp [open "../todo.txt" r] -set todo_lines {} -for {gets $fp line} {$line != ""} {gets $fp line} { - lappend todo_lines [split $line .] -} -close $fp - -set int_l_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi] {TYPE == INT_L}]] -set int_r_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi] {TYPE == INT_R}]] - -for {set idx 0} {$idx < [llength $todo_lines]} {incr idx} { - set line [lindex $todo_lines $idx] - puts "== $idx: $line" - - set tile_type [lindex $line 0] - set dst_wire [lindex $line 1] - set src_wire [lindex $line 2] - - if {$tile_type == "INT_L"} {set tile [lindex $int_l_tiles $idx]; set other_tile [lindex $int_r_tiles $idx]} - if {$tile_type == "INT_R"} {set tile [lindex $int_r_tiles $idx]; set other_tile [lindex $int_l_tiles $idx]} - - set driver_site [get_sites -of_objects [get_site_pins -of_objects [get_nodes -downhill \ - -of_objects [get_nodes -of_objects [get_wires $other_tile/CLK*0]]]]] - - set mylut [create_cell -reference LUT1 mylut_$idx] - set_property -dict "LOC $driver_site BEL A6LUT" $mylut - - set mynet [create_net mynet_$idx] - connect_net -net $mynet -objects "$mylut/I0 $mylut/O" - route_via $mynet "$tile/$src_wire $tile/$dst_wire" + place_design + route_design } proc write_txtdata {filename} { - puts "Writing $filename." - set fp [open $filename w] - set all_pips [lsort -unique [get_pips -of_objects [get_nets -hierarchical]]] - if {$all_pips != {}} { - puts "Dumping pips." - foreach tile [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]] { - foreach pip [filter $all_pips "TILE == $tile"] { - set src_wire [get_wires -uphill -of_objects $pip] - set dst_wire [get_wires -downhill -of_objects $pip] - set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] - set dir_prop [get_property IS_DIRECTIONAL $pip] - puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" - } - } - } - close $fp + puts "Writing $filename." + set fp [open $filename w] + set all_pips [lsort -unique [get_pips -of_objects [get_nets -hierarchical]]] + if {$all_pips != {}} { + puts "Dumping pips." + foreach tile [get_tiles [regsub -all {CLBL[LM]} [get_tiles -of_objects [get_sites -of_objects [get_pblocks roi]]] INT]] { + foreach pip [filter $all_pips "TILE == $tile"] { + set src_wire [get_wires -uphill -of_objects $pip] + set dst_wire [get_wires -downhill -of_objects $pip] + set num_pips [llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst_wire]]] + set dir_prop [get_property IS_DIRECTIONAL $pip] + puts $fp "$tile $pip $src_wire $dst_wire $num_pips $dir_prop" + } + } + } + close $fp } -route_design -write_checkpoint -force design.dcp -write_bitstream -force design.bit -write_txtdata design.txt +proc loop { line idx int_l_tile int_r_tile } { + set tile_type [lindex $line 0] + set dst_wire [lindex $line 1] + set src_wire [lindex $line 2] + + if {$tile_type == "INT_L"} {set tile $int_l_tile; set other_tile $int_r_tile} + if {$tile_type == "INT_R"} {set tile $int_r_tile; set other_tile $int_l_tile} + + set driver_site [get_sites -of_objects [get_site_pins -of_objects [get_nodes -downhill \ + -of_objects [get_nodes -of_objects [get_wires $other_tile/CLK*0]]]]] + + set mylut [create_cell -reference LUT1 mylut_$idx] + set_property -dict "LOC $driver_site BEL A6LUT" $mylut + + set mynet [create_net mynet_$idx] + connect_net -net $mynet -objects "$mylut/I0 $mylut/O" + route_via $mynet "$tile/$src_wire $tile/$dst_wire" +} + +proc load_todo_lines {} { + set fp [open "../todo.txt" r] + set todo_lines {} + for {gets $fp line} {$line != ""} {gets $fp line} { + lappend todo_lines [split $line .] + } + close $fp + return $todo_lines +} + +proc run {} { + base_project + + # write_checkpoint -force design.dcp + + set todo_lines [load_todo_lines] + set int_l_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi] {TYPE == INT_L}]] + set int_r_tiles [randsample_list [llength $todo_lines] [filter [pblock_tiles roi] {TYPE == INT_R}]] + + for {set idx 0} {$idx < [llength $todo_lines]} {incr idx} { + set line [lindex $todo_lines $idx] + puts "== $idx: $line" + set int_l_tile [lindex $int_l_tiles $idx] + set int_r_tile [lindex $int_r_tiles $idx] + loop $line $idx $int_l_tile $int_r_tile + } + + route_design + write_checkpoint -force design.dcp + write_bitstream -force design.bit + write_txtdata design.txt + +} + +run diff --git a/fuzzers/054-gfan/maketodo.py b/fuzzers/054-gfan/maketodo.py index b39d48bf..fe7bebfe 100644 --- a/fuzzers/054-gfan/maketodo.py +++ b/fuzzers/054-gfan/maketodo.py @@ -20,8 +20,8 @@ def maketodo(pipfile, dbfile): maketodo( - "pips_int_l.txt", "%s/%s/segbits_int_l.db" % + "build/pips_int_l.txt", "%s/%s/segbits_int_l.db" % (os.getenv("XRAY_DATABASE_DIR"), os.getenv("XRAY_DATABASE"))) maketodo( - "pips_int_r.txt", "%s/%s/segbits_int_r.db" % + "build/pips_int_r.txt", "%s/%s/segbits_int_r.db" % (os.getenv("XRAY_DATABASE_DIR"), os.getenv("XRAY_DATABASE"))) diff --git a/fuzzers/054-gfan/piplist.tcl b/fuzzers/054-gfan/piplist.tcl deleted file mode 100644 index 4b2c87cc..00000000 --- a/fuzzers/054-gfan/piplist.tcl +++ /dev/null @@ -1,39 +0,0 @@ -create_project -force -part $::env(XRAY_PART) piplist piplist - -read_verilog top.v -synth_design -top top - -set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i] -set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o] - -create_pblock roi -resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" - -set_property CFGBVS VCCO [current_design] -set_property CONFIG_VOLTAGE 3.3 [current_design] -set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] - -place_design -route_design - -write_checkpoint -force piplist.dcp - -source ../../utils/utils.tcl - -proc print_tile_pips {tile_type filename} { - set tile [lindex [get_tiles -filter "TYPE == $tile_type"] 0] - puts "Dumping PIPs for tile $tile ($tile_type) to $filename." - set fp [open $filename w] - foreach pip [lsort [get_pips -filter {IS_DIRECTIONAL} -of_objects [get_tiles $tile]]] { - set src [get_wires -uphill -of_objects $pip] - set dst [get_wires -downhill -of_objects $pip] - if {[llength [get_nodes -uphill -of_objects [get_nodes -of_objects $dst]]] != 1} { - puts $fp "$tile_type.[regsub {.*/} $dst ""].[regsub {.*/} $src ""]" - } - } - close $fp -} - -print_tile_pips INT_L pips_int_l.txt -print_tile_pips INT_R pips_int_r.txt - diff --git a/fuzzers/055-gnd/Makefile b/fuzzers/055-gnd/Makefile index 0216e069..1e6e6cf8 100644 --- a/fuzzers/055-gnd/Makefile +++ b/fuzzers/055-gnd/Makefile @@ -30,7 +30,7 @@ run: clean: rm -rf .Xil/ .cache/ filtered_seg_int_[lr].db run.ok - rm -rf todo.txt vivado* piplist/ piplist.dcp pattern_[lr].txt pips_int_[lr].txt + rm -rf todo.txt vivado* pattern_[lr].txt pips_int_[lr].txt rm -rf specimen_[0-9][0-9][0-9]/ segbits_int_[lr].db mask_clbl[lm]_[lr].segbits .PHONY: database pushdb run clean diff --git a/fuzzers/056-rempips/Makefile b/fuzzers/056-rempips/Makefile index f24f5df5..09d27498 100644 --- a/fuzzers/056-rempips/Makefile +++ b/fuzzers/056-rempips/Makefile @@ -1,61 +1,2 @@ -# WARNING: N cannot be reduced or -m will always fail -N := 10 -SPECIMENS := $(addprefix build/specimen_,$(shell seq -f '%03.0f' $(N))) -SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS)) - -database: $(SPECIMENS_OK) - ${XRAY_SEGMATCH} -m 5 -M 15 -o build/segbits_int_l.db $(addsuffix /segdata_int_l.txt,$(SPECIMENS)) - ${XRAY_SEGMATCH} -m 5 -M 15 -o build/segbits_int_r.db $(addsuffix /segdata_int_r.txt,$(SPECIMENS)) - -pushdb: - ${XRAY_DBFIXUP} --db-root . --clb-int - ${XRAY_MERGEDB} int_l build/segbits_int_l.db - ${XRAY_MERGEDB} int_r build/segbits_int_r.db - -$(SPECIMENS_OK): build/todo.txt - mkdir -p build - bash ${XRAY_DIR}/utils/top_generate.sh $(subst /OK,,$@) - touch $@ - -build/pips_int_l.txt: piplist.tcl - mkdir -p build - cd build && vivado -mode batch -source ../piplist.tcl - -# Used 1) to see if we are done 2) pips to try in generate.tcl -build/todo.txt: build/pips_int_l.txt - #python3 maketodo.py --no-strict | sort -R | head -n10 > build/todo.txt.tmp - python3 maketodo.py >build/todo_all.txt - cat build/todo_all.txt | sort -R | head -n10 > build/todo.txt.tmp - mv build/todo.txt.tmp build/todo.txt - - -# XXX: conider moving to script -run: - \ - set -ex; \ - make clean; \ - mkdir -p todo; \ - while \ - make cleanprj; \ - make build/todo.txt || exit 1; \ - test -s build/todo.txt; \ - do \ - i=$$((i+1)); \ - cp build/todo.txt todo/$${i}.txt; \ - cp build/todo_all.txt todo/$${i}_all.txt; \ - if make database; then \ - make pushdb; \ - fi; \ - done; \ - true - touch run.ok - -clean: - rm -rf build run.ok todo - -# Remove iteration specific files, but keep piplist.tcl output -cleanprj: - rm -rf build/specimen_* build/todo.txt build/*.db - -.PHONY: database pushdb run clean cleanprj +include ../int_loop.mk diff --git a/fuzzers/056-rempips/generate.tcl b/fuzzers/056-rempips/generate.tcl index 286a3afd..4f0c91b7 100644 --- a/fuzzers/056-rempips/generate.tcl +++ b/fuzzers/056-rempips/generate.tcl @@ -1,6 +1,8 @@ +source "$::env(XRAY_DIR)/utils/utils.tcl" + create_project -force -part $::env(XRAY_PART) design design -read_verilog ../../top.v +read_verilog $::env(FUZDIR)/top.v synth_design -top top set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i] @@ -19,8 +21,6 @@ route_design # write_checkpoint -force design.dcp -source "$::env(XRAY_DIR)/utils/utils.tcl" - set fp [open "../todo.txt" r] set todo_lines {} for {gets $fp line} {$line != ""} {gets $fp line} { diff --git a/fuzzers/int_loop.mk b/fuzzers/int_loop.mk new file mode 100644 index 00000000..b91f4670 --- /dev/null +++ b/fuzzers/int_loop.mk @@ -0,0 +1,63 @@ +# WARNING: N cannot be reduced or -m will always fail +N := 10 +SPECIMENS := $(addprefix build/specimen_,$(shell seq -f '%03.0f' $(N))) +SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS)) +# Individual fuzzer directory, such as ~/prjxray/fuzzers/010-lutinit +export FUZDIR=$(shell pwd) + +database: $(SPECIMENS_OK) + ${XRAY_SEGMATCH} -m 5 -M 15 -o build/segbits_int_l.db $(addsuffix /segdata_int_l.txt,$(SPECIMENS)) + ${XRAY_SEGMATCH} -m 5 -M 15 -o build/segbits_int_r.db $(addsuffix /segdata_int_r.txt,$(SPECIMENS)) + +pushdb: + ${XRAY_DBFIXUP} --db-root . --clb-int + ${XRAY_MERGEDB} int_l build/segbits_int_l.db + ${XRAY_MERGEDB} int_r build/segbits_int_r.db + +$(SPECIMENS_OK): build/todo.txt + mkdir -p build + bash ${XRAY_DIR}/utils/top_generate.sh $(subst /OK,,$@) + touch $@ + +build/pips_int_l.txt: $(FUZDIR)/../piplist.tcl + mkdir -p build + cd build && vivado -mode batch -source $(FUZDIR)/../piplist.tcl + +# Used 1) to see if we are done 2) pips to try in generate.tcl +build/todo.txt: build/pips_int_l.txt maketodo.py + #python3 maketodo.py --no-strict | sort -R | head -n10 > build/todo.txt.tmp + python3 maketodo.py >build/todo_all.txt + cat build/todo_all.txt | sort -R | head -n10 > build/todo.txt.tmp + mv build/todo.txt.tmp build/todo.txt + + +# XXX: conider moving to script +run: + \ + set -ex; \ + make clean; \ + mkdir -p todo; \ + while \ + make cleanprj; \ + make build/todo.txt || exit 1; \ + test -s build/todo.txt; \ + do \ + i=$$((i+1)); \ + cp build/todo.txt todo/$${i}.txt; \ + cp build/todo_all.txt todo/$${i}_all.txt; \ + if make database; then \ + make pushdb; \ + fi; \ + done; \ + true + touch run.ok + +clean: + rm -rf build run.ok todo + +# Remove iteration specific files, but keep piplist.tcl output +cleanprj: + rm -rf build/specimen_* build/todo.txt build/*.db + +.PHONY: database pushdb run clean cleanprj + diff --git a/fuzzers/056-rempips/piplist.tcl b/fuzzers/piplist.tcl similarity index 97% rename from fuzzers/056-rempips/piplist.tcl rename to fuzzers/piplist.tcl index 0086ab9b..b5db80f8 100644 --- a/fuzzers/056-rempips/piplist.tcl +++ b/fuzzers/piplist.tcl @@ -1,6 +1,6 @@ create_project -force -part $::env(XRAY_PART) piplist piplist -read_verilog ../top.v +read_verilog $::env(FUZDIR)/top.v synth_design -top top set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i] diff --git a/utils/utils.tcl b/utils/utils.tcl index 85315063..9c7a2413 100644 --- a/utils/utils.tcl +++ b/utils/utils.tcl @@ -1,19 +1,36 @@ - proc route_via {net nodes} { + # Route a simple source to dest net via one or more intermediate nodes + # the nodes do not have have to be directly reachable from each other + # net: net name string + # nodes: list of node or wires strings? + # Returns 1 on success (previously would silently failed with antenna nets) + set net [get_nets $net] + # fixed_route: list of nodes in the full route + # Begins at implicit node set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] + # Implicit end node. Route it at the end lappend nodes [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] puts "" puts "Routing net $net:" foreach to_node $nodes { + # convert wire string to node object set to_node [get_nodes -of_objects [get_wires $to_node]] + # Start at the last point set from_node [lindex $fixed_route end] + # Make vivado do the hard work set route [find_routing_path -quiet -from $from_node -to $to_node] + # TODO: check for this if {$route == ""} { - puts " $from_node -> $to_node: no route found - assuming direct PIP" - lappend fixed_route $to_node + # This can also happen if you try to route to a node already in the route + if { [ lsearch $route $to_node ] >= 0 } { + puts "WARNING: route_via loop. $to_node is already in the path, ignoring" + } else { + puts " $from_node -> $to_node: no route found - assuming direct PIP" + lappend fixed_route $to_node + } } { puts " $from_node -> $to_node: $route" set fixed_route [concat $fixed_route [lrange $route 1 end]] @@ -21,8 +38,17 @@ proc route_via {net nodes} { set_property -quiet FIXED_ROUTE $fixed_route $net } + # Earlier check should catch this now + set status [get_property ROUTE_STATUS $net] + if { $status != "ROUTED" } { + error "failed to route net $net, status $status, route: $fixed_route" + # maybe warn and fail? + # return 0 + } + set_property -quiet FIXED_ROUTE $fixed_route $net puts "" + return 1 } proc tile_wire_pairs {tile1 tile2} {