From 7bdf3329d86d5f0a2b6c99e079f91812c09f5787 Mon Sep 17 00:00:00 2001
From: Alessandro Comodi <acomodi@antmicro.com>
Date: Fri, 19 Feb 2021 14:10:14 +0100
Subject: [PATCH] 071-ppips: add gtp-related ppips

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
---
 fuzzers/071-ppips/generate.tcl | 62 ++++++++++++++++++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/fuzzers/071-ppips/generate.tcl b/fuzzers/071-ppips/generate.tcl
index b1f1faa0..2c92afd6 100644
--- a/fuzzers/071-ppips/generate.tcl
+++ b/fuzzers/071-ppips/generate.tcl
@@ -146,6 +146,50 @@ proc write_pss_ppips_db {filename tile} {
     }
 }
 
+proc write_gtp_channel_ppips_db {filename tile tile_suffix} {
+    set fp [open $filename "w"]
+    set tile [get_tiles $tile]
+    set tile_type [get_property TILE_TYPE $tile]
+
+    foreach pip [get_pips -of_objects $tile] {
+        set dst_wire [get_wires -downhill -of_objects $pip]
+        if {[get_pips -uphill -of_objects [get_nodes -of_objects $dst_wire]] == $pip} {
+            set src_wire [get_wires -uphill -of_objects $pip]
+
+            if {![regexp "IMUX" $src_wire] && ![regexp "GTPE2_CTRL" $src_wire] && ![regexp "GTPE2_CLK" $src_wire]} {
+                continue
+            }
+
+            puts $fp "${tile_type}${tile_suffix}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
+        }
+    }
+
+    close $fp
+}
+
+proc write_gtp_int_interface_ppips_db {filename tile} {
+    set fp [open $filename "w"]
+    set tile [get_tiles $tile]
+    set tile_type [get_property TILE_TYPE $tile]
+
+    foreach pip [get_pips -of_objects $tile] {
+        set dst_wire [get_wires -downhill -of_objects $pip]
+        set src_wire [get_wires -uphill -of_objects $pip]
+
+        if {![regexp "IMUX_OUT" $dst_wire]} {
+            continue
+        }
+
+        if {[regexp "DELAY" $src_wire]} {
+            continue
+        }
+
+        puts $fp "${tile_type}.[regsub {.*/} $dst_wire ""].[regsub {.*/} $src_wire ""] always"
+    }
+
+    close $fp
+}
+
 foreach tile_type {CLBLM_L CLBLM_R CLBLL_L CLBLL_R} {
     set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
     if {[llength $tiles] != 0} {
@@ -202,3 +246,21 @@ foreach tile_type {PSS0 PSS1 PSS2 PSS3 PSS4 INT_INTERFACE_PSS_L} {
         write_pss_ppips_db "ppips_[string tolower $tile_type].db" $tile
     }
 }
+
+foreach tile_type {GTP_CHANNEL_0 GTP_CHANNEL_1 GTP_CHANNEL_2 GTP_CHANNEL_3 GTP_COMMON} {
+    set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
+    if {[llength $tiles] != 0} {
+        set tile [lindex $tiles 0]
+        write_gtp_channel_ppips_db "ppips_[string tolower $tile_type].db" $tile ""
+        write_gtp_channel_ppips_db "ppips_[string tolower $tile_type]_mid_left.db" $tile "_MID_LEFT"
+        write_gtp_channel_ppips_db "ppips_[string tolower $tile_type]_mid_right.db" $tile "_MID_RIGHT"
+    }
+}
+
+foreach tile_type {GTP_INT_INTERFACE} {
+    set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
+    if {[llength $tiles] != 0} {
+        set tile [lindex $tiles 0]
+        write_gtp_int_interface_ppips_db "ppips_[string tolower $tile_type].db" $tile
+    }
+}