From 5c829daa8ca2661a08505a6b0a286e4eba7f5d9d Mon Sep 17 00:00:00 2001 From: Alessandro Comodi Date: Tue, 14 Jan 2020 17:04:02 +0100 Subject: [PATCH] 005-tilegrid: fixed some over-specific settings in generate_full Also added specimens to make some rquired fuzzers find all necessary features Signed-off-by: Alessandro Comodi --- fuzzers/005-tilegrid/generate_full.py | 13 ++++--------- fuzzers/005-tilegrid/hclk_cmt/Makefile | 2 +- fuzzers/005-tilegrid/hclk_ioi/Makefile | 2 +- fuzzers/005-tilegrid/pll/Makefile | 2 +- settings/artix200t.sh | 2 ++ settings/artix50t.sh | 2 ++ settings/artix7.sh | 2 ++ settings/kintex7.sh | 2 ++ settings/zynq7.sh | 2 ++ 9 files changed, 17 insertions(+), 12 deletions(-) diff --git a/fuzzers/005-tilegrid/generate_full.py b/fuzzers/005-tilegrid/generate_full.py index e88ca15e..e0b54b04 100644 --- a/fuzzers/005-tilegrid/generate_full.py +++ b/fuzzers/005-tilegrid/generate_full.py @@ -395,15 +395,10 @@ def propagate_IOI_Y9(database, tiles_by_grid): higher than the rest, just like for some of the SING tiles. """ - arch = os.getenv('XRAY_DATABASE') - if arch in 'artix7': - tiles = ['RIOI3_X43Y9', 'LIOI3_X0Y9'] - elif arch in 'kintex7': - tiles = ['LIOI3_X0Y9'] - elif arch in 'zynq7': - tiles = ['RIOI3_X31Y9'] - else: - assert False, "Unsupported architecture" + ioi_tiles = os.getenv('XRAY_IOI3_TILES') + + assert ioi_tiles is not None, "XRAY_IOI3_TILES env variable not set" + tiles = ioi_tiles.split(" ") for tile in tiles: prev_tile = tiles_by_grid[( diff --git a/fuzzers/005-tilegrid/hclk_cmt/Makefile b/fuzzers/005-tilegrid/hclk_cmt/Makefile index c6172fe8..8aa2699d 100644 --- a/fuzzers/005-tilegrid/hclk_cmt/Makefile +++ b/fuzzers/005-tilegrid/hclk_cmt/Makefile @@ -1,4 +1,4 @@ -N ?= 5 +N ?= 10 GENERATE_ARGS?="--oneval 1 --design params.csv --dword 5 --dframe 1C" include ../fuzzaddr/common.mk diff --git a/fuzzers/005-tilegrid/hclk_ioi/Makefile b/fuzzers/005-tilegrid/hclk_ioi/Makefile index 1e616a32..3f9f5e2a 100644 --- a/fuzzers/005-tilegrid/hclk_ioi/Makefile +++ b/fuzzers/005-tilegrid/hclk_ioi/Makefile @@ -1,4 +1,4 @@ -N ?= 5 +N ?= 10 GENERATE_ARGS?="--oneval 1 --design params.csv --dword 0 --dframe 21" include ../fuzzaddr/common.mk diff --git a/fuzzers/005-tilegrid/pll/Makefile b/fuzzers/005-tilegrid/pll/Makefile index 0d8e4d19..0ff5ced3 100644 --- a/fuzzers/005-tilegrid/pll/Makefile +++ b/fuzzers/005-tilegrid/pll/Makefile @@ -1,3 +1,3 @@ -N ?= 5 +N ?= 10 GENERATE_ARGS?="--oneval 1 --design params.csv --dframe 1C --dword 23" include ../fuzzaddr/common.mk diff --git a/settings/artix200t.sh b/settings/artix200t.sh index ea58e36d..392f00c4 100644 --- a/settings/artix200t.sh +++ b/settings/artix200t.sh @@ -8,6 +8,8 @@ export XRAY_ROI_TILEGRID="SLICE_X0Y0:SLICE_X163Y249 RAMB18_X0Y0:RAMB18_X8Y99 RAM export XRAY_EXCLUDE_ROI_TILEGRID="SLICE_X82Y200:SLICE_X83Y249 SLICE_X82Y0:SLICE_X83Y49" +export XRAY_IOI3_TILES="RIOI3_X105Y9 LIOI3_X0Y9" + export XRAY_PIN_00="R26" export XRAY_PIN_01="P26" export XRAY_PIN_02="N26" diff --git a/settings/artix50t.sh b/settings/artix50t.sh index 726fb337..852f0299 100644 --- a/settings/artix50t.sh +++ b/settings/artix50t.sh @@ -8,6 +8,8 @@ export XRAY_ROI_TILEGRID="SLICE_X0Y0:SLICE_X65Y99 SLICE_X0Y100:SLICE_X57Y149 RAM export XRAY_EXCLUDE_ROI_TILEGRID="" +export XRAY_IOI3_TILES="LIOI3_X0Y9 RIOI3_X43Y9" + export XRAY_PIN_00="E22" export XRAY_PIN_01="D22" export XRAY_PIN_02="E21" diff --git a/settings/artix7.sh b/settings/artix7.sh index a6322781..805cee9f 100644 --- a/settings/artix7.sh +++ b/settings/artix7.sh @@ -8,6 +8,8 @@ export XRAY_ROI_TILEGRID="SLICE_X0Y0:SLICE_X65Y99 SLICE_X0Y100:SLICE_X57Y149 RAM export XRAY_EXCLUDE_ROI_TILEGRID="" +export XRAY_IOI3_TILES="LIOI3_X0Y9 RIOI3_X43Y9" + # These settings must remain in sync export XRAY_ROI="SLICE_X0Y100:SLICE_X35Y149 RAMB18_X0Y40:RAMB18_X0Y59 RAMB36_X0Y20:RAMB36_X0Y29 DSP48_X0Y40:DSP48_X0Y59 IOB_X0Y100:IOB_X0Y149" # Most of CMT X0Y2. diff --git a/settings/kintex7.sh b/settings/kintex7.sh index a2a66ea0..1ec6b199 100644 --- a/settings/kintex7.sh +++ b/settings/kintex7.sh @@ -7,6 +7,8 @@ export XRAY_ROI_TILEGRID="SLICE_X0Y50:SLICE_X19Y99 DSP48_X0Y20:DSP48_X0Y39 RAMB1 export XRAY_EXCLUDE_ROI_TILEGRID="" +export XRAY_IOI3_TILES="LIOI3_X0Y9" + # These settings must remain in sync export XRAY_ROI="SLICE_X0Y50:SLICE_X19Y99 DSP48_X0Y20:DSP48_X0Y39 RAMB18_X0Y20:RAMB18_X0Y39 RAMB36_X0Y10:RAMB36_X0Y19 IOB_X0Y50:IOB_X0Y99" # Part of CMT X0Y1 diff --git a/settings/zynq7.sh b/settings/zynq7.sh index 97a9b826..4d1895f4 100644 --- a/settings/zynq7.sh +++ b/settings/zynq7.sh @@ -7,6 +7,8 @@ export XRAY_ROI_TILEGRID="SLICE_X0Y0:SLICE_X43Y99 RAMB18_X0Y0:RAMB18_X2Y39 RAMB3 export XRAY_EXCLUDE_ROI_TILEGRID="" +export XRAY_IOI3_TILES="RIOI3_X31Y9" + # These settings must remain in sync export XRAY_ROI="SLICE_X00Y50:SLICE_X43Y99 RAMB18_X0Y20:RAMB18_X2Y39 RAMB36_X0Y10:RAMB36_X2Y19 IOB_X0Y50:IOB_X0Y99"