From 5b0a1f7cb519dd57f0ed88f3033500460839ee07 Mon Sep 17 00:00:00 2001 From: John McMaster Date: Fri, 19 Jan 2018 14:02:51 -0800 Subject: [PATCH] roi_harness: example clk hack Signed-off-by: John McMaster --- minitests/roi_harness/README.txt | 6 +++--- minitests/roi_harness/runme.sh | 7 +++++++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/minitests/roi_harness/README.txt b/minitests/roi_harness/README.txt index 12485912..2f24f2da 100644 --- a/minitests/roi_harness/README.txt +++ b/minitests/roi_harness/README.txt @@ -14,6 +14,6 @@ To target Arty A7 you should source the artix DB environment script then source To build the baseline harness: ./runme.sh -To build a sample design using the harness: -XRAY_ROIV=roi_inv.v XRAY_FIXED_XDC=out_xc7a35tcpg236-1_BASYS3-SWBUT_roi_basev/fixed.xdc ./runme.sh - +To build a sample Vivado design using the harness: +XRAY_ROIV=roi_inv.v XRAY_FIXED_XDC=out_xc7a35tcpg236-1_BASYS3-SWBUT_roi_basev/fixed_noclk.xdc ./runme.sh +Note: this was intended for verification only and not as an end user flow (they should use SymbiFlow) diff --git a/minitests/roi_harness/runme.sh b/minitests/roi_harness/runme.sh index a15ab84e..4fa2c200 100755 --- a/minitests/roi_harness/runme.sh +++ b/minitests/roi_harness/runme.sh @@ -10,4 +10,11 @@ ${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit ${XRAY_SEGPRINT} -zd design.bits >design.segp ${XRAY_DIR}/tools/segprint2fasm.py design.segp design.fasm ${XRAY_DIR}/tools/fasm2frame.py design.fasm design.frm +# Hack to get around weird clock error related to clk net not found +# Remove following lines: +#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] +#set_property FIXED_ROUTE { { CLK_BUFG_BUFGCTRL0_O CLK_BUFG_CK_GCLK0 ... CLK_L1 CLBLM_M_CLK } } [get_nets clk_net] +if [ -f fixed.xdc ] ; then + cat fixed.xdc |fgrep -v 'CLOCK_DEDICATED_ROUTE FALSE' |fgrep -v 'set_property FIXED_ROUTE { { CLK_BUFG_BUFGCTRL0_O' >fixed_noclk.xdc +fi popd