diff --git a/fuzzers/005-tilegrid/Makefile b/fuzzers/005-tilegrid/Makefile index c801bb37..f99d969a 100644 --- a/fuzzers/005-tilegrid/Makefile +++ b/fuzzers/005-tilegrid/Makefile @@ -8,6 +8,7 @@ TILEGRID_TDB_DEPENDENCIES += pll/build/segbits_tilegrid.tdb TILEGRID_TDB_DEPENDENCIES += monitor/build/segbits_tilegrid.tdb TILEGRID_TDB_DEPENDENCIES += bram/build/segbits_tilegrid.tdb TILEGRID_TDB_DEPENDENCIES += bram_block/build/segbits_tilegrid.tdb +TILEGRID_TDB_DEPENDENCIES += bram_int/build/segbits_tilegrid.tdb TILEGRID_TDB_DEPENDENCIES += clb/build/segbits_tilegrid.tdb TILEGRID_TDB_DEPENDENCIES += clb_int/build/segbits_tilegrid.tdb GENERATE_FULL_ARGS= @@ -61,6 +62,9 @@ bram/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json bram_block/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json cd bram_block && $(MAKE) +bram_int/build/segbits_tilegrid.tdb: build/basicdb/tilegrid.json + cd bram_int && $(MAKE) + build/tilegrid_tdb.json: add_tdb.py $(TILEGRID_TDB_DEPENDENCIES) python3 add_tdb.py \ --fn-in build/basicdb/tilegrid.json \ @@ -87,6 +91,7 @@ clean: cd ps7_int && $(MAKE) clean cd bram && $(MAKE) clean cd bram_block && $(MAKE) clean + cd bram_int && $(MAKE) clean cd monitor && $(MAKE) clean .PHONY: database pushdb clean run diff --git a/fuzzers/005-tilegrid/add_tdb.py b/fuzzers/005-tilegrid/add_tdb.py index f9253098..5004de93 100644 --- a/fuzzers/005-tilegrid/add_tdb.py +++ b/fuzzers/005-tilegrid/add_tdb.py @@ -1,8 +1,8 @@ #!/usr/bin/env python3 +from __future__ import print_function from prjxray import util import json -import os import util as localutil @@ -65,13 +65,12 @@ def run(fn_in, fn_out, verbose=False): ("clb/build/segbits_tilegrid.tdb", 36, 2), ("clb_int/build/segbits_tilegrid.tdb", int_frames, int_words), ("iob_int/build/segbits_tilegrid.tdb", int_frames, int_words), + ("bram_int/build/segbits_tilegrid.tdb", int_frames, int_words), ] for (tdb_fn, frames, words) in tdb_fns: for (tile, frame, wordidx) in load_db(tdb_fn): tilej = database[tile] - bitsj = tilej['bits'] - bt = util.addr2btype(frame) verbose and print("Add %s %08X_%03u" % (tile, frame, wordidx)) localutil.add_tile_bits(tile, tilej, frame, wordidx, frames, words) diff --git a/fuzzers/005-tilegrid/bram_int/Makefile b/fuzzers/005-tilegrid/bram_int/Makefile new file mode 100644 index 00000000..02f7dc56 --- /dev/null +++ b/fuzzers/005-tilegrid/bram_int/Makefile @@ -0,0 +1,4 @@ +N ?= 30 +GENERATE_ARGS?="--oneval 0 --design params.csv --dword 1 --dframe 15" +include ../fuzzaddr/common.mk + diff --git a/fuzzers/005-tilegrid/bram_int/generate.tcl b/fuzzers/005-tilegrid/bram_int/generate.tcl new file mode 100644 index 00000000..9e8cab8a --- /dev/null +++ b/fuzzers/005-tilegrid/bram_int/generate.tcl @@ -0,0 +1,19 @@ +source "$::env(XRAY_DIR)/utils/utils.tcl" + +proc run {} { + create_project -force -part $::env(XRAY_PART) design design + read_verilog top.v + synth_design -top top + + set_property CFGBVS VCCO [current_design] + set_property CONFIG_VOLTAGE 3.3 [current_design] + set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] + + place_design + route_design + + write_checkpoint -force design.dcp + write_bitstream -force design.bit +} + +run diff --git a/fuzzers/005-tilegrid/bram_int/top.py b/fuzzers/005-tilegrid/bram_int/top.py new file mode 100644 index 00000000..3fc0081b --- /dev/null +++ b/fuzzers/005-tilegrid/bram_int/top.py @@ -0,0 +1,185 @@ +import os +import random +import itertools +random.seed(int(os.getenv("SEED"), 16)) +from prjxray import util +from prjxray.db import Database + + +def gen_brams(): + db = Database(util.get_db_root()) + grid = db.grid() + for tile_name in sorted(grid.tiles()): + loc = grid.loc_of_tilename(tile_name) + gridinfo = grid.gridinfo_at_loc(loc) + + sites = [] + for site_name, site_type in gridinfo.sites.items(): + if site_type in ['RAMB18E1', 'FIFO18E1']: + sites.append(site_name) + + sites.sort() + + if len(sites) == 0: + continue + + if gridinfo.tile_type[-1] == 'L': + int_grid_x = loc.grid_x + 2 + int_tile_type = 'INT_L' + else: + int_grid_x = loc.grid_x - 2 + int_tile_type = 'INT_R' + + int_tile_locs = [ + (int_grid_x, loc.grid_y), + (int_grid_x, loc.grid_y-1), + (int_grid_x, loc.grid_y-2), + (int_grid_x, loc.grid_y-3), + (int_grid_x, loc.grid_y-4), + ] + + int_tiles = [] + for int_tile_loc in int_tile_locs: + int_gridinfo = grid.gridinfo_at_loc(int_tile_loc) + assert int_gridinfo.tile_type == int_tile_type, (int_gridinfo.tile_type, int_tile_type) + + int_tiles.append(grid.tilename_at_loc(int_tile_loc)) + + yield tile_name, sites, int_tiles + + +def write_params(params): + pinstr = 'tile,val\n' + for tile, (val,) in sorted(params.items()): + pinstr += '%s,%s\n' % (tile, val) + open('params.csv', 'w').write(pinstr) + + +def run(): + print( + ''' +module top(); + ''') + + params = {} + + sites = list(gen_brams()) + fuzz_iter = iter(util.gen_fuzz_states(len(sites)*5)) + for tile_name, bram_sites, int_tiles in sites: + # Each BRAM tile has 5 INT tiles. + # The following feature is used to toggle a one PIP in each INT tile + # + # For BRAM_L_X6Y0, there are the following INT tiles and the feature + # to toggle + # + # - INT_L_X6Y0, tie bram_sites[0].DIADI[2] = 0, toggle bram_sites[0].DIADI[3] + # - INT_L_X6Y1, tie bram_sites[1].ADDRBWRADDR[7] = 0, toggle bram_sites[1].ADDRBWRADDR[10] + # - INT_L_X6Y2, tie bram_sites[1].ADDRARDADDR[9] = 0, toggle bram_sites[1].ADDRBWRADDR[9] + # - INT_L_X6Y3, tie bram_sites[1].ADDRBWRADDR[4] = 0, toggle bram_sites[1].ADDRBWRADDR[13] + # - INT_L_X6Y4, tie bram_sites[1].DIBDI[15] = 0, toggle bram_sites[1].DIADI[7] + (b0_diadi3, b1_wraddr10, b1_wraddr9, b1_wraddr13, b1_diadi7) = itertools.islice(fuzz_iter, 5) + params[int_tiles[0]] = (b0_diadi3,) + params[int_tiles[1]] = (b1_wraddr10,) + params[int_tiles[2]] = (b1_wraddr9,) + params[int_tiles[3]] = (b1_wraddr13,) + params[int_tiles[4]] = (b1_diadi7,) + + print( + ''' + wire [15:0] {bram_site0}_diadi; + wire [15:0] {bram_site0}_dibdi; + wire [13:0] {bram_site0}_wraddr; + + wire [15:0] {bram_site1}_diadi; + wire [15:0] {bram_site1}_dibdi; + wire [7:0] {bram_site1}_webwe; + wire [13:0] {bram_site1}_rdaddr; + wire [13:0] {bram_site1}_wraddr; + + // INT 0 + assign {bram_site0}_diadi[2] = 0; + assign {bram_site0}_diadi[3] = {b0_diadi3}; + + // INT 1 + assign {bram_site1}_wraddr[7] = 0; + assign {bram_site1}_wraddr[10] = {b1_wraddr10}; + + // INT 2 + assign {bram_site1}_rdaddr[9] = 0; + assign {bram_site1}_wraddr[9] = {b1_wraddr9}; + + // INT 3 + assign {bram_site1}_wraddr[4] = 0; + assign {bram_site1}_wraddr[13] = {b1_wraddr13}; + + // INT 4 + assign {bram_site1}_dibdi[15] = 0; + assign {bram_site1}_diadi[7] = {b1_diadi7}; + + (* KEEP, DONT_TOUCH, LOC = "{bram_site0}" *) + RAMB18E1 #( + ) bram_{bram_site0} ( + .CLKARDCLK(), + .CLKBWRCLK(), + .ENARDEN(), + .ENBWREN(), + .REGCEAREGCE(), + .REGCEB(), + .RSTRAMARSTRAM(), + .RSTRAMB(), + .RSTREGARSTREG(), + .RSTREGB(), + .ADDRARDADDR(), + .ADDRBWRADDR({bram_site0}_wraddr), + .DIADI({bram_site0}_diadi), + .DIBDI({bram_site0}_dibdi), + .DIPADIP(), + .DIPBDIP(), + .WEA(), + .WEBWE(), + .DOADO(), + .DOBDO(), + .DOPADOP(), + .DOPBDOP()); + + (* KEEP, DONT_TOUCH, LOC = "{bram_site1}" *) + RAMB18E1 #( + ) bram_{bram_site1} ( + .CLKARDCLK(), + .CLKBWRCLK(), + .ENARDEN(), + .ENBWREN(), + .REGCEAREGCE(), + .REGCEB(), + .RSTRAMARSTRAM(), + .RSTRAMB(), + .RSTREGARSTREG(), + .RSTREGB(), + .ADDRARDADDR({bram_site1}_rdaddr), + .ADDRBWRADDR({bram_site1}_wraddr), + .DIADI({bram_site1}_diadi), + .DIBDI({bram_site1}_dibdi), + .DIPADIP(), + .DIPBDIP(), + .WEA(), + .WEBWE({bram_site1}_webwe), + .DOADO(), + .DOBDO(), + .DOPADOP(), + .DOPBDOP()); +'''.format( + bram_site0=bram_sites[0], + bram_site1=bram_sites[1], + b0_diadi3=b0_diadi3, + b1_wraddr10=b1_wraddr10, + b1_wraddr9=b1_wraddr9, + b1_wraddr13=b1_wraddr13, + b1_diadi7=b1_diadi7 + )) + + print("endmodule") + write_params(params) + + +if __name__ == '__main__': + run() diff --git a/fuzzers/005-tilegrid/clb_int/top.py b/fuzzers/005-tilegrid/clb_int/top.py index 62be8763..30b23117 100644 --- a/fuzzers/005-tilegrid/clb_int/top.py +++ b/fuzzers/005-tilegrid/clb_int/top.py @@ -34,8 +34,7 @@ def write_params(params): def run(): - print( - ''' + print(''' module top(); ''') @@ -72,7 +71,7 @@ module top(); MUXF8 f8_{0} ( .I0(f7_to_f8_{0}) ); -''' .format(site_name, isone)) +'''.format(site_name, isone)) print("endmodule") write_params(params) diff --git a/fuzzers/005-tilegrid/generate_full.py b/fuzzers/005-tilegrid/generate_full.py index 74795aef..c57fd6f3 100644 --- a/fuzzers/005-tilegrid/generate_full.py +++ b/fuzzers/005-tilegrid/generate_full.py @@ -58,6 +58,7 @@ def make_tiles_by_grid(tiles): return tiles_by_grid + def add_int_bits(database, tile, baseaddr, offset): """ Add INT bits for given tile. @@ -66,8 +67,8 @@ def add_int_bits(database, tile, baseaddr, offset): return localutil.add_tile_bits( - tile, database[tile], baseaddr, offset, - frames=28, words=2, height=2) + tile, database[tile], baseaddr, offset, frames=28, words=2, height=2) + def add_adjacent_int_tiles(database, tiles_by_grid, verbose=False): ''' @@ -81,7 +82,8 @@ def add_adjacent_int_tiles(database, tiles_by_grid, verbose=False): grid_x = database[inttile]["grid_x"] grid_y = database[inttile]["grid_y"] - framebase = int(database[parent_tile]['bits']['CLB_IO_CLK']['baseaddr'], 0) + framebase = int( + database[parent_tile]['bits']['CLB_IO_CLK']['baseaddr'], 0) parent_wordbase = database[parent_tile]['bits']['CLB_IO_CLK']['offset'] for dst_tile, wordbase in localutil.propagate_up_INT( @@ -90,8 +92,7 @@ def add_adjacent_int_tiles(database, tiles_by_grid, verbose=False): dst_y = dst_tile['grid_y'] add_int_bits( - database, tiles_by_grid[(dst_x, dst_y)], framebase, - wordbase) + database, tiles_by_grid[(dst_x, dst_y)], framebase, wordbase) verbose and print('') for tile_name, tile_data in database.items(): diff --git a/fuzzers/005-tilegrid/iob_int/Makefile b/fuzzers/005-tilegrid/iob_int/Makefile index cd564940..885ee4c2 100644 --- a/fuzzers/005-tilegrid/iob_int/Makefile +++ b/fuzzers/005-tilegrid/iob_int/Makefile @@ -1,3 +1,3 @@ N ?= 35 -GENERATE_ARGS?="--oneval 0 --design params.csv --dframe 14 --dword 1" +GENERATE_ARGS?="--oneval 0 --design params.csv --dframe 15 --dword 1" include ../fuzzaddr/common.mk diff --git a/fuzzers/005-tilegrid/iob_int/top.py b/fuzzers/005-tilegrid/iob_int/top.py index 571ac7df..a2afb76c 100644 --- a/fuzzers/005-tilegrid/iob_int/top.py +++ b/fuzzers/005-tilegrid/iob_int/top.py @@ -43,8 +43,8 @@ def gen_sites(): int_tile_type = 'INT_R' int_tile_locs = [ - (int_grid_x, loc.grid_y), - ] + (int_grid_x, loc.grid_y), + ] pad_gridinfo = grid.gridinfo_at_loc((pad_grid_x, loc.grid_y)) pad_sites = sorted(pad_gridinfo.sites.keys()) @@ -52,12 +52,15 @@ def gen_sites(): if not gridinfo.tile_type.endswith("_SING"): int_tile_locs.append((int_grid_x, loc.grid_y - 1)) - assert len(sites) == len(int_tile_locs), (tile_name, sites, int_tile_locs) + assert len(sites) == len(int_tile_locs), ( + tile_name, sites, int_tile_locs) assert len(sites) == len(pad_sites), (sites, pad_sites) - for site_name, pad_site, int_tile_loc in zip(sites, pad_sites, int_tile_locs): + for site_name, pad_site, int_tile_loc in zip(sites, pad_sites, + int_tile_locs): int_tile_name = grid.tilename_at_loc(int_tile_loc) - assert int_tile_name.startswith(int_tile_type), (int_tile_name, site_name, int_tile_loc) + assert int_tile_name.startswith(int_tile_type), ( + int_tile_name, site_name, int_tile_loc) yield int_tile_name, site_name, pad_site @@ -85,8 +88,8 @@ module top(input wire [`N_DI-1:0] di); params = {} - for idx, ((tile_name, site_name, pad_site_name), isone) in enumerate(zip(sites, - util.gen_fuzz_states(len(sites)))): + for idx, ((tile_name, site_name, pad_site_name), isone) in enumerate(zip( + sites, util.gen_fuzz_states(len(sites)))): params[tile_name] = (site_name, isone, pad_site_name, "di[%u]" % idx) # Force HARD0 -> GFAN1 with CNTVALUEIN4 = 0 diff --git a/fuzzers/005-tilegrid/util.py b/fuzzers/005-tilegrid/util.py index 082c4083..68e9bd04 100644 --- a/fuzzers/005-tilegrid/util.py +++ b/fuzzers/005-tilegrid/util.py @@ -11,9 +11,7 @@ def check_frames(addrlist): for addrstr in addrlist: frame = parse_addr(addrstr, get_base_frame=True) frames.add(frame) - assert len(frames) == 1, ( - "More than one base address", map(hex,frames) - ) + assert len(frames) == 1, ("More than one base address", map(hex, frames)) def parse_addr(line, only_frame=False, get_base_frame=False): @@ -122,7 +120,8 @@ def add_tile_bits( assert offset <= 100, (tile_name, offset) # Few rare cases at X=0 for double width tiles split in half => small negative offset - assert offset >= 0 or "IOB" in tile_name, (tile_name, hex(baseaddr), offset) + assert offset >= 0 or "IOB" in tile_name, ( + tile_name, hex(baseaddr), offset) assert 1 <= words <= 101, words assert offset + words <= 101, ( tile_name, offset + words, offset, words, block_type)