diff --git a/minitests/clb_bused/Makefile b/minitests/clb_bused/Makefile
new file mode 100644
index 00000000..c03fb4d1
--- /dev/null
+++ b/minitests/clb_bused/Makefile
@@ -0,0 +1,27 @@
+N := 3
+SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
+SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS))
+
+all:
+	bash runme.sh
+	test -z $(fgrep CRITICAL vivado.log)
+	segprint -z -D design.bits  >design.txt
+
+database: $(SPECIMENS_OK)
+	${XRAY_SEGMATCH} -o seg_clblx.segbits $(addsuffix /segdata_clbl[lm]_[lr].txt,$(SPECIMENS))
+
+pushdb:
+	${XRAY_MERGEDDB} clbll_l seg_clblx.segbits
+	${XRAY_MERGEDDB} clbll_r seg_clblx.segbits
+	${XRAY_MERGEDDB} clblm_l seg_clblx.segbits
+	${XRAY_MERGEDDB} clblm_r seg_clblx.segbits
+
+$(SPECIMENS_OK):
+	bash generate.sh $(subst /OK,,$@)
+	touch $@
+
+clean:
+	rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit
+
+.PHONY: database pushdb clean
+
diff --git a/minitests/clb_bused/README.txt b/minitests/clb_bused/README.txt
new file mode 100644
index 00000000..f41c0d58
--- /dev/null
+++ b/minitests/clb_bused/README.txt
@@ -0,0 +1,11 @@
+Tests for BUSED bit
+However got this
+
+seg SEG_CLBLL_R_X13Y101
+bit 30_24
+
+seg SEG_CLBLL_R_X13Y100
+bit 30_24
+
+which seems to indicate there is no such bit, or it was rolled into PIP stuff already
+
diff --git a/minitests/clb_bused/runme.sh b/minitests/clb_bused/runme.sh
new file mode 100755
index 00000000..6ffc4043
--- /dev/null
+++ b/minitests/clb_bused/runme.sh
@@ -0,0 +1,8 @@
+#!/bin/bash
+
+set -ex
+# rm -f vivado*.log vivado*.jou
+vivado -mode batch -source runme.tcl
+test -z $(fgrep CRITICAL vivado.log)
+${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit
+#${XRAY_SEGPRINT} design.bits SLICE_X16Y100 SLICE_X16Y101 SLICE_X16Y102 SLICE_X16Y103
diff --git a/minitests/clb_bused/runme.tcl b/minitests/clb_bused/runme.tcl
new file mode 100644
index 00000000..86162f92
--- /dev/null
+++ b/minitests/clb_bused/runme.tcl
@@ -0,0 +1,26 @@
+create_project -force -part $::env(XRAY_PART) design design
+read_verilog top.v
+synth_design -top top
+
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do]
+
+create_pblock roi
+set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi]
+add_cells_to_pblock [get_pblocks roi] [get_cells roi]
+resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
+
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
+
+place_design
+route_design
+
+write_checkpoint -force design.dcp
+write_bitstream -force design.bit
+
diff --git a/minitests/clb_bused/top.v b/minitests/clb_bused/top.v
new file mode 100644
index 00000000..bb31ff33
--- /dev/null
+++ b/minitests/clb_bused/top.v
@@ -0,0 +1,86 @@
+//move some stuff to minitests/ncy0
+
+module top(input clk, stb, di, output do);
+	localparam integer DIN_N = 256;
+	localparam integer DOUT_N = 256;
+
+	reg [DIN_N-1:0] din;
+	wire [DOUT_N-1:0] dout;
+
+	reg [DIN_N-1:0] din_shr;
+	reg [DOUT_N-1:0] dout_shr;
+
+	always @(posedge clk) begin
+		din_shr <= {din_shr, di};
+		dout_shr <= {dout_shr, din_shr[DIN_N-1]};
+		if (stb) begin
+			din <= din_shr;
+			dout_shr <= dout;
+		end
+	end
+
+	assign do = dout_shr[DOUT_N-1];
+
+	roi roi (
+		.clk(clk),
+		.din(din),
+		.dout(dout)
+	);
+endmodule
+
+module roi(input clk, input [255:0] din, output [255:0] dout);
+    clb_FF clb_FF       (.clk(clk), .din(din[  0 +: 8]), .dout(dout[  0 +: 8]));
+    clb_OUT clb_OUT       (.clk(clk), .din(din[  8 +: 8]), .dout(dout[  8 +: 8]));
+endmodule
+
+
+module clb_FF (input clk, input [7:0] din, output [7:0] dout);
+    wire o6;
+    //assign dout[0] = o6;
+
+	(* LOC="SLICE_X18Y100", BEL="B6LUT", KEEP, DONT_TOUCH *)
+	LUT6 #(
+		.INIT(64'h8000_0000_0000_0001)
+	) lut (
+		.I0(din[0]),
+		.I1(din[1]),
+		.I2(din[2]),
+		.I3(din[3]),
+		.I4(din[4]),
+		.I5(din[5]),
+		.O(o6));
+
+	(* LOC="SLICE_X18Y100", BEL="BFF" *)
+	FDPE ff (
+		.C(clk),
+		.Q(dout[1]),
+		.CE(din[0]),
+		.PRE(din[1]),
+		.D(o6));
+endmodule
+
+module clb_OUT (input clk, input [7:0] din, output [7:0] dout);
+    wire o6;
+    assign dout[0] = o6;
+
+	(* LOC="SLICE_X18Y101", BEL="B6LUT", KEEP, DONT_TOUCH *)
+	LUT6 #(
+		.INIT(64'h8000_0000_0000_0001)
+	) lut (
+		.I0(din[0]),
+		.I1(din[1]),
+		.I2(din[2]),
+		.I3(din[3]),
+		.I4(din[4]),
+		.I5(din[5]),
+		.O(o6));
+
+	(* LOC="SLICE_X18Y101", BEL="BFF" *)
+	FDPE ff (
+		.C(clk),
+		.Q(dout[1]),
+		.CE(din[0]),
+		.PRE(din[1]),
+		.D(o6));
+endmodule
+