From 59082d953048b78d58840b7608961668c831da50 Mon Sep 17 00:00:00 2001 From: Sarah Maddox Date: Wed, 18 Apr 2018 15:18:43 +1000 Subject: [PATCH] Fixes link to non-existent glossary entry. Signed-off-by: Sarah Maddox --- docs/architecture/overview.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/architecture/overview.rst b/docs/architecture/overview.rst index ec66cfb1..4e1a139a 100644 --- a/docs/architecture/overview.rst +++ b/docs/architecture/overview.rst @@ -28,6 +28,6 @@ may be used within a single clock domain, connected to span both clock domains in a horizontal clock row, or connected to global clocks. Clock domains have a fixed height of 50 :term:`interconnect tiles -` centered around the horizontal clock lines (25 above, 25 +` centered around the horizontal clock lines (25 above, 25 below). Various function tiles, such as :term:`CLBs `, are attached to interconnect tiles.