diff --git a/fuzzers/045-hclk-cmt-pips/output_cmt.tcl b/fuzzers/045-hclk-cmt-pips/output_cmt.tcl
index f4d00aff..1ad5c1a0 100644
--- a/fuzzers/045-hclk-cmt-pips/output_cmt.tcl
+++ b/fuzzers/045-hclk-cmt-pips/output_cmt.tcl
@@ -3,7 +3,7 @@ set_property design_mode PinPlanning [current_fileset]
 open_io_design -name io_1
 
 set fp [open "cmt_regions.csv" "w"]
-foreach site_type {MMCME2_ADV PLLE2_ADV BUFMRCE BUFHCE IOB33M BUFR} {
+foreach site_type {MMCME2_ADV PLLE2_ADV BUFMRCE BUFHCE IOB33M IOB18M BUFR} {
     foreach site [get_sites -filter "SITE_TYPE == $site_type"] {
         puts $fp "$site,[get_property CLOCK_REGION $site]"
     }
diff --git a/fuzzers/045-hclk-cmt-pips/top.py b/fuzzers/045-hclk-cmt-pips/top.py
index 0c740d01..5e67b0a2 100644
--- a/fuzzers/045-hclk-cmt-pips/top.py
+++ b/fuzzers/045-hclk-cmt-pips/top.py
@@ -133,8 +133,8 @@ def get_paired_iobs(db, grid, tile_name):
             gridinfo, lr + 'IOB')
 
         for site, site_type in gridinfo.sites.items():
-            if site_type == 'IOB33M':
-                yield tile_name, site
+            if site_type in ['IOB33M', 'IOB18M']:
+                yield tile_name, site, site_type[-3:-1]
 
 
 def check_allowed(mmcm_pll_dir, cmt):
@@ -207,7 +207,7 @@ def main():
             mmcm_pll_only, mmcm_pll_dir))
 
     for tile_name in sorted(hclk_cmt_tiles):
-        for _, site in get_paired_iobs(db, grid, tile_name):
+        for _, site, volt in get_paired_iobs(db, grid, tile_name):
 
             ins.append('input clk_{site}'.format(site=site))
             if check_allowed(mmcm_pll_dir, site_to_cmt[site]):
@@ -220,11 +220,11 @@ def main():
                 """
     (* KEEP, DONT_TOUCH, LOC = "{site}" *)
     wire clock_IBUF_{site};
-    IBUF #( .IOSTANDARD("LVCMOS33") ) ibuf_{site} (
+    IBUF #( .IOSTANDARD("LVCMOS{volt}") ) ibuf_{site} (
         .I(clk_{site}),
         .O(clock_IBUF_{site})
         );
-                    """.format(site=site),
+                    """.format(volt=volt, site=site),
                 file=iobs)
 
     print(