From 4c2b0a539551c7e4fb5c3e6ba601c83139deb9fe Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Wed, 26 Jun 2019 13:19:57 +0200 Subject: [PATCH 1/5] Added minitests for SRLs Signed-off-by: Maciej Kurc --- minitests/srl/Makefile | 45 ++++++++++++++++++++++++++++ minitests/srl/README.md | 5 ++++ minitests/srl/par.tcl | 36 ++++++++++++++++++++++ minitests/srl/srl32_init.v | 25 ++++++++++++++++ minitests/srl/srl32_x1.v | 21 +++++++++++++ minitests/srl/srl32_x2.v | 31 +++++++++++++++++++ minitests/srl/srl32_x2_chain.v | 33 ++++++++++++++++++++ minitests/srl/srl32_x3.v | 41 +++++++++++++++++++++++++ minitests/srl/srl32_x3_chain.v | 44 +++++++++++++++++++++++++++ minitests/srl/srl32_x4.v | 51 +++++++++++++++++++++++++++++++ minitests/srl/srl32_x4_chain.v | 55 ++++++++++++++++++++++++++++++++++ 11 files changed, 387 insertions(+) create mode 100644 minitests/srl/Makefile create mode 100644 minitests/srl/README.md create mode 100644 minitests/srl/par.tcl create mode 100644 minitests/srl/srl32_init.v create mode 100644 minitests/srl/srl32_x1.v create mode 100644 minitests/srl/srl32_x2.v create mode 100644 minitests/srl/srl32_x2_chain.v create mode 100644 minitests/srl/srl32_x3.v create mode 100644 minitests/srl/srl32_x3_chain.v create mode 100644 minitests/srl/srl32_x4.v create mode 100644 minitests/srl/srl32_x4_chain.v diff --git a/minitests/srl/Makefile b/minitests/srl/Makefile new file mode 100644 index 00000000..bbccc9e2 --- /dev/null +++ b/minitests/srl/Makefile @@ -0,0 +1,45 @@ +YOSYS = $(XRAY_DIR)/third_party/yosys/yosys +PART = xc7a35tcsg324-1 +BIT2FASM_ARGS = --part "$(XRAY_DIR)/database/artix7/$(PART)" --verbose + +VERILOG_FILES = $(wildcard *.v) +FASM_TARGETS = $(VERILOG_FILES:.v=.fasm) +SEGPRINT_TARGETS = $(VERILOG_FILES:.v=.segprint.log) + +all: $(FASM_TARGETS) $(SEGPRINT_TARGETS) + +clean: + @find . -name "build.*" | xargs rm -rf + @rm -f *.edif + @rm -f *.bit + @rm -f *.bin + @rm -f *.bits + @rm -f *.fasm + @rm -f *.log + @rm -f *.dcp + +.PHONY: all clean + +$(YOSYS): + cd $(XRAY_DIR)/third_party/yosys && make config-gcc && make -j$(shell nproc) + +%.edif: %.v $(YOSYS) + $(YOSYS) -p "read_verilog $< ; synth_xilinx -flatten -nosrl -edif $@" -l $@.log + +%.bit: %.edif par.tcl + mkdir -p build.$(basename $@) + cd build.$(basename $@) && env PROJECT_NAME=$(basename $@) $(XRAY_VIVADO) -mode batch -source ../par.tcl -nojournal -log ../$@.log + rm -rf *.backup.log + +%.fasm: %.bit + PYTHONPATH="$(XRAY_DIR):$(XRAY_DIR)/utils:$(XRAY_DIR)/third_party/fasm" \ + PATH="$(XRAY_DIR)/build/tools:$(PATH)" \ + $(XRAY_BIT2FASM) $(BIT2FASM_ARGS) \ + $< >$@ \ + || (rm -f $@ && exit 1) + +%.bits: %.bit + $(XRAY_BITREAD) -part_file $(XRAY_DIR)/database/artix7/$(PART).yaml -o $@ -z -y $< + +%.segprint.log: %.bits + $(XRAY_SEGPRINT) -z -D -b $< > $@ diff --git a/minitests/srl/README.md b/minitests/srl/README.md new file mode 100644 index 00000000..c634fe1a --- /dev/null +++ b/minitests/srl/README.md @@ -0,0 +1,5 @@ +# Minitests for SRLs + +This is a minitest for various SRL configurations. + +Uses Yosys to generate EDIF which is then P&R'd by Vivado. The makefile also invokes bit2fasm and segprint \ No newline at end of file diff --git a/minitests/srl/par.tcl b/minitests/srl/par.tcl new file mode 100644 index 00000000..b0f9eae4 --- /dev/null +++ b/minitests/srl/par.tcl @@ -0,0 +1,36 @@ +create_project -force -name $env(PROJECT_NAME) -part xc7a35ticsg324-1L + +#read_xdc ../top.xdc +read_edif ../$env(PROJECT_NAME).edif + +link_design -part xc7a35ticsg324-1L + +report_timing_summary -file top_timing_synth.rpt +report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt +report_utilization -file top_utilization_synth.rpt + +opt_design +place_design + +report_utilization -hierarchical -file top_utilization_hierarchical_place.rpt +report_utilization -file top_utilization_place.rpt +report_io -file top_io.rpt +report_control_sets -verbose -file top_control_sets.rpt +report_clock_utilization -file top_clock_utilization.rpt + +route_design +#phys_opt_design + +report_timing_summary -no_header -no_detailed_paths + +write_checkpoint -force ../$env(PROJECT_NAME).dcp + +set_property SEVERITY {Warning} [get_drc_checks UCIO-1] +set_property SEVERITY {Warning} [get_drc_checks NSTD-1] + +report_route_status -file top_route_status.rpt +report_drc -file top_drc.rpt +report_timing_summary -datasheet -max_paths 10 -file top_timing.rpt +report_power -file top_power.rpt + +write_bitstream -force ../$env(PROJECT_NAME).bit diff --git a/minitests/srl/srl32_init.v b/minitests/srl/srl32_init.v new file mode 100644 index 00000000..b80a6ec7 --- /dev/null +++ b/minitests/srl/srl32_init.v @@ -0,0 +1,25 @@ +module top +( +(* clock_buffer_type = "NONE" *) +input wire CLK, +input wire CE, +input wire D, +input wire [4:0] A, +output wire Q +); + + (* LOC="SLICE_X2Y0", BEL="A6LUT" *) + SRLC32E # + ( + .INIT(32'hF0F01030) + ) + srl_a + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q (Q) + ); + +endmodule diff --git a/minitests/srl/srl32_x1.v b/minitests/srl/srl32_x1.v new file mode 100644 index 00000000..2d309662 --- /dev/null +++ b/minitests/srl/srl32_x1.v @@ -0,0 +1,21 @@ +module top +( +(* clock_buffer_type = "NONE" *) +input wire CLK, +input wire CE, +input wire D, +input wire [4:0] A, +output wire Q +); + + (* LOC="SLICE_X2Y0", BEL="A6LUT" *) + SRLC32E srl_a + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q (Q) + ); + +endmodule diff --git a/minitests/srl/srl32_x2.v b/minitests/srl/srl32_x2.v new file mode 100644 index 00000000..14218c9e --- /dev/null +++ b/minitests/srl/srl32_x2.v @@ -0,0 +1,31 @@ +module top +( +(* clock_buffer_type = "NONE" *) +input wire CLK, +input wire CE, +input wire D, +input wire [4:0] A, +output wire [1:0] Q +); + + (* LOC="SLICE_X2Y0", BEL="A6LUT" *) + SRLC32E srl_a + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q (Q[0]) + ); + + (* LOC="SLICE_X2Y0", BEL="B6LUT" *) + SRLC32E srl_b + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q (Q[1]) + ); + +endmodule diff --git a/minitests/srl/srl32_x2_chain.v b/minitests/srl/srl32_x2_chain.v new file mode 100644 index 00000000..75530579 --- /dev/null +++ b/minitests/srl/srl32_x2_chain.v @@ -0,0 +1,33 @@ +module top +( +(* clock_buffer_type = "NONE" *) +input wire CLK, +input wire CE, +input wire D, +input wire [4:0] A, +output wire Q +); + + wire q31_d; + + (* LOC="SLICE_X2Y0", BEL="D6LUT" *) + SRLC32E srl_d + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q31 (q31_d) + ); + + (* LOC="SLICE_X2Y0", BEL="C6LUT" *) + SRLC32E srl_c + ( + .CLK (CLK), + .CE (CE), + .D (q31_d), + .A (A), + .Q (Q) + ); + +endmodule diff --git a/minitests/srl/srl32_x3.v b/minitests/srl/srl32_x3.v new file mode 100644 index 00000000..b36e27b4 --- /dev/null +++ b/minitests/srl/srl32_x3.v @@ -0,0 +1,41 @@ +module top +( +(* clock_buffer_type = "NONE" *) +input wire CLK, +input wire CE, +input wire D, +input wire [4:0] A, +output wire [2:0] Q +); + + (* LOC="SLICE_X2Y0", BEL="A6LUT" *) + SRLC32E srl_a + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q (Q[0]) + ); + + (* LOC="SLICE_X2Y0", BEL="B6LUT" *) + SRLC32E srl_b + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q (Q[1]) + ); + + (* LOC="SLICE_X2Y0", BEL="C6LUT" *) + SRLC32E srl_c + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q (Q[2]) + ); + +endmodule diff --git a/minitests/srl/srl32_x3_chain.v b/minitests/srl/srl32_x3_chain.v new file mode 100644 index 00000000..8ead2e76 --- /dev/null +++ b/minitests/srl/srl32_x3_chain.v @@ -0,0 +1,44 @@ +module top +( +(* clock_buffer_type = "NONE" *) +input wire CLK, +input wire CE, +input wire D, +input wire [4:0] A, +output wire Q +); + + wire q31_d; + wire q31_c; + + (* LOC="SLICE_X2Y0", BEL="D6LUT" *) + SRLC32E srl_d + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q31 (q31_d) + ); + + (* LOC="SLICE_X2Y0", BEL="C6LUT" *) + SRLC32E srl_c + ( + .CLK (CLK), + .CE (CE), + .D (q31_d), + .A (A), + .Q31 (q31_c) + ); + + (* LOC="SLICE_X2Y0", BEL="B6LUT" *) + SRLC32E srl_b + ( + .CLK (CLK), + .CE (CE), + .D (q31_c), + .A (A), + .Q (Q) + ); + +endmodule diff --git a/minitests/srl/srl32_x4.v b/minitests/srl/srl32_x4.v new file mode 100644 index 00000000..9e69b7f0 --- /dev/null +++ b/minitests/srl/srl32_x4.v @@ -0,0 +1,51 @@ +module top +( +(* clock_buffer_type = "NONE" *) +input wire CLK, +input wire CE, +input wire D, +input wire [4:0] A, +output wire [3:0] Q +); + + (* LOC="SLICE_X2Y0", BEL="A6LUT" *) + SRLC32E srl_a + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q (Q[0]) + ); + + (* LOC="SLICE_X2Y0", BEL="B6LUT" *) + SRLC32E srl_b + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q (Q[1]) + ); + + (* LOC="SLICE_X2Y0", BEL="C6LUT" *) + SRLC32E srl_c + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q (Q[2]) + ); + + (* LOC="SLICE_X2Y0", BEL="D6LUT" *) + SRLC32E srl_d + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q (Q[3]) + ); + +endmodule diff --git a/minitests/srl/srl32_x4_chain.v b/minitests/srl/srl32_x4_chain.v new file mode 100644 index 00000000..257a8d03 --- /dev/null +++ b/minitests/srl/srl32_x4_chain.v @@ -0,0 +1,55 @@ +module top +( +(* clock_buffer_type = "NONE" *) +input wire CLK, +input wire CE, +input wire D, +input wire [4:0] A, +output wire Q +); + + wire q31_d; + wire q31_c; + wire q31_b; + + (* LOC="SLICE_X2Y0", BEL="D6LUT" *) + SRLC32E srl_d + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q31 (q31_d) + ); + + (* LOC="SLICE_X2Y0", BEL="C6LUT" *) + SRLC32E srl_c + ( + .CLK (CLK), + .CE (CE), + .D (q31_d), + .A (A), + .Q31 (q31_c) + ); + + (* LOC="SLICE_X2Y0", BEL="B6LUT" *) + SRLC32E srl_b + ( + .CLK (CLK), + .CE (CE), + .D (q31_c), + .A (A), + .Q (q31_b) + ); + + (* LOC="SLICE_X2Y0", BEL="A6LUT" *) + SRLC32E srl_a + ( + .CLK (CLK), + .CE (CE), + .D (q31_b), + .A (A), + .Q (Q) + ); + +endmodule From 98bcd3f4479bc7fd7ce82db17e4ad70e26ac9197 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Fri, 28 Jun 2019 10:52:26 +0200 Subject: [PATCH 2/5] Added full vivado flow to the Makefile Signed-off-by: Maciej Kurc --- minitests/srl/Makefile | 22 ++++++++++++++++++---- minitests/srl/syn.tcl | 11 +++++++++++ 2 files changed, 29 insertions(+), 4 deletions(-) create mode 100644 minitests/srl/syn.tcl diff --git a/minitests/srl/Makefile b/minitests/srl/Makefile index bbccc9e2..c1d730c9 100644 --- a/minitests/srl/Makefile +++ b/minitests/srl/Makefile @@ -1,3 +1,4 @@ +SYNTH ?= vivado YOSYS = $(XRAY_DIR)/third_party/yosys/yosys PART = xc7a35tcsg324-1 BIT2FASM_ARGS = --part "$(XRAY_DIR)/database/artix7/$(PART)" --verbose @@ -9,7 +10,8 @@ SEGPRINT_TARGETS = $(VERILOG_FILES:.v=.segprint.log) all: $(FASM_TARGETS) $(SEGPRINT_TARGETS) clean: - @find . -name "build.*" | xargs rm -rf + @find . -name "build-par.*" | xargs rm -rf + @find . -name "build-syn.*" | xargs rm -rf @rm -f *.edif @rm -f *.bit @rm -f *.bin @@ -18,17 +20,29 @@ clean: @rm -f *.log @rm -f *.dcp -.PHONY: all clean +help: + @echo "Usage: make all [SYNTH=]" + +.PHONY: all clean help $(YOSYS): cd $(XRAY_DIR)/third_party/yosys && make config-gcc && make -j$(shell nproc) +ifeq ($(SYNTH), yosys) %.edif: %.v $(YOSYS) $(YOSYS) -p "read_verilog $< ; synth_xilinx -flatten -nosrl -edif $@" -l $@.log +else ifeq ($(SYNTH), vivado) +%.edif: %.v $(YOSYS) + mkdir -p build-syn.$(basename $@) + cd build-syn.$(basename $@) && env PROJECT_NAME=$(basename $@) $(XRAY_VIVADO) -mode batch -source ../syn.tcl -nojournal -log ../$@.log + rm -rf *.backup.log + +endif + %.bit: %.edif par.tcl - mkdir -p build.$(basename $@) - cd build.$(basename $@) && env PROJECT_NAME=$(basename $@) $(XRAY_VIVADO) -mode batch -source ../par.tcl -nojournal -log ../$@.log + mkdir -p build-par.$(basename $@) + cd build-par.$(basename $@) && env PROJECT_NAME=$(basename $@) $(XRAY_VIVADO) -mode batch -source ../par.tcl -nojournal -log ../$@.log rm -rf *.backup.log %.fasm: %.bit diff --git a/minitests/srl/syn.tcl b/minitests/srl/syn.tcl new file mode 100644 index 00000000..2bce1beb --- /dev/null +++ b/minitests/srl/syn.tcl @@ -0,0 +1,11 @@ +create_project -force -name $env(PROJECT_NAME) -part xc7a35ticsg324-1L + +read_verilog ../$env(PROJECT_NAME).v + +synth_design -top top + +report_timing_summary -file top_timing_synth.rpt +report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt +report_utilization -file top_utilization_synth.rpt + +write_edif -force ../$env(PROJECT_NAME).edif From 4d6f75e8ad35a5ec8a46ed078db9955d0a085eca Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Fri, 28 Jun 2019 10:53:27 +0200 Subject: [PATCH 3/5] Added packing tests for SRL32+LUT6 Signed-off-by: Maciej Kurc --- minitests/srl/srl32_x1_and_lut6_x3.v | 62 +++++++++++++++++++++++++++ minitests/srl/srl32_x2_and_lut6_x2.v | 63 ++++++++++++++++++++++++++++ minitests/srl/srl32_x3_and_lut6_x1.v | 63 ++++++++++++++++++++++++++++ 3 files changed, 188 insertions(+) create mode 100644 minitests/srl/srl32_x1_and_lut6_x3.v create mode 100644 minitests/srl/srl32_x2_and_lut6_x2.v create mode 100644 minitests/srl/srl32_x3_and_lut6_x1.v diff --git a/minitests/srl/srl32_x1_and_lut6_x3.v b/minitests/srl/srl32_x1_and_lut6_x3.v new file mode 100644 index 00000000..ab1a894b --- /dev/null +++ b/minitests/srl/srl32_x1_and_lut6_x3.v @@ -0,0 +1,62 @@ +module top +( +(* clock_buffer_type = "NONE" *) +input wire CLK, +input wire CE, +input wire D, +input wire [5:0] I, +input wire [4:0] A, +output wire [3:0] Q +); + + (* DONT_TOUCH="yes" *) + (* LOC="SLICE_X2Y0", BEL="A6LUT" *) + SRLC32E srl_a + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q (Q[0]) + ); + + (* DONT_TOUCH="yes" *) + (* LOC="SLICE_X2Y0", BEL="B6LUT" *) + LUT6 lut_b + ( + .I0 (I[0]), + .I1 (I[1]), + .I2 (I[2]), + .I3 (I[3]), + .I4 (I[4]), + .I5 (I[5]), + .O (Q[1]) + ); + + (* DONT_TOUCH="yes" *) + (* LOC="SLICE_X2Y0", BEL="C6LUT" *) + LUT6 lut_c + ( + .I0 (I[0]), + .I1 (I[1]), + .I2 (I[2]), + .I3 (I[3]), + .I4 (I[4]), + .I5 (I[5]), + .O (Q[2]) + ); + + (* DONT_TOUCH="yes" *) + (* LOC="SLICE_X2Y0", BEL="D6LUT" *) + LUT6 lut_d + ( + .I0 (I[0]), + .I1 (I[1]), + .I2 (I[2]), + .I3 (I[3]), + .I4 (I[4]), + .I5 (I[5]), + .O (Q[3]) + ); + +endmodule diff --git a/minitests/srl/srl32_x2_and_lut6_x2.v b/minitests/srl/srl32_x2_and_lut6_x2.v new file mode 100644 index 00000000..c68e0c1e --- /dev/null +++ b/minitests/srl/srl32_x2_and_lut6_x2.v @@ -0,0 +1,63 @@ +module top +( +(* clock_buffer_type = "NONE" *) +input wire CLK, +input wire CE, +input wire D, +input wire [5:0] I, +input wire [4:0] A, +output wire [3:0] Q +); + + wire srl_b_mc31; + + (* DONT_TOUCH="yes" *) + (* LOC="SLICE_X2Y0", BEL="A6LUT" *) + SRLC32E srl_a + ( + .CLK (CLK), + .CE (CE), + .D (srl_b_mc31), + .A (A), + .Q (Q[0]) + ); + + (* DONT_TOUCH="yes" *) + (* LOC="SLICE_X2Y0", BEL="B6LUT" *) + SRLC32E srl_b + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q (Q[1]), + .Q31 (srl_b_mc31) + ); + + (* DONT_TOUCH="yes" *) + (* LOC="SLICE_X2Y0", BEL="C6LUT" *) + LUT6 lut_c + ( + .I0 (I[0]), + .I1 (I[1]), + .I2 (I[2]), + .I3 (I[3]), + .I4 (I[4]), + .I5 (I[5]), + .O (Q[2]) + ); + + (* DONT_TOUCH="yes" *) + (* LOC="SLICE_X2Y0", BEL="D6LUT" *) + LUT6 lut_d + ( + .I0 (I[0]), + .I1 (I[1]), + .I2 (I[2]), + .I3 (I[3]), + .I4 (I[4]), + .I5 (I[5]), + .O (Q[3]) + ); + +endmodule diff --git a/minitests/srl/srl32_x3_and_lut6_x1.v b/minitests/srl/srl32_x3_and_lut6_x1.v new file mode 100644 index 00000000..c931bbc9 --- /dev/null +++ b/minitests/srl/srl32_x3_and_lut6_x1.v @@ -0,0 +1,63 @@ +module top +( +(* clock_buffer_type = "NONE" *) +input wire CLK, +input wire CE, +input wire D, +input wire [5:0] I, +input wire [4:0] A, +output wire [3:0] Q +); + + wire srl_b_mc31; + wire srl_c_mc31; + + (* DONT_TOUCH="yes" *) + (* LOC="SLICE_X2Y0", BEL="A6LUT" *) + SRLC32E srl_a + ( + .CLK (CLK), + .CE (CE), + .D (srl_b_mc31), + .A (A), + .Q (Q[0]) + ); + + (* DONT_TOUCH="yes" *) + (* LOC="SLICE_X2Y0", BEL="B6LUT" *) + SRLC32E srl_b + ( + .CLK (CLK), + .CE (CE), + .D (srl_c_mc31), + .A (A), + .Q (Q[1]), + .Q31 (srl_b_mc31) + ); + + (* DONT_TOUCH="yes" *) + (* LOC="SLICE_X2Y0", BEL="C6LUT" *) + SRLC32E srl_c + ( + .CLK (CLK), + .CE (CE), + .D (D), + .A (A), + .Q (Q[2]), + .Q31 (srl_c_mc31) + ); + + (* DONT_TOUCH="yes" *) + (* LOC="SLICE_X2Y0", BEL="D6LUT" *) + LUT6 lut_d + ( + .I0 (I[0]), + .I1 (I[1]), + .I2 (I[2]), + .I3 (I[3]), + .I4 (I[4]), + .I5 (I[5]), + .O (Q[3]) + ); + +endmodule From cbbf46112fd3b3e081da172626ca90a73bfe01d6 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Tue, 2 Jul 2019 16:03:02 +0200 Subject: [PATCH 4/5] Updated EDIF write to include cell attributes Signed-off-by: Maciej Kurc --- minitests/srl/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/minitests/srl/Makefile b/minitests/srl/Makefile index c1d730c9..0e465ae7 100644 --- a/minitests/srl/Makefile +++ b/minitests/srl/Makefile @@ -30,7 +30,7 @@ $(YOSYS): ifeq ($(SYNTH), yosys) %.edif: %.v $(YOSYS) - $(YOSYS) -p "read_verilog $< ; synth_xilinx -flatten -nosrl -edif $@" -l $@.log + $(YOSYS) -p "read_verilog $< ; synth_xilinx -flatten -nosrl; write_edif -pvector bra -attrprop $@" -l $@.log else ifeq ($(SYNTH), vivado) %.edif: %.v $(YOSYS) From 5c6063944269c93713ff0b2ecdbbdb356e8677f8 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Fri, 5 Jul 2019 12:03:30 +0200 Subject: [PATCH 5/5] Added generation of sorted and "uniqued" FASM output Signed-off-by: Maciej Kurc --- minitests/srl/Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/minitests/srl/Makefile b/minitests/srl/Makefile index 0e465ae7..faaf8ef5 100644 --- a/minitests/srl/Makefile +++ b/minitests/srl/Makefile @@ -52,6 +52,9 @@ endif $< >$@ \ || (rm -f $@ && exit 1) +%.unique.fasm: %.fasm + @sort -u $< >$@ + %.bits: %.bit $(XRAY_BITREAD) -part_file $(XRAY_DIR)/database/artix7/$(PART).yaml -o $@ -z -y $<