diff --git a/fuzzers/030-iob18-sing/Makefile b/fuzzers/030-iob18-sing/Makefile new file mode 100644 index 00000000..9c6adb34 --- /dev/null +++ b/fuzzers/030-iob18-sing/Makefile @@ -0,0 +1,40 @@ +# Copyright (C) 2017-2022 The Project X-Ray Authors. +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC +# +# SING-row IOB18 basic-config fuzzer (DRIVE/SLEW/PULLTYPE/STEPDOWN) for the +# single IOB18 site in each *_SING tile. Replaces the hand-copied (and +# mis-addressed) LIOB18_SING entries with real measurements. +# +# Unlike regular IOB18 (where L+R share the 'iob18' segbits db and segmaker +# emits a normalised IOB18. prefix), SING tiles have SEPARATE liob18_sing / +# riob18_sing dbs, so segmaker emits LIOB18_SING. / RIOB18_SING. and the two +# sides must be solved independently. process_rdb.py still re-emits the +# IOB18. prefix, which the per-side mergedb cases rewrite to LIOB18_SING. / +# RIOB18_SING. +N := 30 +include ../fuzzer.mk + +database: build/segbits_liob18_sing.db build/segbits_riob18_sing.db + +# Per-side: segmatch -> drop unresolved (<.. candidates>, which process_rdb +# cannot parse) -> process_rdb enum-merge -> dbfixup. +build/segbits_liob18_sing.db: $(SPECIMENS_OK) + ${XRAY_SEGMATCH} -o build/raw_l.rdb $$(find -name 'segdata_liob18_sing.txt') + python3 process_rdb.py build/raw_l.rdb > build/proc_l.rdb + ${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in build/proc_l.rdb --seg-fn-out $@ + +build/segbits_riob18_sing.db: $(SPECIMENS_OK) + ${XRAY_SEGMATCH} -o build/raw_r.rdb $$(find -name 'segdata_riob18_sing.txt') + python3 process_rdb.py build/raw_r.rdb > build/proc_r.rdb + ${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in build/proc_r.rdb --seg-fn-out $@ + +pushdb: + ${XRAY_MERGEDB} liob18_sing build/segbits_liob18_sing.db + ${XRAY_MERGEDB} riob18_sing build/segbits_riob18_sing.db + +.PHONY: database pushdb diff --git a/fuzzers/030-iob18-sing/bits.dbf b/fuzzers/030-iob18-sing/bits.dbf new file mode 100644 index 00000000..e69de29b diff --git a/fuzzers/030-iob18-sing/derive_drive_from_liob18.py b/fuzzers/030-iob18-sing/derive_drive_from_liob18.py new file mode 100644 index 00000000..56879499 --- /dev/null +++ b/fuzzers/030-iob18-sing/derive_drive_from_liob18.py @@ -0,0 +1,64 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +# +# Copyright (C) 2017-2022 The Project X-Ray Authors. +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +""" +Fallback for SING IOB DRIVE/STEPDOWN: the *_SING tiles have only ~28 IOB18 +sites on the whole device, too few for segmatch to isolate the multi-bit DRIVE +enum (the OUT bit stays ). The SING IOB18 is the *same* IOB18 +primitive as the regular LIOB18/RIOB18 tiles, and the SING fuzz that DID +resolve (IN/SLEW/PULLTYPE, and the DRIVE candidate bits 38_32/38_34/39_23/39_55) +matches the regular tile bit-for-bit. So derive the unresolved SING features +from the REAL virtex7 LIOB18/RIOB18 measurements (origin 030-iob18) rather than +leave them hand-copied/absent. + +Emits, on stdout, the requested feature group(s) for the *_SING tile type, +copied from the same feature on the regular tile. Intended to be appended to +the per-side SING db before pushdb, for ONLY the features the SING fuzz could +not solve (default: DRIVE and STEPDOWN). +""" +import argparse + + +def load(fn): + d = {} + for line in open(fn): + line = line.strip() + if not line: + continue + tag, _, bits = line.partition(' ') + d[tag] = bits + return d + + +def main(): + ap = argparse.ArgumentParser() + ap.add_argument('--src-db', required=True, help='segbits_liob18.db (real)') + ap.add_argument('--src-prefix', default='LIOB18') + ap.add_argument('--dst-prefix', default='LIOB18_SING') + ap.add_argument( + '--groups', nargs='+', default=['DRIVE', 'STEPDOWN'], + help='feature groups to derive (substring match after the site)') + args = ap.parse_args() + + src = load(args.src_db) + for tag, bits in sorted(src.items()): + if not tag.startswith(args.src_prefix + '.'): + continue + # tag = PREFIX.IOB_Yn..[.] + rest = tag[len(args.src_prefix) + 1:] + parts = rest.split('.') + if len(parts) < 3: + continue + group = parts[2] + if group not in args.groups: + continue + print('{}.{} {}'.format(args.dst_prefix, rest, bits)) + + +if __name__ == '__main__': + main() diff --git a/fuzzers/030-iob18-sing/generate.py b/fuzzers/030-iob18-sing/generate.py new file mode 100644 index 00000000..86b9154b --- /dev/null +++ b/fuzzers/030-iob18-sing/generate.py @@ -0,0 +1,94 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +# +# Copyright (C) 2017-2022 The Project X-Ray Authors. +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC +""" +SING-row sibling of 030-iob18. Tags the basic IOB18 config (IN_USE / OUT / IN / +IN_ONLY / IN_DIFF / PULLTYPE / DRIVE / SLEW / STEPDOWN) for the single IOB18 +site in each *_SING tile, per the OBUF / IBUF / unused type chosen in top.py. + +Reuses 030-iob18's drive_opts / enum-zero convention so the merged feature +names (after process_rdb.py) match nextpnr, e.g. +LVCMOS15_LVCMOS18.DRIVE.I12_I16_I2_I4_I6_I8. Single-ended only. +""" +from prjxray.segmaker import Segmaker +from prjxray import segmaker +from prjxray import verilog +import json + +LVCMOS = ['LVCMOS12', 'LVCMOS15', 'LVCMOS18'] + + +def bitfilter(frame, word): + # SING tile frames differ from regular LIOB18; let segmatch find them. + return True + + +def mk_drive_opt(iostandard, drive): + if drive is None: + drive = '_FIXED' + return '{}.DRIVE.I{}'.format(iostandard, drive) + + +def main(): + print("Loading tags") + segmk = Segmaker("design.bits") + + with open('params.jl', 'r') as f: + design = json.load(f) + + for d in design: + site = d['site'] + iostandard = verilog.unquote(d['IOSTANDARD']) + typ = d['type'] # 'OBUF', 'IBUF', or None (unused) + + in_use = 1 if typ is not None else 0 + is_out = 1 if typ == 'OBUF' else 0 + is_in = 1 if typ == 'IBUF' else 0 + + segmk.add_site_tag(site, 'INOUT', 0) + segmk.add_site_tag(site, '{}.IN_USE'.format(iostandard), in_use) + segmk.add_site_tag(site, '{}.OUT'.format(iostandard), is_out) + segmk.add_site_tag(site, '{}.IN'.format(iostandard), is_in) + segmk.add_site_tag(site, '{}.IN_ONLY'.format(iostandard), is_in) + segmk.add_site_tag(site, '{}.IN_DIFF'.format(iostandard), 0) + + # PULLTYPE applies whenever the IOB is in use. + if in_use: + segmaker.add_site_group_zero( + segmk, site, "PULLTYPE.", + ("NONE", "KEEPER", "PULLDOWN", "PULLUP"), "PULLDOWN", + verilog.unquote(d['PULLTYPE'])) + + # DRIVE / SLEW / STEPDOWN only meaningful for output buffers. + if typ == 'OBUF': + drive_opts = set() + for opt in LVCMOS: + for drive_opt in ("2", "4", "6", "8", "12", "16"): + if drive_opt in ["12", "16"] and opt == "LVCMOS12": + continue + drive_opts.add(mk_drive_opt(opt, drive_opt)) + segmaker.add_site_group_zero( + segmk, site, '', drive_opts, mk_drive_opt('LVCMOS25', '12'), + mk_drive_opt(iostandard, d['DRIVE'])) + + if d['SLEW']: + for opt in ["SLOW", "FAST"]: + segmk.add_site_tag( + site, iostandard + ".SLEW." + opt, + opt == verilog.unquote(d['SLEW'])) + + segmk.add_site_tag(site, '{}.STEPDOWN'.format(iostandard), 1) + + segmk.compile(bitfilter=bitfilter) + segmk.write(allow_empty=True) + + +if __name__ == "__main__": + main() diff --git a/fuzzers/030-iob18-sing/generate.tcl b/fuzzers/030-iob18-sing/generate.tcl new file mode 100644 index 00000000..413215be --- /dev/null +++ b/fuzzers/030-iob18-sing/generate.tcl @@ -0,0 +1,107 @@ +# Copyright (C) 2017-2022 The Project X-Ray Authors +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC +source "$::env(XRAY_DIR)/utils/utils.tcl" + +proc make_io_pin_sites {} { + # get all possible IOB pins + foreach pad [get_package_pins -filter "IS_GENERAL_PURPOSE == 1"] { + set site [get_sites -of_objects $pad] + if {[llength $site] == 0} { + continue + } + if [string match IOB18* [get_property SITE_TYPE $site]] { + dict append io_pin_sites $site $pad + } + } + return $io_pin_sites +} + +proc load_pin_lines {} { + # IOB_X0Y103 clk input + # IOB_X0Y129 do[0] output + + set fp [open "params.csv" r] + gets $fp line + + set pin_lines {} + for {gets $fp line} {$line != ""} {gets $fp line} { + lappend pin_lines [split $line ","] + } + close $fp + return $pin_lines +} + +proc loc_pins {} { + set pin_lines [load_pin_lines] + set io_pin_sites [make_io_pin_sites] + + puts "Looping" + for {set idx 0} {$idx < [llength $pin_lines]} {incr idx} { + set line [lindex $pin_lines $idx] + puts "$line" + + set site_str [lindex $line 1] + set pin_str [lindex $line 2] + set iostandard [lindex $line 3] + set drive [lindex $line 4] + set slew [lindex $line 5] + set pulltype [lindex $line 6] + + # Have: site + # Want: pin for site + + set site [get_sites $site_str] + set pad_bel [get_bels -of_objects $site -filter {TYPE =~ PAD && NAME =~ IOB_*}] + # set port [get_ports -of_objects $site] + set port [get_ports $pin_str] + set tile [get_tiles -of_objects $site] + + set pin [dict get $io_pin_sites $site] + + set props {} + #lappend props PACKAGE_PIN $pin + lappend props IOSTANDARD $iostandard + lappend props PULLTYPE $pulltype + + if {$drive != "None"} { + lappend props DRIVE $drive + } + + if {$slew != "None"} { + lappend props SLEW $slew + } + + puts $props + + set_property -dict "$props" $port + } +} + +proc run {} { + create_project -force -part $::env(XRAY_PART) design design + read_verilog top.v + synth_design -top top + + loc_pins + + set_property CFGBVS GND [current_design] + set_property CONFIG_VOLTAGE 1.8 [current_design] + set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] + set_property IS_ENABLED 0 [get_drc_checks {REQP-79}] + set_property IS_ENABLED 0 [get_drc_checks {REQP-144}] + + write_checkpoint -force design_pre_place.dcp + + place_design + route_design + + write_checkpoint -force design.dcp + write_bitstream -force design.bit +} + +run diff --git a/fuzzers/030-iob18-sing/iostandards.py b/fuzzers/030-iob18-sing/iostandards.py new file mode 100644 index 00000000..c6577639 --- /dev/null +++ b/fuzzers/030-iob18-sing/iostandards.py @@ -0,0 +1,17 @@ +LVCMOS = ['LVCMOS12', 'LVCMOS15', 'LVCMOS18'] + +# TODO: add support for digitally controlled impedance (_DCI) and termination (_T) +SSTL = ['SSTL15', #'SSTL15_DCI', 'SSTL15_T_DCI' + 'SSTL135', #'SSTL135_DCI', 'SSTL135_T_DCI' + 'SSTL12', #'SSTL12_DCI', 'SSTL12_T_DCI' + ] + +# TODO: add support for digitally controlled impedance (_DCI) and termination (_T) +DIFF_SSTL15 = ['DIFF_SSTL15', ] # 'DIFF_SSTL15_DCI', 'DIFF_SSTL15_T_DCI'] +DIFF_SSTL135 = ['DIFF_SSTL135', ] # 'DIFF_SSTL135_DCI', 'DIFF_SSTL135_T_DCI'] +DIFF_SSTL12 = ['DIFF_SSTL12', ] # 'DIFF_SSTL12_DCI', 'DIFF_SSTL12_T_DCI'] +DIFF_SSTL = DIFF_SSTL15 + DIFF_SSTL135 + DIFF_SSTL12 + +LVDS = ['LVDS'] + +DIFF = DIFF_SSTL + LVDS \ No newline at end of file diff --git a/fuzzers/030-iob18-sing/params.csv b/fuzzers/030-iob18-sing/params.csv new file mode 100644 index 00000000..976c005d --- /dev/null +++ b/fuzzers/030-iob18-sing/params.csv @@ -0,0 +1,23 @@ +tile,site,pin,iostandard,drive,slew,pulltype +LIOB18_SING_X81Y1,IOB_X0Y0,di[0],LVCMOS15,6,FAST,PULLUP +LIOB18_SING_X81Y103,IOB_X0Y99,di[1],LVCMOS15,2,SLOW,KEEPER +LIOB18_SING_X81Y155,IOB_X0Y149,di[2],LVCMOS15,2,SLOW,PULLDOWN +LIOB18_SING_X81Y157,IOB_X0Y150,do[0],LVCMOS15,4,FAST,PULLDOWN +LIOB18_SING_X81Y209,IOB_X0Y200,do[1],LVCMOS15,16,SLOW,PULLUP +LIOB18_SING_X81Y259,IOB_X0Y249,do[2],LVCMOS15,4,SLOW,PULLDOWN +LIOB18_SING_X81Y261,IOB_X0Y250,di[3],LVCMOS15,16,FAST,KEEPER +LIOB18_SING_X81Y311,IOB_X0Y299,di[4],LVCMOS15,6,SLOW,KEEPER +LIOB18_SING_X81Y313,IOB_X0Y300,di[5],LVCMOS15,12,FAST,NONE +LIOB18_SING_X81Y363,IOB_X0Y349,di[6],LVCMOS15,16,FAST,PULLUP +LIOB18_SING_X81Y51,IOB_X0Y49,di[7],LVCMOS15,12,FAST,PULLUP +RIOB18_SING_X312Y1,IOB_X1Y0,di[8],LVCMOS15,12,FAST,NONE +RIOB18_SING_X312Y103,IOB_X1Y99,di[9],LVCMOS15,2,SLOW,PULLUP +RIOB18_SING_X312Y157,IOB_X1Y150,di[10],LVCMOS15,8,FAST,PULLDOWN +RIOB18_SING_X312Y207,IOB_X1Y199,do[3],LVCMOS15,16,FAST,NONE +RIOB18_SING_X312Y259,IOB_X1Y249,di[11],LVCMOS15,12,SLOW,PULLUP +RIOB18_SING_X312Y261,IOB_X1Y250,di[12],LVCMOS15,2,SLOW,NONE +RIOB18_SING_X312Y311,IOB_X1Y299,di[13],LVCMOS15,2,FAST,NONE +RIOB18_SING_X312Y313,IOB_X1Y300,di[14],LVCMOS15,16,FAST,PULLDOWN +RIOB18_SING_X312Y363,IOB_X1Y349,di[15],LVCMOS15,6,SLOW,NONE +RIOB18_SING_X312Y51,IOB_X1Y49,di[16],LVCMOS15,4,SLOW,KEEPER +RIOB18_SING_X312Y53,IOB_X1Y50,do[4],LVCMOS15,16,FAST,NONE diff --git a/fuzzers/030-iob18-sing/params.jl b/fuzzers/030-iob18-sing/params.jl new file mode 100644 index 00000000..7f502d0d --- /dev/null +++ b/fuzzers/030-iob18-sing/params.jl @@ -0,0 +1,282 @@ +[ + { + "tile": "LIOB18_SING_X81Y1", + "site": "IOB_X0Y0", + "type": "IBUF", + "IOSTANDARD": "\"LVCMOS15\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "PULLTYPE": "\"PULLUP\"", + "pin": "di[0]" + }, + { + "tile": "LIOB18_SING_X81Y103", + "site": "IOB_X0Y99", + "type": "IBUF", + "IOSTANDARD": "\"LVCMOS15\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "PULLTYPE": "\"KEEPER\"", + "pin": "di[1]" + }, + { + "tile": "LIOB18_SING_X81Y105", + "site": "IOB_X0Y100", + "type": null, + "IOSTANDARD": "\"LVCMOS15\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "PULLTYPE": "\"KEEPER\"", + "pin": null + }, + { + "tile": "LIOB18_SING_X81Y155", + "site": "IOB_X0Y149", + "type": "IBUF", + "IOSTANDARD": "\"LVCMOS15\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "PULLTYPE": "\"PULLDOWN\"", + "pin": "di[2]" + }, + { + "tile": "LIOB18_SING_X81Y157", + "site": "IOB_X0Y150", + "type": "OBUF", + "IOSTANDARD": "\"LVCMOS15\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "PULLTYPE": "\"PULLDOWN\"", + "pin": "do[0]" + }, + { + "tile": "LIOB18_SING_X81Y207", + "site": "IOB_X0Y199", + "type": null, + "IOSTANDARD": "\"LVCMOS15\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "PULLTYPE": "\"NONE\"", + "pin": null + }, + { + "tile": "LIOB18_SING_X81Y209", + "site": "IOB_X0Y200", + "type": "OBUF", + "IOSTANDARD": "\"LVCMOS15\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "PULLTYPE": "\"PULLUP\"", + "pin": "do[1]" + }, + { + "tile": "LIOB18_SING_X81Y259", + "site": "IOB_X0Y249", + "type": "OBUF", + "IOSTANDARD": "\"LVCMOS15\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "PULLTYPE": "\"PULLDOWN\"", + "pin": "do[2]" + }, + { + "tile": "LIOB18_SING_X81Y261", + "site": "IOB_X0Y250", + "type": "IBUF", + "IOSTANDARD": "\"LVCMOS15\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "PULLTYPE": "\"KEEPER\"", + "pin": "di[3]" + }, + { + "tile": "LIOB18_SING_X81Y311", + "site": "IOB_X0Y299", + "type": "IBUF", + "IOSTANDARD": "\"LVCMOS15\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "PULLTYPE": "\"KEEPER\"", + "pin": "di[4]" + }, + { + "tile": "LIOB18_SING_X81Y313", + "site": "IOB_X0Y300", + "type": "IBUF", + "IOSTANDARD": "\"LVCMOS15\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "PULLTYPE": "\"NONE\"", + "pin": "di[5]" + }, + { + "tile": "LIOB18_SING_X81Y363", + "site": "IOB_X0Y349", + "type": "IBUF", + "IOSTANDARD": "\"LVCMOS15\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "PULLTYPE": "\"PULLUP\"", + "pin": "di[6]" + }, + { + "tile": "LIOB18_SING_X81Y51", + "site": "IOB_X0Y49", + "type": "IBUF", + "IOSTANDARD": "\"LVCMOS15\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "PULLTYPE": "\"PULLUP\"", + "pin": "di[7]" + }, + { + "tile": "LIOB18_SING_X81Y53", + "site": "IOB_X0Y50", + "type": null, + "IOSTANDARD": "\"LVCMOS15\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "PULLTYPE": "\"NONE\"", + "pin": null + }, + { + "tile": "RIOB18_SING_X312Y1", + "site": "IOB_X1Y0", + "type": "IBUF", + "IOSTANDARD": "\"LVCMOS15\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "PULLTYPE": "\"NONE\"", + "pin": "di[8]" + }, + { + "tile": "RIOB18_SING_X312Y103", + "site": "IOB_X1Y99", + "type": "IBUF", + "IOSTANDARD": "\"LVCMOS15\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "PULLTYPE": "\"PULLUP\"", + "pin": "di[9]" + }, + { + "tile": "RIOB18_SING_X312Y105", + "site": "IOB_X1Y100", + "type": null, + "IOSTANDARD": "\"LVCMOS15\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "PULLTYPE": "\"KEEPER\"", + "pin": null + }, + { + "tile": "RIOB18_SING_X312Y155", + "site": "IOB_X1Y149", + "type": null, + "IOSTANDARD": "\"LVCMOS15\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "PULLTYPE": "\"KEEPER\"", + "pin": null + }, + { + "tile": "RIOB18_SING_X312Y157", + "site": "IOB_X1Y150", + "type": "IBUF", + "IOSTANDARD": "\"LVCMOS15\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "PULLTYPE": "\"PULLDOWN\"", + "pin": "di[10]" + }, + { + "tile": "RIOB18_SING_X312Y207", + "site": "IOB_X1Y199", + "type": "OBUF", + "IOSTANDARD": "\"LVCMOS15\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "PULLTYPE": "\"NONE\"", + "pin": "do[3]" + }, + { + "tile": "RIOB18_SING_X312Y209", + "site": "IOB_X1Y200", + "type": null, + "IOSTANDARD": "\"LVCMOS15\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "PULLTYPE": "\"PULLUP\"", + "pin": null + }, + { + "tile": "RIOB18_SING_X312Y259", + "site": "IOB_X1Y249", + "type": "IBUF", + "IOSTANDARD": "\"LVCMOS15\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "PULLTYPE": "\"PULLUP\"", + "pin": "di[11]" + }, + { + "tile": "RIOB18_SING_X312Y261", + "site": "IOB_X1Y250", + "type": "IBUF", + "IOSTANDARD": "\"LVCMOS15\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "PULLTYPE": "\"NONE\"", + "pin": "di[12]" + }, + { + "tile": "RIOB18_SING_X312Y311", + "site": "IOB_X1Y299", + "type": "IBUF", + "IOSTANDARD": "\"LVCMOS15\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "PULLTYPE": "\"NONE\"", + "pin": "di[13]" + }, + { + "tile": "RIOB18_SING_X312Y313", + "site": "IOB_X1Y300", + "type": "IBUF", + "IOSTANDARD": "\"LVCMOS15\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "PULLTYPE": "\"PULLDOWN\"", + "pin": "di[14]" + }, + { + "tile": "RIOB18_SING_X312Y363", + "site": "IOB_X1Y349", + "type": "IBUF", + "IOSTANDARD": "\"LVCMOS15\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "PULLTYPE": "\"NONE\"", + "pin": "di[15]" + }, + { + "tile": "RIOB18_SING_X312Y51", + "site": "IOB_X1Y49", + "type": "IBUF", + "IOSTANDARD": "\"LVCMOS15\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "PULLTYPE": "\"KEEPER\"", + "pin": "di[16]" + }, + { + "tile": "RIOB18_SING_X312Y53", + "site": "IOB_X1Y50", + "type": "OBUF", + "IOSTANDARD": "\"LVCMOS15\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "PULLTYPE": "\"NONE\"", + "pin": "do[4]" + } +] \ No newline at end of file diff --git a/fuzzers/030-iob18-sing/process_rdb.py b/fuzzers/030-iob18-sing/process_rdb.py new file mode 100644 index 00000000..ce5fd05f --- /dev/null +++ b/fuzzers/030-iob18-sing/process_rdb.py @@ -0,0 +1,266 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +# +# Copyright (C) 2017-2022 The Project X-Ray Authors. +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC +""" IOB bits are more complicated than can be easily expressed to segmaker. +There are couple cases that need to be handled here: + +- There are some bits that are always set for IN-only ports, but are cleared + selectively for OUT and INOUT ports. +- There are bits per each IOSTANDARD, in addition to drive patterns. These + can be merged to provide unique "(IOSTANDARD, DRIVE)" bit sets. +""" +import argparse +import os + + +def get_name(l): + parts = l.strip().split(' ') + return parts[0] + + +def get_site(l): + return get_name(l).split('.')[1] + + +def parse_bits(l): + parts = l.strip().split(' ') + # Any segmatch marker (<0 candidates>, <5 candidates>, , ) + # means "no solved bits"; treat uniformly as empty so a site that has some + # unresolved DRIVE/SLEW entries still keeps the group (avoids KeyError) and + # the resolved siblings drive the enum-merge. + if parts[1].startswith('<'): + return frozenset() + else: + return frozenset(parts[1:]) + + +def filter_negbits(site, feature, bits): + lvds_bits = frozenset(['!38_24', "!38_48", "!39_33", '!39_47', '!39_49']) + if "IOB_Y0" in feature and not "LVDS" in feature: + bits = bits.difference(lvds_bits) + if feature.endswith("IOB_Y0.LVCMOS12_LVCMOS15_LVCMOS18.IN"): + bits = bits.difference(frozenset(['!39_01'])) + if feature.endswith("IOB_Y1.LVCMOS12_LVCMOS15_LVCMOS18.IN"): + bits = bits.difference(frozenset(['!38_126'])) + + return bits + + +def process_features_sets(iostandard_lines): + sites = {} + + for iostd_type, iostd_list in iostandard_lines.items(): + for iostd_line in iostd_list: + feature = get_name(iostd_line) + feature_parts = feature.split('.') + site = get_site(iostd_line) + iostandard = feature_parts[2] + + bits = parse_bits(iostd_line) + + key = (site, iostd_type) + if key not in sites: + sites[key] = {} + + group = feature_parts[3] + if group not in sites[key]: + sites[key][group] = {} + + if group in ['DRIVE', 'SLEW']: + enum = feature_parts[4] + sites[key][group][(iostandard, enum)] = bits + elif group in ['IN', 'IN_DIFF', 'IN_ONLY', 'IN_USE', 'OUT', + 'STEPDOWN', 'ZIBUF_LOW_PWR']: + sites[key][group][(iostandard, None)] = bits + else: + assert False, group + + for site in sites: + for iostandard, enum in sites[site]['DRIVE']: + sites[site]['DRIVE'][(iostandard, enum)] |= sites[site]['OUT'][( + iostandard, None)] + + for iostandard, enum in sites[site]['IN']: + sites[site]['IN_ONLY'][(iostandard, enum)] -= sites[site]['IN'][( + iostandard, enum)] + + common_bits = {} + for site, iostd_type in sites: + for group in sites[(site, iostd_type)]: + if (site, group) not in common_bits: + common_bits[(site, group)] = set() + + for bits in sites[(site, iostd_type)][group].values(): + common_bits[(site, group)] |= bits + + slew_in_drives = {} + + for site, iostd_type in sites: + common_bits[(site, 'IN')] |= common_bits[(site, 'IN_DIFF')] + common_bits[(site, 'IN_DIFF')] |= common_bits[(site, 'IN')] + + # Only DIFF IOSTANDARDS such as LVDS or TMDS do not have DRIVE or SLEW features + if iostd_type == "NORMAL": + key = (site, iostd_type) + common_bits[(site, 'DRIVE')] -= common_bits[(site, 'SLEW')] + common_bits[(site, 'IN_ONLY')] |= common_bits[(site, 'DRIVE')] + + for iostandard, enum in sites[key]['DRIVE']: + slew_in_drive = common_bits[ + (site, 'SLEW')] & sites[key]['DRIVE'][(iostandard, enum)] + if slew_in_drive: + if (key, iostandard) not in slew_in_drives: + slew_in_drives[(key, iostandard)] = set() + + slew_in_drives[(key, iostandard)] |= slew_in_drive + sites[key]['DRIVE'][(iostandard, enum)] -= slew_in_drive + + for site, iostandard in slew_in_drives: + for _, enum in sites[site]['SLEW']: + sites[site]['SLEW'][(iostandard, + enum)] |= slew_in_drives[(site, iostandard)] + + for site in sites: + for iostandard, enum in sites[site]['DRIVE']: + sites[site]['DRIVE'][(iostandard, enum)] |= sites[site]['IN_USE'][( + iostandard, None)] + + for iostandard, enum in sites[site]['IN']: + _, iostd_type = site + if iostd_type == "ONLY_DIFF": + sites[site]['IN_DIFF'][(iostandard, enum)] = \ + sites[site]['IN'][(iostandard, enum)] + elif sites[site]['IN_DIFF'][(iostandard, enum)]: + sites[site]['IN_DIFF'][(iostandard, enum)] |= \ + sites[site]['IN'][(iostandard, enum)] + + for site, iostd_type in sites: + if iostd_type == "NORMAL": + del sites[(site, iostd_type)]['OUT'] + + allow_zero = ['SLEW'] + + common_groups = dict() + for site, iostd_type in sites: + if site not in common_groups: + common_groups[site] = dict() + + key = (site, iostd_type) + for group in sites[key]: + if iostd_type == "ONLY_DIFF" and group == "IN": + continue + + # Merge features that are identical. + # + # For example: + # + # IOB18.IOB_Y1.LVCMOS15.IN 38_42 39_41 + # IOB18.IOB_Y1.LVCMOS18.IN 38_42 39_41 + # + # Must be grouped. + for (iostandard, enum), bits in sites[key][group].items(): + if (bits, group) not in common_groups[site]: + common_groups[site][(bits, group)] = { + 'IOSTANDARDS': set(), + 'enums': set(), + } + + common_groups[site][(bits, + group)]['IOSTANDARDS'].add(iostandard) + if enum is not None: + common_groups[site][(bits, group)]['enums'].add(enum) + + # On Virtex-7 some Y1 IN groups differ from their Y0 counterparts by a + # single bit (e.g. LVCMOS* sets 39_01 while SSTL* does not), so the + # name-harmonisation below must not fold two distinct-bit groups onto one + # feature name -- doing so emits duplicate db lines that break dbfixup. + # Require identical bits before adopting a visited name for virtex7; other + # families never produce two-group Y1 IN splits, so they are unaffected. + require_same_bits = os.environ.get('XRAY_DATABASE') == 'virtex7' + + visited_iostandards = list() + for site, groups in common_groups.items(): + for (bits, group), v in groups.items(): + iostandards = v['IOSTANDARDS'] + enums = v['enums'] + + # It happens that some features appear only in one of the IOB sites and not + # in the other. This makes it hard to assign the correct features to the correct + # site in the P&R toolchain. + # + # The following code makes sure that the same set of iostandards + # (even if not really present at a site location) appears for each site + for visited_iostandard, visited_group, visited_enums, visited_bits in visited_iostandards: + same_enum = enums == visited_enums + same_group = group == visited_group + compatible_iostd = any( + x in iostandards for x in visited_iostandard) + take_visited_iostd = len(visited_iostandard) > len(iostandards) + same_bits = bits == visited_bits + if same_enum and same_group and compatible_iostd and take_visited_iostd \ + and (same_bits or not require_same_bits): + iostandards = visited_iostandard + break + + visited_iostandards.append((iostandards, group, enums, bits)) + + iostandards_string = '_'.join(sorted(iostandards)) + + if enums: + feature = 'IOB18.{site}.{iostandards}.{group}.{enums}'.format( + site=site, + iostandards=iostandards_string, + group=group, + enums='_'.join(sorted(enums)), + ) + else: + feature = 'IOB18.{site}.{iostandards}.{group}'.format( + site=site, + iostandards=iostandards_string, + group=group, + ) + + if not bits and group not in allow_zero: + continue + + neg_bits = frozenset( + '!{}'.format(b) for b in (common_bits[(site, group)] - bits)) + neg_bits = filter_negbits(site, feature, neg_bits) + print('{} {}'.format(feature, ' '.join(sorted(bits | neg_bits)))) + + +def main(): + parser = argparse.ArgumentParser( + description="Convert IOB rdb into good rdb." + "") + parser.add_argument('input_rdb') + + args = parser.parse_args() + + iostandard_lines = { + "NORMAL": list(), + "ONLY_DIFF": list(), + } + + with open(args.input_rdb) as f: + for l in f: + if ('.SSTL' in l or '.LVCMOS' in l + or '.LVTTL' in l) and 'IOB_' in l: + iostandard_lines["NORMAL"].append(l) + elif ('.TMDS' in l or 'LVDS' in l): + iostandard_lines["ONLY_DIFF"].append(l) + else: + print(l.strip()) + + process_features_sets(iostandard_lines) + + +if __name__ == "__main__": + main() diff --git a/fuzzers/030-iob18-sing/top.py b/fuzzers/030-iob18-sing/top.py new file mode 100644 index 00000000..d549889b --- /dev/null +++ b/fuzzers/030-iob18-sing/top.py @@ -0,0 +1,126 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +# +# Copyright (C) 2017-2022 The Project X-Ray Authors. +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC +""" +SING-row IOB18 basic-config fuzzer design. For each IOB18 site that lives in a +*_SING tile, randomly instantiate OBUF / IBUF / nothing. The mix of driven, +input-only and unused sites gives segmaker the 0-reference it needs to resolve +the OUT / DRIVE / IN_USE bits (an all-output design leaves them const-1). + +DRIVE / SLEW / PULLTYPE are applied to the ports by generate.tcl's loc_pins +from params.csv; the per-site type is recorded in params.jl for generate.py. +""" +import json +import os +import random +random.seed(int(os.getenv("SEED"), 16)) +from prjxray import util +from prjxray import verilog +from prjxray.db import Database + +# HP banks: low-voltage standards only. +IOSTANDARDS = ['LVCMOS12', 'LVCMOS15', 'LVCMOS18'] +PULLS = ["NONE", "KEEPER", "PULLDOWN", "PULLUP"] +SLEWS = ['FAST', 'SLOW'] +# OBUF (drive out), IBUF (input only) and unused, weighted toward variety. +TYPES = ['OBUF', 'OBUF', 'IBUF', 'IBUF', None, None] + + +def drives_for(iostandard): + if iostandard == 'LVCMOS12': + return [2, 4, 6, 8] + return [2, 4, 6, 8, 12, 16] + + +def gen_sites(): + db = Database(util.get_db_root(), util.get_part()) + grid = db.grid() + for tile_name in sorted(grid.tiles()): + gridinfo = grid.gridinfo_at_loc(grid.loc_of_tilename(tile_name)) + if not gridinfo.tile_type.endswith("_SING"): + continue + for site_name, site_type in gridinfo.sites.items(): + if site_type == 'IOB18': + yield tile_name, site_name + + +def main(): + # One IOSTANDARD per specimen: all SING IOBs share it so a bank never sees + # conflicting VCCO (DRC BIVC-1). Variety across the N specimens gives + # process_rdb the LVCMOS12/15/18 set it merges into the DRIVE enum names. + iostandard = random.choice(IOSTANDARDS) + params = [] + for tile, site in gen_sites(): + params.append( + { + 'tile': tile, + 'site': site, + 'type': random.choice(TYPES), + 'IOSTANDARD': verilog.quote(iostandard), + 'DRIVE': random.choice(drives_for(iostandard)), + 'SLEW': verilog.quote(random.choice(SLEWS)), + 'PULLTYPE': verilog.quote(random.choice(PULLS)), + }) + + # params.csv for generate.tcl's loc_pins (tile,site,pin,iostd,drive,slew,pull) + lines = ['tile,site,pin,iostandard,drive,slew,pulltype'] + n_in = n_out = 0 + for p in params: + if p['type'] == 'OBUF': + p['pin'] = 'do[{}]'.format(n_out) + n_out += 1 + elif p['type'] == 'IBUF': + p['pin'] = 'di[{}]'.format(n_in) + n_in += 1 + else: + p['pin'] = None + continue + lines.append( + ','.join( + map( + str, ( + p['tile'], p['site'], p['pin'], + verilog.unquote(p['IOSTANDARD']), p['DRIVE'], + verilog.unquote(p['SLEW']), + verilog.unquote(p['PULLTYPE']))))) + open('params.csv', 'w').write('\n'.join(lines) + '\n') + + with open('params.jl', 'w') as f: + json.dump(params, f, indent=2) + + # Verilog: one OBUF / IBUF per used site, LOC'd; unused sites get nothing. + # OBUFs are driven by a DONT_TOUCH LUT source (no external clock port, which + # would be an unplaceable terminal); DRIVE/SLEW/PULLTYPE come from loc_pins. + print('module top(output wire [{no}:0] do, input wire [{ni}:0] di);'.format( + no=max(n_out - 1, 0), ni=max(n_in - 1, 0))) + print(' wire src;') + print(' (* KEEP, DONT_TOUCH *) ' + 'LUT6 #(.INIT(64\'hAAAAAAAAAAAAAAAA)) srclut ' + '(.O(src), .I0(1\'b0), .I1(1\'b0), .I2(1\'b0), ' + '.I3(1\'b0), .I4(1\'b0), .I5(1\'b0));') + for idx, p in enumerate(params): + if p['type'] == 'OBUF': + print( + ''' + (* KEEP, DONT_TOUCH, LOC = "{site}" *) + OBUF obuf_{idx} (.I(src), .O({pin}));'''.format( + site=p['site'], idx=idx, pin=p['pin'])) + elif p['type'] == 'IBUF': + print( + ''' + wire ib_{idx}; + (* KEEP, DONT_TOUCH, LOC = "{site}" *) + IBUF ibuf_{idx} (.I({pin}), .O(ib_{idx}));'''.format( + site=p['site'], idx=idx, pin=p['pin'])) + print('endmodule') + + +if __name__ == '__main__': + main() diff --git a/fuzzers/035-iob18-ilogic/Makefile b/fuzzers/035-iob18-ilogic/Makefile new file mode 100644 index 00000000..370d863a --- /dev/null +++ b/fuzzers/035-iob18-ilogic/Makefile @@ -0,0 +1,42 @@ +# Copyright (C) 2017-2020 The Project X-Ray Authors. +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC +# +# IOB18 (HP-bank) ILOGIC fuzzer for Virtex-7. The kintex7 035-iob-ilogic +# fuzzer targets IOB33/HR sites that do not exist on this part, so its LIOI/ +# RIOI results were transplanted. This variant places ISERDESE2/IDDR on real +# IOB18 sites on BOTH the L and R columns and measures the ILOGIC config bits +# (incl. ZINV_D) directly. +N := 30 +include ../fuzzer.mk + +database: build/segbits_iob18_ilogic.db + +build/segbits_iob18_ilogic.rdb: $(SPECIMENS_OK) + ${XRAY_SEGMATCH} -c 6 -o build/segbits_iob18_ilogic.rdb2 $$(find -name segdata_*.txt) + # ISERDES features belong to 035b-iob18-iserdes; DYN_* are solved there too. + grep -v ".ISERDES." build/segbits_iob18_ilogic.rdb2 | grep -v "DYN_" >$@ + +build/segbits_iob18_ilogic.db: build/segbits_iob18_ilogic.rdb + ${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --groups tag_groups.txt --seg-fn-in $^ --seg-fn-out $@ + ${XRAY_MASKMERGE} build/mask_iob18_ilogic.db $$(find -name segdata_*.txt) + +pushdb: + ${XRAY_MERGEDB} lioi build/segbits_iob18_ilogic.db + ${XRAY_MERGEDB} lioi_tbytesrc build/segbits_iob18_ilogic.db + ${XRAY_MERGEDB} lioi_tbyteterm build/segbits_iob18_ilogic.db + ${XRAY_MERGEDB} rioi build/segbits_iob18_ilogic.db + ${XRAY_MERGEDB} rioi_tbytesrc build/segbits_iob18_ilogic.db + ${XRAY_MERGEDB} rioi_tbyteterm build/segbits_iob18_ilogic.db + ${XRAY_MERGEDB} mask_lioi build/mask_iob18_ilogic.db + ${XRAY_MERGEDB} mask_lioi_tbytesrc build/mask_iob18_ilogic.db + ${XRAY_MERGEDB} mask_lioi_tbyteterm build/mask_iob18_ilogic.db + ${XRAY_MERGEDB} mask_rioi build/mask_iob18_ilogic.db + ${XRAY_MERGEDB} mask_rioi_tbytesrc build/mask_iob18_ilogic.db + ${XRAY_MERGEDB} mask_rioi_tbyteterm build/mask_iob18_ilogic.db + +.PHONY: database pushdb diff --git a/fuzzers/035-iob18-ilogic/bits.dbf b/fuzzers/035-iob18-ilogic/bits.dbf new file mode 100644 index 00000000..e69de29b diff --git a/fuzzers/035-iob18-ilogic/generate.py b/fuzzers/035-iob18-ilogic/generate.py new file mode 100644 index 00000000..0c0902d7 --- /dev/null +++ b/fuzzers/035-iob18-ilogic/generate.py @@ -0,0 +1,259 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +# +# Copyright (C) 2017-2020 The Project X-Ray Authors. +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC + +from prjxray.segmaker import Segmaker +from prjxray import verilog +import json + +# Set to true to enable additional tags useful for tracing bit toggles. +DEBUG_FUZZER = False + + +def bitfilter(frame, word): + if frame < 25 or frame > 31: + return False + + return True + + +def handle_data_width(segmk, d): + if 'DATA_WIDTH' not in d: + return + + site = d['ilogic_loc'] + + # It appears several widths end up with the same bitstream pattern. + # This groups those widths together for documentation. + widths = [ + [2], + [3], + [4, 6], + [5, 7], + [8], + [10], + [14], + ] + + width_map = {} + + for ws in widths: + for w in ws: + width_map[w] = 'W{}'.format('_'.join(map(str, ws))) + + zero_opt = 2 + W_OPT_ZERO = width_map[zero_opt] + if d['DATA_WIDTH'] == zero_opt: + segmk.add_site_tag(site, 'ISERDES.DATA_WIDTH.{}'.format(W_OPT_ZERO), 1) + + for opt in width_map.values(): + if opt == W_OPT_ZERO: + continue + + segmk.add_site_tag(site, 'ISERDES.DATA_WIDTH.{}'.format(opt), 0) + else: + w_opt = width_map[d['DATA_WIDTH']] + if w_opt != W_OPT_ZERO: + segmk.add_site_tag( + site, 'ISERDES.DATA_WIDTH.{}'.format(W_OPT_ZERO), 0) + segmk.add_site_tag(site, 'ISERDES.DATA_WIDTH.{}'.format(w_opt), 1) + + +def handle_data_rate(segmk, d): + if 'DATA_WIDTH' not in d: + return + + site = d['ilogic_loc'] + + for opt in ['SDR', 'DDR']: + segmk.add_site_tag( + site, 'ISERDES.DATA_RATE.{}'.format(opt), + verilog.unquote(d['DATA_RATE']) == opt) + + +def main(): + print("Loading tags") + segmk = Segmaker("design.bits") + + with open('params.jl', 'r') as f: + design = json.load(f) + + for d in design: + site = d['ilogic_loc'] + + handle_data_width(segmk, d) + handle_data_rate(segmk, d) + + segmk.add_site_tag(site, 'ISERDES.IN_USE', d['use_iserdese2']) + + if 'NUM_CE' in d: + segmk.add_site_tag(site, 'ISERDES.NUM_CE.N2', d['NUM_CE'] == 2) + + segmk.add_site_tag( + site, 'IDDR_OR_ISERDES.IN_USE', d['use_iserdese2'] + or d['iddr_mux_config'] != 'none') + + if 'INTERFACE_TYPE' in d: + for opt in ( + 'MEMORY', + 'MEMORY_DDR3', + 'MEMORY_QDR', + 'NETWORKING', + 'OVERSAMPLE', + ): + segmk.add_site_tag( + site, 'ISERDES.INTERFACE_TYPE.{}'.format(opt), + opt == verilog.unquote(d['INTERFACE_TYPE'])) + segmk.add_site_tag( + site, 'ISERDES.INTERFACE_TYPE.Z_{}'.format(opt), + opt != verilog.unquote(d['INTERFACE_TYPE'])) + + segmk.add_site_tag( + site, 'ISERDES.INTERFACE_TYPE.NOT_MEMORY', + 'MEMORY' not in verilog.unquote(d['INTERFACE_TYPE'])) + + if d['iddr_mux_config'] != 'none': + segmk.add_site_tag(site, 'IFF.ZINIT_Q1', not d['INIT_Q1']) + segmk.add_site_tag(site, 'IFF.ZINIT_Q2', not d['INIT_Q2']) + + if 'DYN_CLKDIV_INV_EN' in d: + segmk.add_site_tag( + site, 'DYN_CLKDIV_INV_EN', + verilog.unquote(d['DYN_CLKDIV_INV_EN']) == 'TRUE') + + if 'DYN_CLK_INV_EN' in d: + segmk.add_site_tag( + site, 'DYN_CLK_INV_EN', + verilog.unquote(d['DYN_CLK_INV_EN']) == 'TRUE') + + if 'INIT_Q3' in d: + segmk.add_site_tag(site, 'IFF.ZINIT_Q3', not d['INIT_Q3']) + segmk.add_site_tag(site, 'IFF.ZINIT_Q4', not d['INIT_Q4']) + segmk.add_site_tag( + site, 'IFF.ZSRVAL_Q1', not d['SRVAL_Q1']) + segmk.add_site_tag( + site, 'IFF.ZSRVAL_Q2', not d['SRVAL_Q2']) + segmk.add_site_tag( + site, 'IFF.ZSRVAL_Q3', not d['SRVAL_Q3']) + segmk.add_site_tag( + site, 'IFF.ZSRVAL_Q4', not d['SRVAL_Q4']) + + if 'IS_CLK_INVERTED' in d and not d['DISABLE_CLOCKS']: + if verilog.unquote(d['INTERFACE_TYPE']) == 'MEMORY_DDR3': + segmk.add_site_tag( + site, 'IFF.INV_CLK', d['IS_CLK_INVERTED']) + segmk.add_site_tag( + site, 'IFF.INV_CLKB', d['IS_CLKB_INVERTED']) + segmk.add_site_tag( + site, 'IFF.ZINV_CLK', not d['IS_CLK_INVERTED']) + segmk.add_site_tag( + site, 'IFF.ZINV_CLKB', not d['IS_CLKB_INVERTED']) + + segmk.add_site_tag( + site, 'IFF.ZINV_CLK_XOR', + d['IS_CLK_INVERTED'] ^ d['IS_CLKB_INVERTED']) + segmk.add_site_tag( + site, 'IFF.ZINV_CLK_NXOR', + not (d['IS_CLK_INVERTED'] ^ d['IS_CLKB_INVERTED'])) + + segmk.add_site_tag( + site, 'IFF.ZINV_CLK_OR', d['IS_CLK_INVERTED'] + or d['IS_CLKB_INVERTED']) + segmk.add_site_tag( + site, 'IFF.ZINV_CLK_NOR', not ( + d['IS_CLK_INVERTED'] or d['IS_CLKB_INVERTED'])) + segmk.add_site_tag( + site, 'IFF.ZINV_CLK_AND', d['IS_CLK_INVERTED'] + and d['IS_CLKB_INVERTED']) + segmk.add_site_tag( + site, 'IFF.ZINV_CLK_NAND', not ( + d['IS_CLK_INVERTED'] + and d['IS_CLKB_INVERTED'])) + + if 'IS_OCLK_INVERTED' in d and not d['DISABLE_CLOCKS']: + segmk.add_site_tag( + site, 'IFF.INV_OCLK', d['IS_OCLK_INVERTED']) + segmk.add_site_tag( + site, 'IFF.ZINV_OCLK', not d['IS_OCLK_INVERTED']) + segmk.add_site_tag( + site, 'IFF.INV_OCLKB', d['IS_OCLKB_INVERTED']) + segmk.add_site_tag( + site, 'IFF.ZINV_OCLKB', not d['IS_OCLKB_INVERTED']) + + if 'IS_CLKDIV_INVERTED' in d and not d['DISABLE_CLOCKS'] and \ + verilog.unquote(d['INTERFACE_TYPE']) == 'MEMORY': + segmk.add_site_tag( + site, 'IFF.INV_CLKDIV', d['IS_CLKDIV_INVERTED']) + segmk.add_site_tag( + site, 'IFF.ZINV_CLKDIV', not d['IS_CLKDIV_INVERTED']) + + if 'IS_C_INVERTED' in d: + segmk.add_site_tag( + site, 'IFF.ZINV_C', not d['IS_C_INVERTED']) + + segmk.add_site_tag(site, 'ZINV_D', not d['IS_D_INVERTED']) + + if 'SRTYPE' in d: + for opt in ['ASYNC', 'SYNC']: + segmk.add_site_tag( + site, 'IFF.SRTYPE.{}'.format(opt), + verilog.unquote(d['SRTYPE']) == opt) + + if 'DDR_CLK_EDGE' in d: + for opt in ['OPPOSITE_EDGE', 'SAME_EDGE', + 'SAME_EDGE_PIPELINED']: + segmk.add_site_tag( + site, 'IFF.DDR_CLK_EDGE.{}'.format(opt), + verilog.unquote(d['DDR_CLK_EDGE']) == opt) + + if d['iddr_mux_config'] == 'direct': + segmk.add_site_tag(site, 'IFFDELMUXE3.P0', 0) + segmk.add_site_tag(site, 'IFFDELMUXE3.P1', 1) + segmk.add_site_tag(site, 'IFFDELMUXE3.P2', 0) + elif d['iddr_mux_config'] == 'idelay': + segmk.add_site_tag(site, 'IFFDELMUXE3.P0', 1) + segmk.add_site_tag(site, 'IFFDELMUXE3.P1', 0) + segmk.add_site_tag(site, 'IFFDELMUXE3.P2', 0) + elif d['iddr_mux_config'] == 'none': + segmk.add_site_tag(site, 'IFFDELMUXE3.P0', 0) + segmk.add_site_tag(site, 'IFFDELMUXE3.P1', 0) + segmk.add_site_tag(site, 'IFFDELMUXE3.P2', 0) + else: + assert False, d['mux_config'] + + if d['mux_config'] == 'direct': + segmk.add_site_tag(site, 'IDELMUXE3.P0', 0) + segmk.add_site_tag(site, 'IDELMUXE3.P1', 1) + segmk.add_site_tag(site, 'IDELMUXE3.P2', 0) + + elif d['mux_config'] == 'idelay': + segmk.add_site_tag(site, 'IDELMUXE3.P0', 1) + segmk.add_site_tag(site, 'IDELMUXE3.P1', 0) + segmk.add_site_tag(site, 'IDELMUXE3.P2', 0) + + elif d['mux_config'] == 'none': + segmk.add_site_tag(site, 'IDELMUXE3.P0', 0) + segmk.add_site_tag(site, 'IDELMUXE3.P1', 0) + segmk.add_site_tag(site, 'IDELMUXE3.P2', 0) + else: + assert False, d['mux_config'] + + if DEBUG_FUZZER: + for k in d: + segmk.add_site_tag( + site, 'param_' + k + '_' + str(d[k]).replace( + ' ', '').replace('\n', ''), 1) + + segmk.compile(bitfilter=bitfilter) + segmk.write(allow_empty=True) + + +if __name__ == "__main__": + main() diff --git a/fuzzers/035-iob18-ilogic/generate.tcl b/fuzzers/035-iob18-ilogic/generate.tcl new file mode 100644 index 00000000..f631c021 --- /dev/null +++ b/fuzzers/035-iob18-ilogic/generate.tcl @@ -0,0 +1,39 @@ +# Copyright (C) 2017-2022 The Project X-Ray Authors +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC +create_project -force -part $::env(XRAY_PART) design design +read_verilog top.v +synth_design -top top + +set_property CFGBVS GND [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] +set_param tcl.collectionResultDisplayLimit 0 + +set_property IS_ENABLED 0 [get_drc_checks {NSTD-1}] +set_property IS_ENABLED 0 [get_drc_checks {UCIO-1}] +set_property IS_ENABLED 0 [get_drc_checks {REQP-79}] +set_property IS_ENABLED 0 [get_drc_checks {REQP-81}] +set_property IS_ENABLED 0 [get_drc_checks {REQP-84}] +set_property IS_ENABLED 0 [get_drc_checks {REQP-85}] +set_property IS_ENABLED 0 [get_drc_checks {REQP-87}] +set_property IS_ENABLED 0 [get_drc_checks {REQP-85}] +set_property IS_ENABLED 0 [get_drc_checks {AVAL-28}] +# ISERDES/ILOGIC fuzzer deliberately builds "invalid" clocking and D-inversion +# mux configs to observe their bits; suppress the DRCs that would block bitgen. +set_property IS_ENABLED 0 [get_drc_checks {REQP-105}] +set_property IS_ENABLED 0 [get_drc_checks {PDRC-26}] +set_property IS_ENABLED 0 [get_drc_checks {PDRC-158}] +set_property IS_ENABLED 0 [get_drc_checks {REQP-1580}] +set_property IS_ENABLED 0 [get_drc_checks {REQP-1581}] +set_property IS_ENABLED 0 [get_drc_checks {REQP-1582}] + +place_design +route_design + +write_checkpoint -force design.dcp +write_bitstream -force design.bit diff --git a/fuzzers/035-iob18-ilogic/params.csv b/fuzzers/035-iob18-ilogic/params.csv new file mode 100644 index 00000000..8a5d22ba --- /dev/null +++ b/fuzzers/035-iob18-ilogic/params.csv @@ -0,0 +1,672 @@ +tile,site,pin,iostandard,drive,slew +LIOB18_X81Y10,IOB_X0Y10,dio[0],LVCMOS18,6,FAST,PULLDOWN +LIOB18_X81Y101,IOB_X0Y97,dio[1],LVCMOS18,6,FAST,PULLUP +LIOB18_X81Y101,IOB_X0Y98,dio[2],LVCMOS18,4,FAST,PULLDOWN +LIOB18_X81Y106,IOB_X0Y101,dio[3],LVCMOS18,6,FAST,KEEPER +LIOB18_X81Y106,IOB_X0Y102,dio[4],LVCMOS18,6,FAST,PULLDOWN +LIOB18_X81Y108,IOB_X0Y103,dio[5],LVCMOS18,2,SLOW,KEEPER +LIOB18_X81Y108,IOB_X0Y104,dio[6],LVCMOS18,16,FAST,PULLUP +LIOB18_X81Y110,IOB_X0Y105,dio[7],LVCMOS18,16,SLOW,NONE +LIOB18_X81Y110,IOB_X0Y106,dio[8],LVCMOS18,2,FAST,PULLUP +LIOB18_X81Y112,IOB_X0Y107,dio[9],LVCMOS18,6,SLOW,PULLDOWN +LIOB18_X81Y112,IOB_X0Y108,dio[10],LVCMOS18,4,SLOW,NONE +LIOB18_X81Y114,IOB_X0Y109,dio[11],LVCMOS18,16,SLOW,PULLDOWN +LIOB18_X81Y114,IOB_X0Y110,dio[12],LVCMOS18,6,FAST,KEEPER +LIOB18_X81Y116,IOB_X0Y111,dio[13],LVCMOS18,8,FAST,NONE +LIOB18_X81Y116,IOB_X0Y112,dio[14],LVCMOS18,8,FAST,PULLUP +LIOB18_X81Y118,IOB_X0Y113,dio[15],LVCMOS18,12,SLOW,PULLUP +LIOB18_X81Y118,IOB_X0Y114,dio[16],LVCMOS18,6,FAST,NONE +LIOB18_X81Y12,IOB_X0Y11,dio[17],LVCMOS18,6,FAST,NONE +LIOB18_X81Y12,IOB_X0Y12,dio[18],LVCMOS18,8,FAST,PULLUP +LIOB18_X81Y120,IOB_X0Y115,dio[19],LVCMOS18,16,FAST,KEEPER +LIOB18_X81Y120,IOB_X0Y116,dio[20],LVCMOS18,6,SLOW,KEEPER +LIOB18_X81Y122,IOB_X0Y117,dio[21],LVCMOS18,6,FAST,KEEPER +LIOB18_X81Y122,IOB_X0Y118,dio[22],LVCMOS18,2,FAST,NONE +LIOB18_X81Y124,IOB_X0Y119,dio[23],LVCMOS18,12,SLOW,PULLDOWN +LIOB18_X81Y124,IOB_X0Y120,dio[24],LVCMOS18,12,SLOW,PULLUP +LIOB18_X81Y126,IOB_X0Y121,dio[25],LVCMOS18,8,FAST,PULLUP +LIOB18_X81Y126,IOB_X0Y122,dio[26],LVCMOS18,2,SLOW,PULLUP +LIOB18_X81Y128,IOB_X0Y123,dio[27],LVCMOS18,2,FAST,NONE +LIOB18_X81Y128,IOB_X0Y124,dio[28],LVCMOS18,16,FAST,PULLUP +LIOB18_X81Y131,IOB_X0Y125,dio[29],LVCMOS18,6,SLOW,PULLDOWN +LIOB18_X81Y131,IOB_X0Y126,dio[30],LVCMOS18,2,SLOW,PULLUP +LIOB18_X81Y133,IOB_X0Y127,dio[31],LVCMOS18,8,FAST,KEEPER +LIOB18_X81Y133,IOB_X0Y128,dio[32],LVCMOS18,16,FAST,NONE +LIOB18_X81Y135,IOB_X0Y129,dio[33],LVCMOS18,4,FAST,NONE +LIOB18_X81Y135,IOB_X0Y130,dio[34],LVCMOS18,4,FAST,NONE +LIOB18_X81Y137,IOB_X0Y131,dio[35],LVCMOS18,16,SLOW,PULLDOWN +LIOB18_X81Y137,IOB_X0Y132,dio[36],LVCMOS18,4,FAST,NONE +LIOB18_X81Y139,IOB_X0Y133,dio[37],LVCMOS18,12,SLOW,KEEPER +LIOB18_X81Y139,IOB_X0Y134,dio[38],LVCMOS18,4,SLOW,NONE +LIOB18_X81Y14,IOB_X0Y13,dio[39],LVCMOS18,8,SLOW,PULLUP +LIOB18_X81Y14,IOB_X0Y14,dio[40],LVCMOS18,4,FAST,KEEPER +LIOB18_X81Y141,IOB_X0Y135,dio[41],LVCMOS18,16,SLOW,PULLDOWN +LIOB18_X81Y141,IOB_X0Y136,dio[42],LVCMOS18,6,FAST,PULLUP +LIOB18_X81Y143,IOB_X0Y137,dio[43],LVCMOS18,12,SLOW,KEEPER +LIOB18_X81Y143,IOB_X0Y138,dio[44],LVCMOS18,4,FAST,PULLDOWN +LIOB18_X81Y145,IOB_X0Y139,dio[45],LVCMOS18,8,SLOW,PULLDOWN +LIOB18_X81Y145,IOB_X0Y140,dio[46],LVCMOS18,2,FAST,NONE +LIOB18_X81Y147,IOB_X0Y141,dio[47],LVCMOS18,2,SLOW,NONE +LIOB18_X81Y147,IOB_X0Y142,dio[48],LVCMOS18,8,SLOW,PULLUP +LIOB18_X81Y149,IOB_X0Y143,dio[49],LVCMOS18,16,FAST,PULLDOWN +LIOB18_X81Y149,IOB_X0Y144,dio[50],LVCMOS18,4,FAST,PULLDOWN +LIOB18_X81Y151,IOB_X0Y145,dio[51],LVCMOS18,6,FAST,KEEPER +LIOB18_X81Y151,IOB_X0Y146,dio[52],LVCMOS18,12,SLOW,NONE +LIOB18_X81Y153,IOB_X0Y147,dio[53],LVCMOS18,4,FAST,KEEPER +LIOB18_X81Y153,IOB_X0Y148,dio[54],LVCMOS18,16,SLOW,PULLDOWN +LIOB18_X81Y158,IOB_X0Y151,dio[55],LVCMOS18,16,SLOW,NONE +LIOB18_X81Y158,IOB_X0Y152,dio[56],LVCMOS18,4,SLOW,NONE +LIOB18_X81Y16,IOB_X0Y15,dio[57],LVCMOS18,8,SLOW,KEEPER +LIOB18_X81Y16,IOB_X0Y16,dio[58],LVCMOS18,12,SLOW,NONE +LIOB18_X81Y160,IOB_X0Y153,dio[59],LVCMOS18,2,FAST,PULLUP +LIOB18_X81Y160,IOB_X0Y154,dio[60],LVCMOS18,6,FAST,KEEPER +LIOB18_X81Y162,IOB_X0Y155,dio[61],LVCMOS18,4,FAST,NONE +LIOB18_X81Y162,IOB_X0Y156,dio[62],LVCMOS18,6,SLOW,PULLUP +LIOB18_X81Y164,IOB_X0Y157,dio[63],LVCMOS18,4,FAST,NONE +LIOB18_X81Y164,IOB_X0Y158,dio[64],LVCMOS18,2,FAST,PULLDOWN +LIOB18_X81Y166,IOB_X0Y159,dio[65],LVCMOS18,4,FAST,NONE +LIOB18_X81Y166,IOB_X0Y160,dio[66],LVCMOS18,16,SLOW,NONE +LIOB18_X81Y168,IOB_X0Y161,dio[67],LVCMOS18,6,SLOW,NONE +LIOB18_X81Y168,IOB_X0Y162,dio[68],LVCMOS18,4,SLOW,KEEPER +LIOB18_X81Y170,IOB_X0Y163,dio[69],LVCMOS18,12,FAST,PULLUP +LIOB18_X81Y170,IOB_X0Y164,dio[70],LVCMOS18,2,SLOW,NONE +LIOB18_X81Y172,IOB_X0Y165,dio[71],LVCMOS18,12,FAST,PULLUP +LIOB18_X81Y172,IOB_X0Y166,dio[72],LVCMOS18,8,SLOW,NONE +LIOB18_X81Y174,IOB_X0Y167,dio[73],LVCMOS18,8,FAST,PULLDOWN +LIOB18_X81Y174,IOB_X0Y168,dio[74],LVCMOS18,8,FAST,PULLUP +LIOB18_X81Y176,IOB_X0Y169,dio[75],LVCMOS18,16,FAST,PULLUP +LIOB18_X81Y176,IOB_X0Y170,dio[76],LVCMOS18,4,FAST,NONE +LIOB18_X81Y178,IOB_X0Y171,dio[77],LVCMOS18,8,SLOW,NONE +LIOB18_X81Y178,IOB_X0Y172,dio[78],LVCMOS18,12,SLOW,PULLDOWN +LIOB18_X81Y18,IOB_X0Y17,dio[79],LVCMOS18,12,FAST,PULLUP +LIOB18_X81Y18,IOB_X0Y18,dio[80],LVCMOS18,2,FAST,KEEPER +LIOB18_X81Y180,IOB_X0Y173,dio[81],LVCMOS18,8,SLOW,PULLUP +LIOB18_X81Y180,IOB_X0Y174,dio[82],LVCMOS18,16,SLOW,PULLDOWN +LIOB18_X81Y183,IOB_X0Y175,dio[83],LVCMOS18,6,SLOW,PULLDOWN +LIOB18_X81Y183,IOB_X0Y176,dio[84],LVCMOS18,8,FAST,PULLDOWN +LIOB18_X81Y185,IOB_X0Y177,dio[85],LVCMOS18,2,SLOW,NONE +LIOB18_X81Y185,IOB_X0Y178,dio[86],LVCMOS18,8,SLOW,PULLUP +LIOB18_X81Y187,IOB_X0Y179,dio[87],LVCMOS18,8,FAST,NONE +LIOB18_X81Y187,IOB_X0Y180,dio[88],LVCMOS18,16,SLOW,KEEPER +LIOB18_X81Y189,IOB_X0Y181,dio[89],LVCMOS18,16,SLOW,PULLUP +LIOB18_X81Y189,IOB_X0Y182,dio[90],LVCMOS18,6,FAST,NONE +LIOB18_X81Y191,IOB_X0Y183,dio[91],LVCMOS18,4,SLOW,KEEPER +LIOB18_X81Y191,IOB_X0Y184,dio[92],LVCMOS18,16,SLOW,NONE +LIOB18_X81Y193,IOB_X0Y185,dio[93],LVCMOS18,2,SLOW,KEEPER +LIOB18_X81Y193,IOB_X0Y186,dio[94],LVCMOS18,6,SLOW,PULLUP +LIOB18_X81Y195,IOB_X0Y187,dio[95],LVCMOS18,6,SLOW,PULLUP +LIOB18_X81Y195,IOB_X0Y188,dio[96],LVCMOS18,4,SLOW,KEEPER +LIOB18_X81Y197,IOB_X0Y189,dio[97],LVCMOS18,8,SLOW,PULLUP +LIOB18_X81Y197,IOB_X0Y190,dio[98],LVCMOS18,6,SLOW,PULLDOWN +LIOB18_X81Y199,IOB_X0Y191,dio[99],LVCMOS18,8,SLOW,NONE +LIOB18_X81Y199,IOB_X0Y192,dio[100],LVCMOS18,2,FAST,KEEPER +LIOB18_X81Y2,IOB_X0Y1,dio[101],LVCMOS18,12,SLOW,PULLDOWN +LIOB18_X81Y2,IOB_X0Y2,dio[102],LVCMOS18,6,SLOW,NONE +LIOB18_X81Y20,IOB_X0Y19,dio[103],LVCMOS18,6,SLOW,KEEPER +LIOB18_X81Y20,IOB_X0Y20,dio[104],LVCMOS18,6,FAST,PULLUP +LIOB18_X81Y201,IOB_X0Y193,dio[105],LVCMOS18,6,FAST,NONE +LIOB18_X81Y201,IOB_X0Y194,dio[106],LVCMOS18,2,SLOW,PULLDOWN +LIOB18_X81Y203,IOB_X0Y195,dio[107],LVCMOS18,2,SLOW,PULLDOWN +LIOB18_X81Y203,IOB_X0Y196,dio[108],LVCMOS18,2,SLOW,NONE +LIOB18_X81Y205,IOB_X0Y197,dio[109],LVCMOS18,12,SLOW,NONE +LIOB18_X81Y205,IOB_X0Y198,dio[110],LVCMOS18,16,FAST,PULLUP +LIOB18_X81Y210,IOB_X0Y201,dio[111],LVCMOS18,8,SLOW,KEEPER +LIOB18_X81Y210,IOB_X0Y202,dio[112],LVCMOS18,12,FAST,KEEPER +LIOB18_X81Y212,IOB_X0Y203,dio[113],LVCMOS18,6,FAST,KEEPER +LIOB18_X81Y212,IOB_X0Y204,dio[114],LVCMOS18,6,SLOW,NONE +LIOB18_X81Y214,IOB_X0Y205,dio[115],LVCMOS18,12,SLOW,PULLUP +LIOB18_X81Y214,IOB_X0Y206,dio[116],LVCMOS18,2,FAST,KEEPER +LIOB18_X81Y216,IOB_X0Y207,dio[117],LVCMOS18,6,SLOW,KEEPER +LIOB18_X81Y216,IOB_X0Y208,dio[118],LVCMOS18,6,FAST,PULLDOWN +LIOB18_X81Y218,IOB_X0Y209,dio[119],LVCMOS18,12,SLOW,PULLUP +LIOB18_X81Y218,IOB_X0Y210,dio[120],LVCMOS18,4,SLOW,PULLUP +LIOB18_X81Y22,IOB_X0Y21,dio[121],LVCMOS18,8,SLOW,PULLDOWN +LIOB18_X81Y22,IOB_X0Y22,dio[122],LVCMOS18,16,FAST,KEEPER +LIOB18_X81Y220,IOB_X0Y211,dio[123],LVCMOS18,12,SLOW,PULLUP +LIOB18_X81Y220,IOB_X0Y212,dio[124],LVCMOS18,2,FAST,KEEPER +LIOB18_X81Y222,IOB_X0Y213,dio[125],LVCMOS18,12,FAST,PULLDOWN +LIOB18_X81Y222,IOB_X0Y214,dio[126],LVCMOS18,2,SLOW,PULLDOWN +LIOB18_X81Y224,IOB_X0Y215,dio[127],LVCMOS18,4,SLOW,PULLUP +LIOB18_X81Y224,IOB_X0Y216,dio[128],LVCMOS18,6,FAST,NONE +LIOB18_X81Y226,IOB_X0Y217,dio[129],LVCMOS18,8,FAST,PULLDOWN +LIOB18_X81Y226,IOB_X0Y218,dio[130],LVCMOS18,2,FAST,KEEPER +LIOB18_X81Y228,IOB_X0Y219,dio[131],LVCMOS18,2,FAST,KEEPER +LIOB18_X81Y228,IOB_X0Y220,dio[132],LVCMOS18,6,SLOW,PULLUP +LIOB18_X81Y230,IOB_X0Y221,dio[133],LVCMOS18,2,SLOW,KEEPER +LIOB18_X81Y230,IOB_X0Y222,dio[134],LVCMOS18,16,FAST,PULLDOWN +LIOB18_X81Y232,IOB_X0Y223,dio[135],LVCMOS18,8,FAST,PULLUP +LIOB18_X81Y232,IOB_X0Y224,dio[136],LVCMOS18,6,SLOW,NONE +LIOB18_X81Y235,IOB_X0Y225,dio[137],LVCMOS18,16,SLOW,PULLUP +LIOB18_X81Y235,IOB_X0Y226,dio[138],LVCMOS18,8,FAST,KEEPER +LIOB18_X81Y237,IOB_X0Y227,dio[139],LVCMOS18,6,FAST,PULLUP +LIOB18_X81Y237,IOB_X0Y228,dio[140],LVCMOS18,16,SLOW,PULLDOWN +LIOB18_X81Y239,IOB_X0Y229,dio[141],LVCMOS18,12,FAST,PULLDOWN +LIOB18_X81Y239,IOB_X0Y230,dio[142],LVCMOS18,16,FAST,PULLUP +LIOB18_X81Y24,IOB_X0Y23,dio[143],LVCMOS18,4,SLOW,KEEPER +LIOB18_X81Y24,IOB_X0Y24,dio[144],LVCMOS18,12,SLOW,KEEPER +LIOB18_X81Y241,IOB_X0Y231,dio[145],LVCMOS18,12,SLOW,NONE +LIOB18_X81Y241,IOB_X0Y232,dio[146],LVCMOS18,16,FAST,KEEPER +LIOB18_X81Y243,IOB_X0Y233,dio[147],LVCMOS18,12,SLOW,NONE +LIOB18_X81Y243,IOB_X0Y234,dio[148],LVCMOS18,8,SLOW,PULLDOWN +LIOB18_X81Y245,IOB_X0Y235,dio[149],LVCMOS18,12,SLOW,PULLUP +LIOB18_X81Y245,IOB_X0Y236,dio[150],LVCMOS18,8,SLOW,PULLUP +LIOB18_X81Y247,IOB_X0Y237,dio[151],LVCMOS18,8,FAST,KEEPER +LIOB18_X81Y247,IOB_X0Y238,dio[152],LVCMOS18,2,FAST,PULLDOWN +LIOB18_X81Y249,IOB_X0Y239,dio[153],LVCMOS18,2,SLOW,KEEPER +LIOB18_X81Y249,IOB_X0Y240,dio[154],LVCMOS18,16,SLOW,NONE +LIOB18_X81Y251,IOB_X0Y241,dio[155],LVCMOS18,8,SLOW,KEEPER +LIOB18_X81Y251,IOB_X0Y242,dio[156],LVCMOS18,12,SLOW,KEEPER +LIOB18_X81Y253,IOB_X0Y243,dio[157],LVCMOS18,2,FAST,PULLUP +LIOB18_X81Y253,IOB_X0Y244,dio[158],LVCMOS18,16,FAST,PULLUP +LIOB18_X81Y255,IOB_X0Y245,dio[159],LVCMOS18,4,SLOW,NONE +LIOB18_X81Y255,IOB_X0Y246,dio[160],LVCMOS18,16,SLOW,PULLUP +LIOB18_X81Y257,IOB_X0Y247,dio[161],LVCMOS18,6,FAST,PULLDOWN +LIOB18_X81Y257,IOB_X0Y248,dio[162],LVCMOS18,12,SLOW,PULLDOWN +LIOB18_X81Y262,IOB_X0Y251,dio[163],LVCMOS18,16,SLOW,PULLUP +LIOB18_X81Y262,IOB_X0Y252,dio[164],LVCMOS18,6,SLOW,NONE +LIOB18_X81Y264,IOB_X0Y253,dio[165],LVCMOS18,12,SLOW,PULLUP +LIOB18_X81Y264,IOB_X0Y254,dio[166],LVCMOS18,6,SLOW,NONE +LIOB18_X81Y266,IOB_X0Y255,dio[167],LVCMOS18,6,FAST,KEEPER +LIOB18_X81Y266,IOB_X0Y256,dio[168],LVCMOS18,4,SLOW,PULLUP +LIOB18_X81Y268,IOB_X0Y257,dio[169],LVCMOS18,8,FAST,KEEPER +LIOB18_X81Y268,IOB_X0Y258,dio[170],LVCMOS18,6,FAST,PULLDOWN +LIOB18_X81Y27,IOB_X0Y25,dio[171],LVCMOS18,8,FAST,NONE +LIOB18_X81Y27,IOB_X0Y26,dio[172],LVCMOS18,8,FAST,NONE +LIOB18_X81Y270,IOB_X0Y259,dio[173],LVCMOS18,12,FAST,NONE +LIOB18_X81Y270,IOB_X0Y260,dio[174],LVCMOS18,8,SLOW,PULLUP +LIOB18_X81Y272,IOB_X0Y261,dio[175],LVCMOS18,12,SLOW,NONE +LIOB18_X81Y272,IOB_X0Y262,dio[176],LVCMOS18,12,FAST,KEEPER +LIOB18_X81Y274,IOB_X0Y263,dio[177],LVCMOS18,12,FAST,PULLUP +LIOB18_X81Y274,IOB_X0Y264,dio[178],LVCMOS18,2,SLOW,PULLDOWN +LIOB18_X81Y276,IOB_X0Y265,dio[179],LVCMOS18,2,FAST,KEEPER +LIOB18_X81Y276,IOB_X0Y266,dio[180],LVCMOS18,6,FAST,NONE +LIOB18_X81Y278,IOB_X0Y267,dio[181],LVCMOS18,6,SLOW,PULLDOWN +LIOB18_X81Y278,IOB_X0Y268,dio[182],LVCMOS18,4,FAST,PULLDOWN +LIOB18_X81Y280,IOB_X0Y269,dio[183],LVCMOS18,16,FAST,PULLUP +LIOB18_X81Y280,IOB_X0Y270,dio[184],LVCMOS18,12,FAST,PULLDOWN +LIOB18_X81Y282,IOB_X0Y271,dio[185],LVCMOS18,6,FAST,KEEPER +LIOB18_X81Y282,IOB_X0Y272,dio[186],LVCMOS18,2,SLOW,KEEPER +LIOB18_X81Y284,IOB_X0Y273,dio[187],LVCMOS18,12,SLOW,PULLDOWN +LIOB18_X81Y284,IOB_X0Y274,dio[188],LVCMOS18,2,SLOW,KEEPER +LIOB18_X81Y287,IOB_X0Y275,dio[189],LVCMOS18,4,FAST,PULLDOWN +LIOB18_X81Y287,IOB_X0Y276,dio[190],LVCMOS18,8,SLOW,KEEPER +LIOB18_X81Y289,IOB_X0Y277,dio[191],LVCMOS18,8,FAST,KEEPER +LIOB18_X81Y289,IOB_X0Y278,dio[192],LVCMOS18,2,FAST,PULLDOWN +LIOB18_X81Y29,IOB_X0Y27,dio[193],LVCMOS18,16,SLOW,PULLUP +LIOB18_X81Y29,IOB_X0Y28,dio[194],LVCMOS18,16,FAST,NONE +LIOB18_X81Y291,IOB_X0Y279,dio[195],LVCMOS18,2,FAST,NONE +LIOB18_X81Y291,IOB_X0Y280,dio[196],LVCMOS18,12,SLOW,KEEPER +LIOB18_X81Y293,IOB_X0Y281,dio[197],LVCMOS18,8,FAST,NONE +LIOB18_X81Y293,IOB_X0Y282,dio[198],LVCMOS18,16,FAST,PULLUP +LIOB18_X81Y295,IOB_X0Y283,dio[199],LVCMOS18,4,SLOW,KEEPER +LIOB18_X81Y295,IOB_X0Y284,dio[200],LVCMOS18,12,SLOW,KEEPER +LIOB18_X81Y297,IOB_X0Y285,dio[201],LVCMOS18,12,FAST,PULLUP +LIOB18_X81Y297,IOB_X0Y286,dio[202],LVCMOS18,2,FAST,NONE +LIOB18_X81Y299,IOB_X0Y287,dio[203],LVCMOS18,16,SLOW,PULLUP +LIOB18_X81Y299,IOB_X0Y288,dio[204],LVCMOS18,12,SLOW,PULLDOWN +LIOB18_X81Y301,IOB_X0Y289,dio[205],LVCMOS18,8,SLOW,NONE +LIOB18_X81Y301,IOB_X0Y290,dio[206],LVCMOS18,12,FAST,KEEPER +LIOB18_X81Y303,IOB_X0Y291,dio[207],LVCMOS18,12,FAST,KEEPER +LIOB18_X81Y303,IOB_X0Y292,dio[208],LVCMOS18,8,FAST,PULLUP +LIOB18_X81Y305,IOB_X0Y293,dio[209],LVCMOS18,6,SLOW,KEEPER +LIOB18_X81Y305,IOB_X0Y294,dio[210],LVCMOS18,6,SLOW,NONE +LIOB18_X81Y307,IOB_X0Y295,dio[211],LVCMOS18,8,SLOW,PULLUP +LIOB18_X81Y307,IOB_X0Y296,dio[212],LVCMOS18,6,SLOW,PULLUP +LIOB18_X81Y309,IOB_X0Y297,dio[213],LVCMOS18,8,SLOW,PULLDOWN +LIOB18_X81Y309,IOB_X0Y298,dio[214],LVCMOS18,4,FAST,PULLDOWN +LIOB18_X81Y31,IOB_X0Y29,dio[215],LVCMOS18,4,SLOW,NONE +LIOB18_X81Y31,IOB_X0Y30,dio[216],LVCMOS18,12,SLOW,PULLDOWN +LIOB18_X81Y314,IOB_X0Y301,dio[217],LVCMOS18,8,SLOW,PULLDOWN +LIOB18_X81Y314,IOB_X0Y302,dio[218],LVCMOS18,2,FAST,PULLUP +LIOB18_X81Y316,IOB_X0Y303,dio[219],LVCMOS18,8,FAST,KEEPER +LIOB18_X81Y316,IOB_X0Y304,dio[220],LVCMOS18,12,SLOW,NONE +LIOB18_X81Y318,IOB_X0Y305,dio[221],LVCMOS18,8,SLOW,PULLDOWN +LIOB18_X81Y318,IOB_X0Y306,dio[222],LVCMOS18,12,SLOW,NONE +LIOB18_X81Y320,IOB_X0Y307,dio[223],LVCMOS18,12,SLOW,KEEPER +LIOB18_X81Y320,IOB_X0Y308,dio[224],LVCMOS18,8,FAST,PULLUP +LIOB18_X81Y322,IOB_X0Y309,dio[225],LVCMOS18,12,FAST,NONE +LIOB18_X81Y322,IOB_X0Y310,dio[226],LVCMOS18,8,SLOW,KEEPER +LIOB18_X81Y324,IOB_X0Y311,dio[227],LVCMOS18,12,SLOW,NONE +LIOB18_X81Y324,IOB_X0Y312,dio[228],LVCMOS18,4,SLOW,KEEPER +LIOB18_X81Y326,IOB_X0Y313,dio[229],LVCMOS18,8,FAST,PULLUP +LIOB18_X81Y326,IOB_X0Y314,dio[230],LVCMOS18,16,FAST,KEEPER +LIOB18_X81Y328,IOB_X0Y315,dio[231],LVCMOS18,16,SLOW,PULLUP +LIOB18_X81Y328,IOB_X0Y316,dio[232],LVCMOS18,6,FAST,NONE +LIOB18_X81Y33,IOB_X0Y31,dio[233],LVCMOS18,8,FAST,PULLUP +LIOB18_X81Y33,IOB_X0Y32,dio[234],LVCMOS18,6,FAST,PULLUP +LIOB18_X81Y330,IOB_X0Y317,dio[235],LVCMOS18,16,FAST,KEEPER +LIOB18_X81Y330,IOB_X0Y318,dio[236],LVCMOS18,16,SLOW,PULLUP +LIOB18_X81Y332,IOB_X0Y319,dio[237],LVCMOS18,8,SLOW,PULLDOWN +LIOB18_X81Y332,IOB_X0Y320,dio[238],LVCMOS18,16,FAST,PULLDOWN +LIOB18_X81Y334,IOB_X0Y321,dio[239],LVCMOS18,12,SLOW,KEEPER +LIOB18_X81Y334,IOB_X0Y322,dio[240],LVCMOS18,2,SLOW,KEEPER +LIOB18_X81Y336,IOB_X0Y323,dio[241],LVCMOS18,8,SLOW,KEEPER +LIOB18_X81Y336,IOB_X0Y324,dio[242],LVCMOS18,8,SLOW,NONE +LIOB18_X81Y339,IOB_X0Y325,dio[243],LVCMOS18,6,FAST,PULLDOWN +LIOB18_X81Y339,IOB_X0Y326,dio[244],LVCMOS18,4,SLOW,NONE +LIOB18_X81Y341,IOB_X0Y327,dio[245],LVCMOS18,6,FAST,PULLUP +LIOB18_X81Y341,IOB_X0Y328,dio[246],LVCMOS18,2,SLOW,NONE +LIOB18_X81Y343,IOB_X0Y329,dio[247],LVCMOS18,12,SLOW,PULLUP +LIOB18_X81Y343,IOB_X0Y330,dio[248],LVCMOS18,2,FAST,NONE +LIOB18_X81Y345,IOB_X0Y331,dio[249],LVCMOS18,16,FAST,NONE +LIOB18_X81Y345,IOB_X0Y332,dio[250],LVCMOS18,12,FAST,NONE +LIOB18_X81Y347,IOB_X0Y333,dio[251],LVCMOS18,6,SLOW,NONE +LIOB18_X81Y347,IOB_X0Y334,dio[252],LVCMOS18,4,FAST,NONE +LIOB18_X81Y349,IOB_X0Y335,dio[253],LVCMOS18,4,FAST,PULLDOWN +LIOB18_X81Y349,IOB_X0Y336,dio[254],LVCMOS18,16,SLOW,KEEPER +LIOB18_X81Y35,IOB_X0Y33,dio[255],LVCMOS18,2,FAST,PULLUP +LIOB18_X81Y35,IOB_X0Y34,dio[256],LVCMOS18,12,FAST,PULLDOWN +LIOB18_X81Y351,IOB_X0Y337,dio[257],LVCMOS18,2,SLOW,NONE +LIOB18_X81Y351,IOB_X0Y338,dio[258],LVCMOS18,12,FAST,NONE +LIOB18_X81Y353,IOB_X0Y339,dio[259],LVCMOS18,8,SLOW,NONE +LIOB18_X81Y353,IOB_X0Y340,dio[260],LVCMOS18,16,FAST,NONE +LIOB18_X81Y355,IOB_X0Y341,dio[261],LVCMOS18,6,FAST,PULLUP +LIOB18_X81Y355,IOB_X0Y342,dio[262],LVCMOS18,16,FAST,KEEPER +LIOB18_X81Y357,IOB_X0Y343,dio[263],LVCMOS18,2,SLOW,PULLDOWN +LIOB18_X81Y357,IOB_X0Y344,dio[264],LVCMOS18,6,SLOW,PULLDOWN +LIOB18_X81Y359,IOB_X0Y345,dio[265],LVCMOS18,12,SLOW,PULLDOWN +LIOB18_X81Y359,IOB_X0Y346,dio[266],LVCMOS18,6,FAST,PULLDOWN +LIOB18_X81Y361,IOB_X0Y347,dio[267],LVCMOS18,12,FAST,PULLDOWN +LIOB18_X81Y361,IOB_X0Y348,dio[268],LVCMOS18,16,FAST,PULLUP +LIOB18_X81Y37,IOB_X0Y35,dio[269],LVCMOS18,6,FAST,PULLDOWN +LIOB18_X81Y37,IOB_X0Y36,dio[270],LVCMOS18,2,FAST,NONE +LIOB18_X81Y39,IOB_X0Y37,dio[271],LVCMOS18,6,FAST,PULLUP +LIOB18_X81Y39,IOB_X0Y38,dio[272],LVCMOS18,16,FAST,KEEPER +LIOB18_X81Y4,IOB_X0Y3,dio[273],LVCMOS18,16,SLOW,KEEPER +LIOB18_X81Y4,IOB_X0Y4,dio[274],LVCMOS18,8,FAST,PULLUP +LIOB18_X81Y41,IOB_X0Y39,dio[275],LVCMOS18,12,SLOW,KEEPER +LIOB18_X81Y41,IOB_X0Y40,dio[276],LVCMOS18,8,SLOW,PULLUP +LIOB18_X81Y43,IOB_X0Y41,dio[277],LVCMOS18,16,SLOW,NONE +LIOB18_X81Y43,IOB_X0Y42,dio[278],LVCMOS18,6,FAST,PULLDOWN +LIOB18_X81Y45,IOB_X0Y43,dio[279],LVCMOS18,16,SLOW,KEEPER +LIOB18_X81Y45,IOB_X0Y44,dio[280],LVCMOS18,16,SLOW,NONE +LIOB18_X81Y47,IOB_X0Y45,dio[281],LVCMOS18,4,FAST,KEEPER +LIOB18_X81Y47,IOB_X0Y46,dio[282],LVCMOS18,4,FAST,NONE +LIOB18_X81Y49,IOB_X0Y47,dio[283],LVCMOS18,12,SLOW,NONE +LIOB18_X81Y49,IOB_X0Y48,dio[284],LVCMOS18,8,FAST,KEEPER +LIOB18_X81Y54,IOB_X0Y51,dio[285],LVCMOS18,12,FAST,KEEPER +LIOB18_X81Y54,IOB_X0Y52,dio[286],LVCMOS18,2,SLOW,PULLDOWN +LIOB18_X81Y56,IOB_X0Y53,dio[287],LVCMOS18,16,FAST,NONE +LIOB18_X81Y56,IOB_X0Y54,dio[288],LVCMOS18,8,SLOW,KEEPER +LIOB18_X81Y58,IOB_X0Y55,dio[289],LVCMOS18,4,SLOW,KEEPER +LIOB18_X81Y58,IOB_X0Y56,dio[290],LVCMOS18,8,FAST,PULLDOWN +LIOB18_X81Y6,IOB_X0Y5,dio[291],LVCMOS18,8,SLOW,KEEPER +LIOB18_X81Y6,IOB_X0Y6,dio[292],LVCMOS18,6,SLOW,PULLUP +LIOB18_X81Y60,IOB_X0Y57,dio[293],LVCMOS18,16,FAST,PULLDOWN +LIOB18_X81Y60,IOB_X0Y58,dio[294],LVCMOS18,6,SLOW,KEEPER +LIOB18_X81Y62,IOB_X0Y59,dio[295],LVCMOS18,6,FAST,KEEPER +LIOB18_X81Y62,IOB_X0Y60,dio[296],LVCMOS18,6,FAST,PULLDOWN +LIOB18_X81Y64,IOB_X0Y61,dio[297],LVCMOS18,8,SLOW,PULLUP +LIOB18_X81Y64,IOB_X0Y62,dio[298],LVCMOS18,2,SLOW,NONE +LIOB18_X81Y66,IOB_X0Y63,dio[299],LVCMOS18,16,FAST,PULLUP +LIOB18_X81Y66,IOB_X0Y64,dio[300],LVCMOS18,16,SLOW,PULLUP +LIOB18_X81Y68,IOB_X0Y65,dio[301],LVCMOS18,2,SLOW,KEEPER +LIOB18_X81Y68,IOB_X0Y66,dio[302],LVCMOS18,4,FAST,KEEPER +LIOB18_X81Y70,IOB_X0Y67,dio[303],LVCMOS18,2,FAST,PULLUP +LIOB18_X81Y70,IOB_X0Y68,dio[304],LVCMOS18,4,SLOW,NONE +LIOB18_X81Y72,IOB_X0Y69,dio[305],LVCMOS18,4,SLOW,KEEPER +LIOB18_X81Y72,IOB_X0Y70,dio[306],LVCMOS18,8,SLOW,PULLDOWN +LIOB18_X81Y74,IOB_X0Y71,dio[307],LVCMOS18,2,FAST,PULLDOWN +LIOB18_X81Y74,IOB_X0Y72,dio[308],LVCMOS18,6,SLOW,NONE +LIOB18_X81Y76,IOB_X0Y73,dio[309],LVCMOS18,8,SLOW,NONE +LIOB18_X81Y76,IOB_X0Y74,dio[310],LVCMOS18,12,FAST,KEEPER +LIOB18_X81Y79,IOB_X0Y75,dio[311],LVCMOS18,2,SLOW,KEEPER +LIOB18_X81Y79,IOB_X0Y76,dio[312],LVCMOS18,12,SLOW,NONE +LIOB18_X81Y8,IOB_X0Y7,dio[313],LVCMOS18,4,SLOW,PULLDOWN +LIOB18_X81Y8,IOB_X0Y8,dio[314],LVCMOS18,12,FAST,NONE +LIOB18_X81Y81,IOB_X0Y77,dio[315],LVCMOS18,12,SLOW,KEEPER +LIOB18_X81Y81,IOB_X0Y78,dio[316],LVCMOS18,2,FAST,NONE +LIOB18_X81Y83,IOB_X0Y79,dio[317],LVCMOS18,16,FAST,NONE +LIOB18_X81Y83,IOB_X0Y80,dio[318],LVCMOS18,16,SLOW,PULLDOWN +LIOB18_X81Y85,IOB_X0Y81,dio[319],LVCMOS18,4,SLOW,PULLDOWN +LIOB18_X81Y85,IOB_X0Y82,dio[320],LVCMOS18,4,FAST,PULLDOWN +LIOB18_X81Y87,IOB_X0Y83,dio[321],LVCMOS18,8,SLOW,PULLUP +LIOB18_X81Y87,IOB_X0Y84,dio[322],LVCMOS18,6,FAST,NONE +LIOB18_X81Y89,IOB_X0Y85,dio[323],LVCMOS18,16,FAST,PULLDOWN +LIOB18_X81Y89,IOB_X0Y86,dio[324],LVCMOS18,16,SLOW,KEEPER +LIOB18_X81Y91,IOB_X0Y87,dio[325],LVCMOS18,6,SLOW,KEEPER +LIOB18_X81Y91,IOB_X0Y88,dio[326],LVCMOS18,8,SLOW,PULLUP +LIOB18_X81Y93,IOB_X0Y89,dio[327],LVCMOS18,8,SLOW,PULLUP +LIOB18_X81Y93,IOB_X0Y90,dio[328],LVCMOS18,16,FAST,NONE +LIOB18_X81Y95,IOB_X0Y91,dio[329],LVCMOS18,12,FAST,PULLUP +LIOB18_X81Y95,IOB_X0Y92,dio[330],LVCMOS18,16,FAST,PULLUP +LIOB18_X81Y97,IOB_X0Y93,dio[331],LVCMOS18,16,FAST,PULLUP +LIOB18_X81Y97,IOB_X0Y94,dio[332],LVCMOS18,12,SLOW,PULLUP +LIOB18_X81Y99,IOB_X0Y95,dio[333],LVCMOS18,6,FAST,PULLUP +LIOB18_X81Y99,IOB_X0Y96,dio[334],LVCMOS18,4,FAST,NONE +RIOB18_X312Y10,IOB_X1Y9,dio[335],LVCMOS18,6,SLOW,PULLDOWN +RIOB18_X312Y10,IOB_X1Y10,dio[336],LVCMOS18,2,FAST,PULLUP +RIOB18_X312Y101,IOB_X1Y97,dio[337],LVCMOS18,4,FAST,PULLUP +RIOB18_X312Y101,IOB_X1Y98,dio[338],LVCMOS18,6,SLOW,KEEPER +RIOB18_X312Y106,IOB_X1Y101,dio[339],LVCMOS18,12,SLOW,PULLUP +RIOB18_X312Y106,IOB_X1Y102,dio[340],LVCMOS18,6,SLOW,PULLUP +RIOB18_X312Y108,IOB_X1Y103,dio[341],LVCMOS18,8,FAST,NONE +RIOB18_X312Y108,IOB_X1Y104,dio[342],LVCMOS18,6,SLOW,PULLDOWN +RIOB18_X312Y110,IOB_X1Y105,dio[343],LVCMOS18,6,FAST,PULLUP +RIOB18_X312Y110,IOB_X1Y106,dio[344],LVCMOS18,2,FAST,KEEPER +RIOB18_X312Y112,IOB_X1Y107,dio[345],LVCMOS18,2,FAST,NONE +RIOB18_X312Y112,IOB_X1Y108,dio[346],LVCMOS18,6,SLOW,NONE +RIOB18_X312Y114,IOB_X1Y109,dio[347],LVCMOS18,8,FAST,PULLUP +RIOB18_X312Y114,IOB_X1Y110,dio[348],LVCMOS18,16,FAST,PULLUP +RIOB18_X312Y116,IOB_X1Y111,dio[349],LVCMOS18,16,FAST,PULLDOWN +RIOB18_X312Y116,IOB_X1Y112,dio[350],LVCMOS18,12,SLOW,PULLUP +RIOB18_X312Y118,IOB_X1Y113,dio[351],LVCMOS18,8,SLOW,PULLUP +RIOB18_X312Y118,IOB_X1Y114,dio[352],LVCMOS18,4,FAST,KEEPER +RIOB18_X312Y12,IOB_X1Y11,dio[353],LVCMOS18,2,FAST,KEEPER +RIOB18_X312Y12,IOB_X1Y12,dio[354],LVCMOS18,4,SLOW,PULLUP +RIOB18_X312Y120,IOB_X1Y115,dio[355],LVCMOS18,6,SLOW,KEEPER +RIOB18_X312Y120,IOB_X1Y116,dio[356],LVCMOS18,16,SLOW,PULLDOWN +RIOB18_X312Y122,IOB_X1Y117,dio[357],LVCMOS18,16,SLOW,PULLUP +RIOB18_X312Y122,IOB_X1Y118,dio[358],LVCMOS18,6,FAST,PULLDOWN +RIOB18_X312Y124,IOB_X1Y119,dio[359],LVCMOS18,6,FAST,NONE +RIOB18_X312Y124,IOB_X1Y120,dio[360],LVCMOS18,2,FAST,PULLDOWN +RIOB18_X312Y126,IOB_X1Y121,dio[361],LVCMOS18,12,FAST,PULLUP +RIOB18_X312Y126,IOB_X1Y122,dio[362],LVCMOS18,12,FAST,KEEPER +RIOB18_X312Y128,IOB_X1Y123,dio[363],LVCMOS18,6,SLOW,PULLDOWN +RIOB18_X312Y128,IOB_X1Y124,dio[364],LVCMOS18,6,FAST,NONE +RIOB18_X312Y131,IOB_X1Y125,dio[365],LVCMOS18,4,FAST,PULLUP +RIOB18_X312Y131,IOB_X1Y126,dio[366],LVCMOS18,6,FAST,NONE +RIOB18_X312Y133,IOB_X1Y127,dio[367],LVCMOS18,2,SLOW,PULLDOWN +RIOB18_X312Y133,IOB_X1Y128,dio[368],LVCMOS18,8,SLOW,NONE +RIOB18_X312Y135,IOB_X1Y129,dio[369],LVCMOS18,12,SLOW,KEEPER +RIOB18_X312Y135,IOB_X1Y130,dio[370],LVCMOS18,12,SLOW,NONE +RIOB18_X312Y137,IOB_X1Y131,dio[371],LVCMOS18,4,SLOW,PULLDOWN +RIOB18_X312Y137,IOB_X1Y132,dio[372],LVCMOS18,6,SLOW,PULLDOWN +RIOB18_X312Y139,IOB_X1Y133,dio[373],LVCMOS18,16,SLOW,PULLUP +RIOB18_X312Y139,IOB_X1Y134,dio[374],LVCMOS18,8,FAST,KEEPER +RIOB18_X312Y14,IOB_X1Y13,dio[375],LVCMOS18,8,SLOW,NONE +RIOB18_X312Y14,IOB_X1Y14,dio[376],LVCMOS18,16,SLOW,PULLUP +RIOB18_X312Y141,IOB_X1Y135,dio[377],LVCMOS18,16,FAST,KEEPER +RIOB18_X312Y141,IOB_X1Y136,dio[378],LVCMOS18,2,FAST,NONE +RIOB18_X312Y143,IOB_X1Y137,dio[379],LVCMOS18,2,FAST,KEEPER +RIOB18_X312Y143,IOB_X1Y138,dio[380],LVCMOS18,6,SLOW,PULLUP +RIOB18_X312Y145,IOB_X1Y139,dio[381],LVCMOS18,6,FAST,PULLDOWN +RIOB18_X312Y145,IOB_X1Y140,dio[382],LVCMOS18,8,FAST,NONE +RIOB18_X312Y147,IOB_X1Y141,dio[383],LVCMOS18,4,FAST,NONE +RIOB18_X312Y147,IOB_X1Y142,dio[384],LVCMOS18,4,FAST,NONE +RIOB18_X312Y149,IOB_X1Y143,dio[385],LVCMOS18,8,SLOW,NONE +RIOB18_X312Y149,IOB_X1Y144,dio[386],LVCMOS18,12,SLOW,NONE +RIOB18_X312Y151,IOB_X1Y145,dio[387],LVCMOS18,12,SLOW,PULLDOWN +RIOB18_X312Y151,IOB_X1Y146,dio[388],LVCMOS18,16,SLOW,KEEPER +RIOB18_X312Y153,IOB_X1Y147,dio[389],LVCMOS18,12,FAST,PULLDOWN +RIOB18_X312Y153,IOB_X1Y148,dio[390],LVCMOS18,16,SLOW,KEEPER +RIOB18_X312Y158,IOB_X1Y151,dio[391],LVCMOS18,4,SLOW,KEEPER +RIOB18_X312Y158,IOB_X1Y152,dio[392],LVCMOS18,8,SLOW,PULLDOWN +RIOB18_X312Y16,IOB_X1Y15,dio[393],LVCMOS18,16,SLOW,KEEPER +RIOB18_X312Y16,IOB_X1Y16,dio[394],LVCMOS18,12,SLOW,PULLUP +RIOB18_X312Y160,IOB_X1Y153,dio[395],LVCMOS18,4,SLOW,PULLDOWN +RIOB18_X312Y160,IOB_X1Y154,dio[396],LVCMOS18,6,SLOW,KEEPER +RIOB18_X312Y162,IOB_X1Y155,dio[397],LVCMOS18,2,FAST,KEEPER +RIOB18_X312Y162,IOB_X1Y156,dio[398],LVCMOS18,8,SLOW,PULLUP +RIOB18_X312Y164,IOB_X1Y157,dio[399],LVCMOS18,8,FAST,PULLUP +RIOB18_X312Y164,IOB_X1Y158,dio[400],LVCMOS18,8,SLOW,NONE +RIOB18_X312Y166,IOB_X1Y159,dio[401],LVCMOS18,8,FAST,NONE +RIOB18_X312Y166,IOB_X1Y160,dio[402],LVCMOS18,2,SLOW,NONE +RIOB18_X312Y168,IOB_X1Y161,dio[403],LVCMOS18,6,SLOW,KEEPER +RIOB18_X312Y168,IOB_X1Y162,dio[404],LVCMOS18,6,FAST,NONE +RIOB18_X312Y170,IOB_X1Y163,dio[405],LVCMOS18,4,SLOW,PULLDOWN +RIOB18_X312Y170,IOB_X1Y164,dio[406],LVCMOS18,4,FAST,PULLDOWN +RIOB18_X312Y172,IOB_X1Y165,dio[407],LVCMOS18,8,SLOW,NONE +RIOB18_X312Y172,IOB_X1Y166,dio[408],LVCMOS18,6,SLOW,KEEPER +RIOB18_X312Y174,IOB_X1Y167,dio[409],LVCMOS18,2,FAST,PULLDOWN +RIOB18_X312Y174,IOB_X1Y168,dio[410],LVCMOS18,16,FAST,KEEPER +RIOB18_X312Y176,IOB_X1Y169,dio[411],LVCMOS18,16,FAST,NONE +RIOB18_X312Y176,IOB_X1Y170,dio[412],LVCMOS18,12,SLOW,KEEPER +RIOB18_X312Y178,IOB_X1Y171,dio[413],LVCMOS18,8,FAST,PULLUP +RIOB18_X312Y178,IOB_X1Y172,dio[414],LVCMOS18,16,FAST,KEEPER +RIOB18_X312Y18,IOB_X1Y17,dio[415],LVCMOS18,8,SLOW,PULLDOWN +RIOB18_X312Y18,IOB_X1Y18,dio[416],LVCMOS18,8,SLOW,NONE +RIOB18_X312Y180,IOB_X1Y173,dio[417],LVCMOS18,12,SLOW,PULLDOWN +RIOB18_X312Y180,IOB_X1Y174,dio[418],LVCMOS18,6,FAST,PULLDOWN +RIOB18_X312Y183,IOB_X1Y175,dio[419],LVCMOS18,4,FAST,PULLUP +RIOB18_X312Y183,IOB_X1Y176,dio[420],LVCMOS18,6,SLOW,PULLUP +RIOB18_X312Y185,IOB_X1Y177,dio[421],LVCMOS18,12,FAST,PULLUP +RIOB18_X312Y185,IOB_X1Y178,dio[422],LVCMOS18,2,SLOW,PULLDOWN +RIOB18_X312Y187,IOB_X1Y179,dio[423],LVCMOS18,4,FAST,NONE +RIOB18_X312Y187,IOB_X1Y180,dio[424],LVCMOS18,4,FAST,NONE +RIOB18_X312Y189,IOB_X1Y181,dio[425],LVCMOS18,16,FAST,PULLUP +RIOB18_X312Y189,IOB_X1Y182,dio[426],LVCMOS18,6,SLOW,PULLDOWN +RIOB18_X312Y191,IOB_X1Y183,dio[427],LVCMOS18,6,SLOW,NONE +RIOB18_X312Y191,IOB_X1Y184,dio[428],LVCMOS18,16,SLOW,PULLDOWN +RIOB18_X312Y193,IOB_X1Y185,dio[429],LVCMOS18,8,FAST,PULLUP +RIOB18_X312Y193,IOB_X1Y186,dio[430],LVCMOS18,12,FAST,PULLUP +RIOB18_X312Y195,IOB_X1Y187,dio[431],LVCMOS18,4,FAST,NONE +RIOB18_X312Y195,IOB_X1Y188,dio[432],LVCMOS18,8,SLOW,PULLUP +RIOB18_X312Y197,IOB_X1Y189,dio[433],LVCMOS18,16,FAST,PULLDOWN +RIOB18_X312Y197,IOB_X1Y190,dio[434],LVCMOS18,4,SLOW,NONE +RIOB18_X312Y199,IOB_X1Y191,dio[435],LVCMOS18,8,FAST,NONE +RIOB18_X312Y199,IOB_X1Y192,dio[436],LVCMOS18,6,SLOW,PULLUP +RIOB18_X312Y2,IOB_X1Y1,dio[437],LVCMOS18,8,SLOW,NONE +RIOB18_X312Y2,IOB_X1Y2,dio[438],LVCMOS18,6,SLOW,KEEPER +RIOB18_X312Y20,IOB_X1Y19,dio[439],LVCMOS18,12,FAST,PULLUP +RIOB18_X312Y20,IOB_X1Y20,dio[440],LVCMOS18,16,SLOW,PULLUP +RIOB18_X312Y201,IOB_X1Y193,dio[441],LVCMOS18,12,SLOW,NONE +RIOB18_X312Y201,IOB_X1Y194,dio[442],LVCMOS18,8,SLOW,KEEPER +RIOB18_X312Y203,IOB_X1Y195,dio[443],LVCMOS18,6,FAST,PULLDOWN +RIOB18_X312Y203,IOB_X1Y196,dio[444],LVCMOS18,16,SLOW,PULLDOWN +RIOB18_X312Y205,IOB_X1Y197,dio[445],LVCMOS18,16,SLOW,PULLUP +RIOB18_X312Y205,IOB_X1Y198,dio[446],LVCMOS18,6,FAST,NONE +RIOB18_X312Y210,IOB_X1Y201,dio[447],LVCMOS18,4,FAST,KEEPER +RIOB18_X312Y210,IOB_X1Y202,dio[448],LVCMOS18,8,FAST,PULLDOWN +RIOB18_X312Y212,IOB_X1Y203,dio[449],LVCMOS18,2,SLOW,PULLUP +RIOB18_X312Y212,IOB_X1Y204,dio[450],LVCMOS18,6,SLOW,KEEPER +RIOB18_X312Y214,IOB_X1Y205,dio[451],LVCMOS18,12,FAST,PULLDOWN +RIOB18_X312Y214,IOB_X1Y206,dio[452],LVCMOS18,8,FAST,NONE +RIOB18_X312Y216,IOB_X1Y207,dio[453],LVCMOS18,8,FAST,KEEPER +RIOB18_X312Y216,IOB_X1Y208,dio[454],LVCMOS18,12,SLOW,NONE +RIOB18_X312Y218,IOB_X1Y209,dio[455],LVCMOS18,8,SLOW,KEEPER +RIOB18_X312Y218,IOB_X1Y210,dio[456],LVCMOS18,4,SLOW,PULLDOWN +RIOB18_X312Y22,IOB_X1Y21,dio[457],LVCMOS18,16,SLOW,PULLDOWN +RIOB18_X312Y22,IOB_X1Y22,dio[458],LVCMOS18,16,SLOW,KEEPER +RIOB18_X312Y220,IOB_X1Y211,dio[459],LVCMOS18,2,SLOW,NONE +RIOB18_X312Y220,IOB_X1Y212,dio[460],LVCMOS18,12,FAST,KEEPER +RIOB18_X312Y222,IOB_X1Y213,dio[461],LVCMOS18,6,FAST,PULLDOWN +RIOB18_X312Y222,IOB_X1Y214,dio[462],LVCMOS18,2,FAST,NONE +RIOB18_X312Y224,IOB_X1Y215,dio[463],LVCMOS18,16,FAST,NONE +RIOB18_X312Y224,IOB_X1Y216,dio[464],LVCMOS18,12,FAST,NONE +RIOB18_X312Y226,IOB_X1Y217,dio[465],LVCMOS18,6,FAST,PULLUP +RIOB18_X312Y226,IOB_X1Y218,dio[466],LVCMOS18,6,SLOW,PULLDOWN +RIOB18_X312Y228,IOB_X1Y219,dio[467],LVCMOS18,8,FAST,NONE +RIOB18_X312Y228,IOB_X1Y220,dio[468],LVCMOS18,8,SLOW,PULLDOWN +RIOB18_X312Y230,IOB_X1Y221,dio[469],LVCMOS18,4,SLOW,PULLDOWN +RIOB18_X312Y230,IOB_X1Y222,dio[470],LVCMOS18,16,FAST,NONE +RIOB18_X312Y232,IOB_X1Y223,dio[471],LVCMOS18,8,FAST,NONE +RIOB18_X312Y232,IOB_X1Y224,dio[472],LVCMOS18,8,SLOW,PULLDOWN +RIOB18_X312Y235,IOB_X1Y225,dio[473],LVCMOS18,4,SLOW,PULLDOWN +RIOB18_X312Y235,IOB_X1Y226,dio[474],LVCMOS18,8,SLOW,PULLDOWN +RIOB18_X312Y237,IOB_X1Y227,dio[475],LVCMOS18,16,FAST,PULLDOWN +RIOB18_X312Y237,IOB_X1Y228,dio[476],LVCMOS18,8,SLOW,KEEPER +RIOB18_X312Y239,IOB_X1Y229,dio[477],LVCMOS18,4,SLOW,NONE +RIOB18_X312Y239,IOB_X1Y230,dio[478],LVCMOS18,8,SLOW,KEEPER +RIOB18_X312Y24,IOB_X1Y23,dio[479],LVCMOS18,16,SLOW,NONE +RIOB18_X312Y24,IOB_X1Y24,dio[480],LVCMOS18,6,SLOW,KEEPER +RIOB18_X312Y241,IOB_X1Y231,dio[481],LVCMOS18,8,SLOW,NONE +RIOB18_X312Y241,IOB_X1Y232,dio[482],LVCMOS18,6,SLOW,PULLUP +RIOB18_X312Y243,IOB_X1Y233,dio[483],LVCMOS18,2,SLOW,PULLDOWN +RIOB18_X312Y243,IOB_X1Y234,dio[484],LVCMOS18,2,SLOW,PULLUP +RIOB18_X312Y245,IOB_X1Y235,dio[485],LVCMOS18,6,SLOW,KEEPER +RIOB18_X312Y245,IOB_X1Y236,dio[486],LVCMOS18,8,SLOW,PULLDOWN +RIOB18_X312Y247,IOB_X1Y237,dio[487],LVCMOS18,16,FAST,NONE +RIOB18_X312Y247,IOB_X1Y238,dio[488],LVCMOS18,2,SLOW,NONE +RIOB18_X312Y249,IOB_X1Y239,dio[489],LVCMOS18,16,FAST,PULLUP +RIOB18_X312Y249,IOB_X1Y240,dio[490],LVCMOS18,2,SLOW,PULLDOWN +RIOB18_X312Y251,IOB_X1Y241,dio[491],LVCMOS18,12,FAST,PULLUP +RIOB18_X312Y251,IOB_X1Y242,dio[492],LVCMOS18,8,SLOW,KEEPER +RIOB18_X312Y253,IOB_X1Y243,dio[493],LVCMOS18,6,SLOW,PULLUP +RIOB18_X312Y253,IOB_X1Y244,dio[494],LVCMOS18,16,FAST,KEEPER +RIOB18_X312Y255,IOB_X1Y245,dio[495],LVCMOS18,2,SLOW,PULLDOWN +RIOB18_X312Y255,IOB_X1Y246,dio[496],LVCMOS18,2,SLOW,NONE +RIOB18_X312Y257,IOB_X1Y247,dio[497],LVCMOS18,8,SLOW,PULLUP +RIOB18_X312Y257,IOB_X1Y248,dio[498],LVCMOS18,16,SLOW,PULLUP +RIOB18_X312Y262,IOB_X1Y251,dio[499],LVCMOS18,16,SLOW,PULLDOWN +RIOB18_X312Y262,IOB_X1Y252,dio[500],LVCMOS18,2,SLOW,KEEPER +RIOB18_X312Y264,IOB_X1Y253,dio[501],LVCMOS18,6,FAST,PULLDOWN +RIOB18_X312Y264,IOB_X1Y254,dio[502],LVCMOS18,16,SLOW,NONE +RIOB18_X312Y266,IOB_X1Y255,dio[503],LVCMOS18,12,SLOW,KEEPER +RIOB18_X312Y266,IOB_X1Y256,dio[504],LVCMOS18,12,FAST,PULLDOWN +RIOB18_X312Y268,IOB_X1Y257,dio[505],LVCMOS18,6,FAST,KEEPER +RIOB18_X312Y268,IOB_X1Y258,dio[506],LVCMOS18,4,FAST,NONE +RIOB18_X312Y27,IOB_X1Y25,dio[507],LVCMOS18,16,FAST,NONE +RIOB18_X312Y27,IOB_X1Y26,dio[508],LVCMOS18,8,FAST,KEEPER +RIOB18_X312Y270,IOB_X1Y259,dio[509],LVCMOS18,2,FAST,PULLDOWN +RIOB18_X312Y270,IOB_X1Y260,dio[510],LVCMOS18,2,FAST,PULLUP +RIOB18_X312Y272,IOB_X1Y261,dio[511],LVCMOS18,16,SLOW,PULLDOWN +RIOB18_X312Y272,IOB_X1Y262,dio[512],LVCMOS18,4,SLOW,PULLDOWN +RIOB18_X312Y274,IOB_X1Y263,dio[513],LVCMOS18,8,FAST,PULLUP +RIOB18_X312Y274,IOB_X1Y264,dio[514],LVCMOS18,16,FAST,NONE +RIOB18_X312Y276,IOB_X1Y265,dio[515],LVCMOS18,4,FAST,PULLDOWN +RIOB18_X312Y276,IOB_X1Y266,dio[516],LVCMOS18,6,SLOW,PULLUP +RIOB18_X312Y278,IOB_X1Y267,dio[517],LVCMOS18,8,SLOW,NONE +RIOB18_X312Y278,IOB_X1Y268,dio[518],LVCMOS18,4,SLOW,PULLUP +RIOB18_X312Y280,IOB_X1Y269,dio[519],LVCMOS18,12,FAST,PULLUP +RIOB18_X312Y280,IOB_X1Y270,dio[520],LVCMOS18,16,SLOW,PULLUP +RIOB18_X312Y282,IOB_X1Y271,dio[521],LVCMOS18,16,SLOW,NONE +RIOB18_X312Y282,IOB_X1Y272,dio[522],LVCMOS18,8,SLOW,PULLDOWN +RIOB18_X312Y284,IOB_X1Y273,dio[523],LVCMOS18,8,SLOW,PULLDOWN +RIOB18_X312Y284,IOB_X1Y274,dio[524],LVCMOS18,2,SLOW,KEEPER +RIOB18_X312Y287,IOB_X1Y275,dio[525],LVCMOS18,2,FAST,PULLDOWN +RIOB18_X312Y287,IOB_X1Y276,dio[526],LVCMOS18,6,FAST,PULLDOWN +RIOB18_X312Y289,IOB_X1Y277,dio[527],LVCMOS18,16,SLOW,PULLDOWN +RIOB18_X312Y289,IOB_X1Y278,dio[528],LVCMOS18,4,FAST,PULLDOWN +RIOB18_X312Y29,IOB_X1Y27,dio[529],LVCMOS18,4,SLOW,PULLDOWN +RIOB18_X312Y29,IOB_X1Y28,dio[530],LVCMOS18,8,FAST,NONE +RIOB18_X312Y291,IOB_X1Y279,dio[531],LVCMOS18,8,SLOW,PULLDOWN +RIOB18_X312Y291,IOB_X1Y280,dio[532],LVCMOS18,16,FAST,PULLDOWN +RIOB18_X312Y293,IOB_X1Y281,dio[533],LVCMOS18,8,FAST,PULLDOWN +RIOB18_X312Y293,IOB_X1Y282,dio[534],LVCMOS18,6,SLOW,NONE +RIOB18_X312Y295,IOB_X1Y283,dio[535],LVCMOS18,2,FAST,NONE +RIOB18_X312Y295,IOB_X1Y284,dio[536],LVCMOS18,8,FAST,NONE +RIOB18_X312Y297,IOB_X1Y285,dio[537],LVCMOS18,16,FAST,PULLDOWN +RIOB18_X312Y297,IOB_X1Y286,dio[538],LVCMOS18,4,SLOW,KEEPER +RIOB18_X312Y299,IOB_X1Y287,dio[539],LVCMOS18,12,SLOW,PULLUP +RIOB18_X312Y299,IOB_X1Y288,dio[540],LVCMOS18,6,SLOW,PULLDOWN +RIOB18_X312Y301,IOB_X1Y289,dio[541],LVCMOS18,2,SLOW,PULLDOWN +RIOB18_X312Y301,IOB_X1Y290,dio[542],LVCMOS18,4,SLOW,PULLUP +RIOB18_X312Y303,IOB_X1Y291,dio[543],LVCMOS18,16,FAST,PULLUP +RIOB18_X312Y303,IOB_X1Y292,dio[544],LVCMOS18,16,SLOW,KEEPER +RIOB18_X312Y305,IOB_X1Y293,dio[545],LVCMOS18,12,FAST,NONE +RIOB18_X312Y305,IOB_X1Y294,dio[546],LVCMOS18,8,FAST,KEEPER +RIOB18_X312Y307,IOB_X1Y295,dio[547],LVCMOS18,12,SLOW,NONE +RIOB18_X312Y307,IOB_X1Y296,dio[548],LVCMOS18,16,SLOW,PULLUP +RIOB18_X312Y309,IOB_X1Y297,dio[549],LVCMOS18,4,FAST,KEEPER +RIOB18_X312Y309,IOB_X1Y298,dio[550],LVCMOS18,4,SLOW,NONE +RIOB18_X312Y31,IOB_X1Y29,dio[551],LVCMOS18,6,SLOW,KEEPER +RIOB18_X312Y31,IOB_X1Y30,dio[552],LVCMOS18,2,SLOW,NONE +RIOB18_X312Y314,IOB_X1Y301,dio[553],LVCMOS18,2,SLOW,KEEPER +RIOB18_X312Y314,IOB_X1Y302,dio[554],LVCMOS18,8,FAST,KEEPER +RIOB18_X312Y316,IOB_X1Y303,dio[555],LVCMOS18,2,FAST,KEEPER +RIOB18_X312Y316,IOB_X1Y304,dio[556],LVCMOS18,6,FAST,PULLUP +RIOB18_X312Y318,IOB_X1Y305,dio[557],LVCMOS18,16,FAST,PULLUP +RIOB18_X312Y318,IOB_X1Y306,dio[558],LVCMOS18,4,SLOW,PULLUP +RIOB18_X312Y320,IOB_X1Y307,dio[559],LVCMOS18,8,SLOW,PULLDOWN +RIOB18_X312Y320,IOB_X1Y308,dio[560],LVCMOS18,8,SLOW,PULLDOWN +RIOB18_X312Y322,IOB_X1Y309,dio[561],LVCMOS18,6,SLOW,PULLDOWN +RIOB18_X312Y322,IOB_X1Y310,dio[562],LVCMOS18,4,FAST,KEEPER +RIOB18_X312Y324,IOB_X1Y311,dio[563],LVCMOS18,4,FAST,KEEPER +RIOB18_X312Y324,IOB_X1Y312,dio[564],LVCMOS18,6,FAST,NONE +RIOB18_X312Y326,IOB_X1Y313,dio[565],LVCMOS18,8,FAST,PULLUP +RIOB18_X312Y326,IOB_X1Y314,dio[566],LVCMOS18,6,SLOW,PULLUP +RIOB18_X312Y328,IOB_X1Y315,dio[567],LVCMOS18,12,FAST,NONE +RIOB18_X312Y328,IOB_X1Y316,dio[568],LVCMOS18,2,FAST,PULLUP +RIOB18_X312Y33,IOB_X1Y31,dio[569],LVCMOS18,12,FAST,NONE +RIOB18_X312Y33,IOB_X1Y32,dio[570],LVCMOS18,12,FAST,PULLUP +RIOB18_X312Y330,IOB_X1Y317,dio[571],LVCMOS18,4,FAST,KEEPER +RIOB18_X312Y330,IOB_X1Y318,dio[572],LVCMOS18,8,FAST,NONE +RIOB18_X312Y332,IOB_X1Y319,dio[573],LVCMOS18,8,SLOW,KEEPER +RIOB18_X312Y332,IOB_X1Y320,dio[574],LVCMOS18,12,FAST,NONE +RIOB18_X312Y334,IOB_X1Y321,dio[575],LVCMOS18,16,FAST,NONE +RIOB18_X312Y334,IOB_X1Y322,dio[576],LVCMOS18,16,SLOW,KEEPER +RIOB18_X312Y336,IOB_X1Y323,dio[577],LVCMOS18,6,FAST,NONE +RIOB18_X312Y336,IOB_X1Y324,dio[578],LVCMOS18,4,FAST,NONE +RIOB18_X312Y339,IOB_X1Y325,dio[579],LVCMOS18,16,FAST,KEEPER +RIOB18_X312Y339,IOB_X1Y326,dio[580],LVCMOS18,16,SLOW,NONE +RIOB18_X312Y341,IOB_X1Y327,dio[581],LVCMOS18,6,SLOW,NONE +RIOB18_X312Y341,IOB_X1Y328,dio[582],LVCMOS18,2,SLOW,PULLUP +RIOB18_X312Y343,IOB_X1Y329,dio[583],LVCMOS18,16,SLOW,PULLUP +RIOB18_X312Y343,IOB_X1Y330,dio[584],LVCMOS18,8,SLOW,KEEPER +RIOB18_X312Y345,IOB_X1Y331,dio[585],LVCMOS18,12,SLOW,PULLUP +RIOB18_X312Y345,IOB_X1Y332,dio[586],LVCMOS18,16,FAST,PULLUP +RIOB18_X312Y347,IOB_X1Y333,dio[587],LVCMOS18,8,FAST,NONE +RIOB18_X312Y347,IOB_X1Y334,dio[588],LVCMOS18,6,SLOW,KEEPER +RIOB18_X312Y349,IOB_X1Y335,dio[589],LVCMOS18,4,FAST,PULLUP +RIOB18_X312Y349,IOB_X1Y336,dio[590],LVCMOS18,12,SLOW,PULLDOWN +RIOB18_X312Y35,IOB_X1Y33,dio[591],LVCMOS18,6,SLOW,PULLDOWN +RIOB18_X312Y35,IOB_X1Y34,dio[592],LVCMOS18,4,SLOW,PULLUP +RIOB18_X312Y351,IOB_X1Y337,dio[593],LVCMOS18,6,SLOW,KEEPER +RIOB18_X312Y351,IOB_X1Y338,dio[594],LVCMOS18,8,FAST,KEEPER +RIOB18_X312Y353,IOB_X1Y339,dio[595],LVCMOS18,6,FAST,PULLDOWN +RIOB18_X312Y353,IOB_X1Y340,dio[596],LVCMOS18,6,SLOW,KEEPER +RIOB18_X312Y355,IOB_X1Y341,dio[597],LVCMOS18,8,FAST,NONE +RIOB18_X312Y355,IOB_X1Y342,dio[598],LVCMOS18,8,SLOW,PULLDOWN +RIOB18_X312Y357,IOB_X1Y343,dio[599],LVCMOS18,6,FAST,NONE +RIOB18_X312Y357,IOB_X1Y344,dio[600],LVCMOS18,8,SLOW,KEEPER +RIOB18_X312Y359,IOB_X1Y345,dio[601],LVCMOS18,8,SLOW,NONE +RIOB18_X312Y359,IOB_X1Y346,dio[602],LVCMOS18,16,SLOW,PULLDOWN +RIOB18_X312Y361,IOB_X1Y347,dio[603],LVCMOS18,8,FAST,NONE +RIOB18_X312Y361,IOB_X1Y348,dio[604],LVCMOS18,6,FAST,PULLDOWN +RIOB18_X312Y37,IOB_X1Y35,dio[605],LVCMOS18,4,SLOW,KEEPER +RIOB18_X312Y37,IOB_X1Y36,dio[606],LVCMOS18,12,SLOW,PULLDOWN +RIOB18_X312Y39,IOB_X1Y37,dio[607],LVCMOS18,4,FAST,PULLUP +RIOB18_X312Y39,IOB_X1Y38,dio[608],LVCMOS18,6,FAST,PULLDOWN +RIOB18_X312Y4,IOB_X1Y3,dio[609],LVCMOS18,16,FAST,PULLDOWN +RIOB18_X312Y4,IOB_X1Y4,dio[610],LVCMOS18,12,SLOW,PULLUP +RIOB18_X312Y41,IOB_X1Y39,dio[611],LVCMOS18,6,SLOW,NONE +RIOB18_X312Y41,IOB_X1Y40,dio[612],LVCMOS18,16,SLOW,NONE +RIOB18_X312Y43,IOB_X1Y41,dio[613],LVCMOS18,16,FAST,NONE +RIOB18_X312Y43,IOB_X1Y42,dio[614],LVCMOS18,12,FAST,PULLUP +RIOB18_X312Y45,IOB_X1Y43,dio[615],LVCMOS18,6,FAST,PULLDOWN +RIOB18_X312Y45,IOB_X1Y44,dio[616],LVCMOS18,6,SLOW,PULLDOWN +RIOB18_X312Y47,IOB_X1Y45,dio[617],LVCMOS18,12,FAST,PULLUP +RIOB18_X312Y47,IOB_X1Y46,dio[618],LVCMOS18,2,SLOW,NONE +RIOB18_X312Y49,IOB_X1Y47,dio[619],LVCMOS18,2,FAST,PULLUP +RIOB18_X312Y49,IOB_X1Y48,dio[620],LVCMOS18,4,SLOW,PULLDOWN +RIOB18_X312Y54,IOB_X1Y51,dio[621],LVCMOS18,12,SLOW,PULLDOWN +RIOB18_X312Y54,IOB_X1Y52,dio[622],LVCMOS18,2,FAST,PULLDOWN +RIOB18_X312Y56,IOB_X1Y53,dio[623],LVCMOS18,6,SLOW,NONE +RIOB18_X312Y56,IOB_X1Y54,dio[624],LVCMOS18,4,SLOW,PULLDOWN +RIOB18_X312Y58,IOB_X1Y55,dio[625],LVCMOS18,8,SLOW,KEEPER +RIOB18_X312Y58,IOB_X1Y56,dio[626],LVCMOS18,12,SLOW,PULLUP +RIOB18_X312Y6,IOB_X1Y5,dio[627],LVCMOS18,6,SLOW,PULLUP +RIOB18_X312Y6,IOB_X1Y6,dio[628],LVCMOS18,16,FAST,PULLDOWN +RIOB18_X312Y60,IOB_X1Y57,dio[629],LVCMOS18,8,FAST,KEEPER +RIOB18_X312Y60,IOB_X1Y58,dio[630],LVCMOS18,2,FAST,PULLDOWN +RIOB18_X312Y62,IOB_X1Y59,dio[631],LVCMOS18,6,SLOW,PULLUP +RIOB18_X312Y62,IOB_X1Y60,dio[632],LVCMOS18,4,SLOW,PULLDOWN +RIOB18_X312Y64,IOB_X1Y61,dio[633],LVCMOS18,2,FAST,KEEPER +RIOB18_X312Y64,IOB_X1Y62,dio[634],LVCMOS18,2,SLOW,PULLUP +RIOB18_X312Y66,IOB_X1Y63,dio[635],LVCMOS18,6,FAST,PULLUP +RIOB18_X312Y66,IOB_X1Y64,dio[636],LVCMOS18,6,FAST,PULLDOWN +RIOB18_X312Y68,IOB_X1Y65,dio[637],LVCMOS18,4,SLOW,KEEPER +RIOB18_X312Y68,IOB_X1Y66,dio[638],LVCMOS18,2,FAST,PULLUP +RIOB18_X312Y70,IOB_X1Y67,dio[639],LVCMOS18,12,SLOW,NONE +RIOB18_X312Y70,IOB_X1Y68,dio[640],LVCMOS18,16,FAST,PULLDOWN +RIOB18_X312Y72,IOB_X1Y69,dio[641],LVCMOS18,8,FAST,PULLDOWN +RIOB18_X312Y72,IOB_X1Y70,dio[642],LVCMOS18,8,FAST,PULLDOWN +RIOB18_X312Y74,IOB_X1Y71,dio[643],LVCMOS18,12,SLOW,NONE +RIOB18_X312Y74,IOB_X1Y72,dio[644],LVCMOS18,6,FAST,KEEPER +RIOB18_X312Y76,IOB_X1Y73,dio[645],LVCMOS18,2,SLOW,KEEPER +RIOB18_X312Y76,IOB_X1Y74,dio[646],LVCMOS18,4,FAST,NONE +RIOB18_X312Y79,IOB_X1Y75,dio[647],LVCMOS18,2,SLOW,NONE +RIOB18_X312Y79,IOB_X1Y76,dio[648],LVCMOS18,6,SLOW,KEEPER +RIOB18_X312Y8,IOB_X1Y7,dio[649],LVCMOS18,6,SLOW,PULLDOWN +RIOB18_X312Y8,IOB_X1Y8,dio[650],LVCMOS18,16,FAST,PULLUP +RIOB18_X312Y81,IOB_X1Y77,dio[651],LVCMOS18,2,SLOW,NONE +RIOB18_X312Y81,IOB_X1Y78,dio[652],LVCMOS18,2,FAST,KEEPER +RIOB18_X312Y83,IOB_X1Y79,dio[653],LVCMOS18,8,FAST,NONE +RIOB18_X312Y83,IOB_X1Y80,dio[654],LVCMOS18,4,FAST,NONE +RIOB18_X312Y85,IOB_X1Y81,dio[655],LVCMOS18,12,FAST,KEEPER +RIOB18_X312Y85,IOB_X1Y82,dio[656],LVCMOS18,6,FAST,PULLDOWN +RIOB18_X312Y87,IOB_X1Y83,dio[657],LVCMOS18,12,SLOW,KEEPER +RIOB18_X312Y87,IOB_X1Y84,dio[658],LVCMOS18,6,FAST,NONE +RIOB18_X312Y89,IOB_X1Y85,dio[659],LVCMOS18,4,FAST,KEEPER +RIOB18_X312Y89,IOB_X1Y86,dio[660],LVCMOS18,12,SLOW,PULLUP +RIOB18_X312Y91,IOB_X1Y87,dio[661],LVCMOS18,6,SLOW,NONE +RIOB18_X312Y91,IOB_X1Y88,dio[662],LVCMOS18,12,SLOW,NONE +RIOB18_X312Y93,IOB_X1Y89,dio[663],LVCMOS18,6,FAST,KEEPER +RIOB18_X312Y93,IOB_X1Y90,dio[664],LVCMOS18,8,FAST,PULLDOWN +RIOB18_X312Y95,IOB_X1Y91,dio[665],LVCMOS18,2,SLOW,NONE +RIOB18_X312Y95,IOB_X1Y92,dio[666],LVCMOS18,4,FAST,PULLDOWN +RIOB18_X312Y97,IOB_X1Y93,dio[667],LVCMOS18,12,FAST,KEEPER +RIOB18_X312Y97,IOB_X1Y94,dio[668],LVCMOS18,8,SLOW,KEEPER +RIOB18_X312Y99,IOB_X1Y95,dio[669],LVCMOS18,4,FAST,KEEPER +RIOB18_X312Y99,IOB_X1Y96,dio[670],LVCMOS18,8,FAST,KEEPER diff --git a/fuzzers/035-iob18-ilogic/params.jl b/fuzzers/035-iob18-ilogic/params.jl new file mode 100644 index 00000000..1762b1dc --- /dev/null +++ b/fuzzers/035-iob18-ilogic/params.jl @@ -0,0 +1,22846 @@ +[ + { + "tile": "LIOB18_X81Y10", + "site": "IOB_X0Y10", + "ilogic_loc": "ILOGIC_X0Y10", + "ologic_loc": "OLOGIC_X0Y10", + "idelay_loc": "IDELAY_X0Y10", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[0]", + "owire": "do_buf[0]", + "iwire": "di_buf[0]", + "twire": "t[0]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y101", + "site": "IOB_X0Y97", + "ilogic_loc": "ILOGIC_X0Y97", + "ologic_loc": "OLOGIC_X0Y97", + "idelay_loc": "IDELAY_X0Y97", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[1]", + "owire": "do_buf[1]", + "iwire": "di_buf[1]", + "twire": "t[1]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 2, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y97),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y101", + "site": "IOB_X0Y98", + "ilogic_loc": "ILOGIC_X0Y98", + "ologic_loc": "OLOGIC_X0Y98", + "idelay_loc": "IDELAY_X0Y98", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[2]", + "owire": "do_buf[2]", + "iwire": "di_buf[2]", + "twire": "t[2]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 5, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 2, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y98),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y106", + "site": "IOB_X0Y101", + "ilogic_loc": "ILOGIC_X0Y101", + "ologic_loc": "OLOGIC_X0Y101", + "idelay_loc": "IDELAY_X0Y101", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[3]", + "owire": "do_buf[3]", + "iwire": "di_buf[3]", + "twire": "t[3]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y106", + "site": "IOB_X0Y102", + "ilogic_loc": "ILOGIC_X0Y102", + "ologic_loc": "OLOGIC_X0Y102", + "idelay_loc": "IDELAY_X0Y102", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[4]", + "owire": "do_buf[4]", + "iwire": "di_buf[4]", + "twire": "t[4]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y102),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y108", + "site": "IOB_X0Y103", + "ilogic_loc": "ILOGIC_X0Y103", + "ologic_loc": "OLOGIC_X0Y103", + "idelay_loc": "IDELAY_X0Y103", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[5]", + "owire": "do_buf[5]", + "iwire": "di_buf[5]", + "twire": "t[5]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 7, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y103),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y103),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y108", + "site": "IOB_X0Y104", + "ilogic_loc": "ILOGIC_X0Y104", + "ologic_loc": "OLOGIC_X0Y104", + "idelay_loc": "IDELAY_X0Y104", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[6]", + "owire": "do_buf[6]", + "iwire": "di_buf[6]", + "twire": "t[6]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y104),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 3, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y104),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y110", + "site": "IOB_X0Y105", + "ilogic_loc": "ILOGIC_X0Y105", + "ologic_loc": "OLOGIC_X0Y105", + "idelay_loc": "IDELAY_X0Y105", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[7]", + "owire": "do_buf[7]", + "iwire": "di_buf[7]", + "twire": "t[7]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y110", + "site": "IOB_X0Y106", + "ilogic_loc": "ILOGIC_X0Y106", + "ologic_loc": "OLOGIC_X0Y106", + "idelay_loc": "IDELAY_X0Y106", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[8]", + "owire": "do_buf[8]", + "iwire": "di_buf[8]", + "twire": "t[8]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y112", + "site": "IOB_X0Y107", + "ilogic_loc": "ILOGIC_X0Y107", + "ologic_loc": "OLOGIC_X0Y107", + "idelay_loc": "IDELAY_X0Y107", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[9]", + "owire": "do_buf[9]", + "iwire": "di_buf[9]", + "twire": "t[9]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y107),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y112", + "site": "IOB_X0Y108", + "ilogic_loc": "ILOGIC_X0Y108", + "ologic_loc": "OLOGIC_X0Y108", + "idelay_loc": "IDELAY_X0Y108", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[10]", + "owire": "do_buf[10]", + "iwire": "di_buf[10]", + "twire": "t[10]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y108),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y114", + "site": "IOB_X0Y109", + "ilogic_loc": "ILOGIC_X0Y109", + "ologic_loc": "OLOGIC_X0Y109", + "idelay_loc": "IDELAY_X0Y109", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[11]", + "owire": "do_buf[11]", + "iwire": "di_buf[11]", + "twire": "t[11]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 7, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 2, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y109),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y114", + "site": "IOB_X0Y110", + "ilogic_loc": "ILOGIC_X0Y110", + "ologic_loc": "OLOGIC_X0Y110", + "idelay_loc": "IDELAY_X0Y110", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[12]", + "owire": "do_buf[12]", + "iwire": "di_buf[12]", + "twire": "t[12]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 2, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y110),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y116", + "site": "IOB_X0Y111", + "ilogic_loc": "ILOGIC_X0Y111", + "ologic_loc": "OLOGIC_X0Y111", + "idelay_loc": "IDELAY_X0Y111", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[13]", + "owire": "do_buf[13]", + "iwire": "di_buf[13]", + "twire": "t[13]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 2, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y111),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y111),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y116", + "site": "IOB_X0Y112", + "ilogic_loc": "ILOGIC_X0Y112", + "ologic_loc": "OLOGIC_X0Y112", + "idelay_loc": "IDELAY_X0Y112", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[14]", + "owire": "do_buf[14]", + "iwire": "di_buf[14]", + "twire": "t[14]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 3, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y112),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y118", + "site": "IOB_X0Y113", + "ilogic_loc": "ILOGIC_X0Y113", + "ologic_loc": "OLOGIC_X0Y113", + "idelay_loc": "IDELAY_X0Y113", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[15]", + "owire": "do_buf[15]", + "iwire": "di_buf[15]", + "twire": "t[15]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y118", + "site": "IOB_X0Y114", + "ilogic_loc": "ILOGIC_X0Y114", + "ologic_loc": "OLOGIC_X0Y114", + "idelay_loc": "IDELAY_X0Y114", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[16]", + "owire": "do_buf[16]", + "iwire": "di_buf[16]", + "twire": "t[16]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y114),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y12", + "site": "IOB_X0Y11", + "ilogic_loc": "ILOGIC_X0Y11", + "ologic_loc": "OLOGIC_X0Y11", + "idelay_loc": "IDELAY_X0Y11", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[17]", + "owire": "do_buf[17]", + "iwire": "di_buf[17]", + "twire": "t[17]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y11),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y12", + "site": "IOB_X0Y12", + "ilogic_loc": "ILOGIC_X0Y12", + "ologic_loc": "OLOGIC_X0Y12", + "idelay_loc": "IDELAY_X0Y12", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[18]", + "owire": "do_buf[18]", + "iwire": "di_buf[18]", + "twire": "t[18]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y120", + "site": "IOB_X0Y115", + "ilogic_loc": "ILOGIC_X0Y115", + "ologic_loc": "OLOGIC_X0Y115", + "idelay_loc": "IDELAY_X0Y115", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[19]", + "owire": "do_buf[19]", + "iwire": "di_buf[19]", + "twire": "t[19]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y120", + "site": "IOB_X0Y116", + "ilogic_loc": "ILOGIC_X0Y116", + "ologic_loc": "OLOGIC_X0Y116", + "idelay_loc": "IDELAY_X0Y116", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[20]", + "owire": "do_buf[20]", + "iwire": "di_buf[20]", + "twire": "t[20]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y122", + "site": "IOB_X0Y117", + "ilogic_loc": "ILOGIC_X0Y117", + "ologic_loc": "OLOGIC_X0Y117", + "idelay_loc": "IDELAY_X0Y117", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[21]", + "owire": "do_buf[21]", + "iwire": "di_buf[21]", + "twire": "t[21]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y117),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y122", + "site": "IOB_X0Y118", + "ilogic_loc": "ILOGIC_X0Y118", + "ologic_loc": "OLOGIC_X0Y118", + "idelay_loc": "IDELAY_X0Y118", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[22]", + "owire": "do_buf[22]", + "iwire": "di_buf[22]", + "twire": "t[22]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y118),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y124", + "site": "IOB_X0Y119", + "ilogic_loc": "ILOGIC_X0Y119", + "ologic_loc": "OLOGIC_X0Y119", + "idelay_loc": "IDELAY_X0Y119", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[23]", + "owire": "do_buf[23]", + "iwire": "di_buf[23]", + "twire": "t[23]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y124", + "site": "IOB_X0Y120", + "ilogic_loc": "ILOGIC_X0Y120", + "ologic_loc": "OLOGIC_X0Y120", + "idelay_loc": "IDELAY_X0Y120", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[24]", + "owire": "do_buf[24]", + "iwire": "di_buf[24]", + "twire": "t[24]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y126", + "site": "IOB_X0Y121", + "ilogic_loc": "ILOGIC_X0Y121", + "ologic_loc": "OLOGIC_X0Y121", + "idelay_loc": "IDELAY_X0Y121", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[25]", + "owire": "do_buf[25]", + "iwire": "di_buf[25]", + "twire": "t[25]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "LIOB18_X81Y126", + "site": "IOB_X0Y122", + "ilogic_loc": "ILOGIC_X0Y122", + "ologic_loc": "OLOGIC_X0Y122", + "idelay_loc": "IDELAY_X0Y122", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[26]", + "owire": "do_buf[26]", + "iwire": "di_buf[26]", + "twire": "t[26]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y128", + "site": "IOB_X0Y123", + "ilogic_loc": "ILOGIC_X0Y123", + "ologic_loc": "OLOGIC_X0Y123", + "idelay_loc": "IDELAY_X0Y123", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[27]", + "owire": "do_buf[27]", + "iwire": "di_buf[27]", + "twire": "t[27]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y128", + "site": "IOB_X0Y124", + "ilogic_loc": "ILOGIC_X0Y124", + "ologic_loc": "OLOGIC_X0Y124", + "idelay_loc": "IDELAY_X0Y124", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[28]", + "owire": "do_buf[28]", + "iwire": "di_buf[28]", + "twire": "t[28]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y131", + "site": "IOB_X0Y125", + "ilogic_loc": "ILOGIC_X0Y125", + "ologic_loc": "OLOGIC_X0Y125", + "idelay_loc": "IDELAY_X0Y125", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[29]", + "owire": "do_buf[29]", + "iwire": "di_buf[29]", + "twire": "t[29]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y131", + "site": "IOB_X0Y126", + "ilogic_loc": "ILOGIC_X0Y126", + "ologic_loc": "OLOGIC_X0Y126", + "idelay_loc": "IDELAY_X0Y126", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[30]", + "owire": "do_buf[30]", + "iwire": "di_buf[30]", + "twire": "t[30]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y126),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y126),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y133", + "site": "IOB_X0Y127", + "ilogic_loc": "ILOGIC_X0Y127", + "ologic_loc": "OLOGIC_X0Y127", + "idelay_loc": "IDELAY_X0Y127", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[31]", + "owire": "do_buf[31]", + "iwire": "di_buf[31]", + "twire": "t[31]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "LIOB18_X81Y133", + "site": "IOB_X0Y128", + "ilogic_loc": "ILOGIC_X0Y128", + "ologic_loc": "OLOGIC_X0Y128", + "idelay_loc": "IDELAY_X0Y128", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[32]", + "owire": "do_buf[32]", + "iwire": "di_buf[32]", + "twire": "t[32]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y128),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y128),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y135", + "site": "IOB_X0Y129", + "ilogic_loc": "ILOGIC_X0Y129", + "ologic_loc": "OLOGIC_X0Y129", + "idelay_loc": "IDELAY_X0Y129", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[33]", + "owire": "do_buf[33]", + "iwire": "di_buf[33]", + "twire": "t[33]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y135", + "site": "IOB_X0Y130", + "ilogic_loc": "ILOGIC_X0Y130", + "ologic_loc": "OLOGIC_X0Y130", + "idelay_loc": "IDELAY_X0Y130", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[34]", + "owire": "do_buf[34]", + "iwire": "di_buf[34]", + "twire": "t[34]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y130),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y130),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y137", + "site": "IOB_X0Y131", + "ilogic_loc": "ILOGIC_X0Y131", + "ologic_loc": "OLOGIC_X0Y131", + "idelay_loc": "IDELAY_X0Y131", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[35]", + "owire": "do_buf[35]", + "iwire": "di_buf[35]", + "twire": "t[35]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y131),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y137", + "site": "IOB_X0Y132", + "ilogic_loc": "ILOGIC_X0Y132", + "ologic_loc": "OLOGIC_X0Y132", + "idelay_loc": "IDELAY_X0Y132", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[36]", + "owire": "do_buf[36]", + "iwire": "di_buf[36]", + "twire": "t[36]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y132),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y139", + "site": "IOB_X0Y133", + "ilogic_loc": "ILOGIC_X0Y133", + "ologic_loc": "OLOGIC_X0Y133", + "idelay_loc": "IDELAY_X0Y133", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[37]", + "owire": "do_buf[37]", + "iwire": "di_buf[37]", + "twire": "t[37]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y139", + "site": "IOB_X0Y134", + "ilogic_loc": "ILOGIC_X0Y134", + "ologic_loc": "OLOGIC_X0Y134", + "idelay_loc": "IDELAY_X0Y134", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[38]", + "owire": "do_buf[38]", + "iwire": "di_buf[38]", + "twire": "t[38]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y134),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y134),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y14", + "site": "IOB_X0Y13", + "ilogic_loc": "ILOGIC_X0Y13", + "ologic_loc": "OLOGIC_X0Y13", + "idelay_loc": "IDELAY_X0Y13", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[39]", + "owire": "do_buf[39]", + "iwire": "di_buf[39]", + "twire": "t[39]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 3, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y13),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y13),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y14", + "site": "IOB_X0Y14", + "ilogic_loc": "ILOGIC_X0Y14", + "ologic_loc": "OLOGIC_X0Y14", + "idelay_loc": "IDELAY_X0Y14", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[40]", + "owire": "do_buf[40]", + "iwire": "di_buf[40]", + "twire": "t[40]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y14),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y141", + "site": "IOB_X0Y135", + "ilogic_loc": "ILOGIC_X0Y135", + "ologic_loc": "OLOGIC_X0Y135", + "idelay_loc": "IDELAY_X0Y135", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[41]", + "owire": "do_buf[41]", + "iwire": "di_buf[41]", + "twire": "t[41]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y141", + "site": "IOB_X0Y136", + "ilogic_loc": "ILOGIC_X0Y136", + "ologic_loc": "OLOGIC_X0Y136", + "idelay_loc": "IDELAY_X0Y136", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[42]", + "owire": "do_buf[42]", + "iwire": "di_buf[42]", + "twire": "t[42]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y136),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y143", + "site": "IOB_X0Y137", + "ilogic_loc": "ILOGIC_X0Y137", + "ologic_loc": "OLOGIC_X0Y137", + "idelay_loc": "IDELAY_X0Y137", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[43]", + "owire": "do_buf[43]", + "iwire": "di_buf[43]", + "twire": "t[43]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y143", + "site": "IOB_X0Y138", + "ilogic_loc": "ILOGIC_X0Y138", + "ologic_loc": "OLOGIC_X0Y138", + "idelay_loc": "IDELAY_X0Y138", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[44]", + "owire": "do_buf[44]", + "iwire": "di_buf[44]", + "twire": "t[44]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y145", + "site": "IOB_X0Y139", + "ilogic_loc": "ILOGIC_X0Y139", + "ologic_loc": "OLOGIC_X0Y139", + "idelay_loc": "IDELAY_X0Y139", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[45]", + "owire": "do_buf[45]", + "iwire": "di_buf[45]", + "twire": "t[45]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y145", + "site": "IOB_X0Y140", + "ilogic_loc": "ILOGIC_X0Y140", + "ologic_loc": "OLOGIC_X0Y140", + "idelay_loc": "IDELAY_X0Y140", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[46]", + "owire": "do_buf[46]", + "iwire": "di_buf[46]", + "twire": "t[46]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y147", + "site": "IOB_X0Y141", + "ilogic_loc": "ILOGIC_X0Y141", + "ologic_loc": "OLOGIC_X0Y141", + "idelay_loc": "IDELAY_X0Y141", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[47]", + "owire": "do_buf[47]", + "iwire": "di_buf[47]", + "twire": "t[47]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y147", + "site": "IOB_X0Y142", + "ilogic_loc": "ILOGIC_X0Y142", + "ologic_loc": "OLOGIC_X0Y142", + "idelay_loc": "IDELAY_X0Y142", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[48]", + "owire": "do_buf[48]", + "iwire": "di_buf[48]", + "twire": "t[48]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y142),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y149", + "site": "IOB_X0Y143", + "ilogic_loc": "ILOGIC_X0Y143", + "ologic_loc": "OLOGIC_X0Y143", + "idelay_loc": "IDELAY_X0Y143", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[49]", + "owire": "do_buf[49]", + "iwire": "di_buf[49]", + "twire": "t[49]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 2, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y143),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y149", + "site": "IOB_X0Y144", + "ilogic_loc": "ILOGIC_X0Y144", + "ologic_loc": "OLOGIC_X0Y144", + "idelay_loc": "IDELAY_X0Y144", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[50]", + "owire": "do_buf[50]", + "iwire": "di_buf[50]", + "twire": "t[50]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 5, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y144),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y144),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y151", + "site": "IOB_X0Y145", + "ilogic_loc": "ILOGIC_X0Y145", + "ologic_loc": "OLOGIC_X0Y145", + "idelay_loc": "IDELAY_X0Y145", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[51]", + "owire": "do_buf[51]", + "iwire": "di_buf[51]", + "twire": "t[51]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y151", + "site": "IOB_X0Y146", + "ilogic_loc": "ILOGIC_X0Y146", + "ologic_loc": "OLOGIC_X0Y146", + "idelay_loc": "IDELAY_X0Y146", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[52]", + "owire": "do_buf[52]", + "iwire": "di_buf[52]", + "twire": "t[52]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y153", + "site": "IOB_X0Y147", + "ilogic_loc": "ILOGIC_X0Y147", + "ologic_loc": "OLOGIC_X0Y147", + "idelay_loc": "IDELAY_X0Y147", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[53]", + "owire": "do_buf[53]", + "iwire": "di_buf[53]", + "twire": "t[53]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y147),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y153", + "site": "IOB_X0Y148", + "ilogic_loc": "ILOGIC_X0Y148", + "ologic_loc": "OLOGIC_X0Y148", + "idelay_loc": "IDELAY_X0Y148", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[54]", + "owire": "do_buf[54]", + "iwire": "di_buf[54]", + "twire": "t[54]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y148),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y148),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y158", + "site": "IOB_X0Y151", + "ilogic_loc": "ILOGIC_X0Y151", + "ologic_loc": "OLOGIC_X0Y151", + "idelay_loc": "IDELAY_X0Y151", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[55]", + "owire": "do_buf[55]", + "iwire": "di_buf[55]", + "twire": "t[55]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y151),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y158", + "site": "IOB_X0Y152", + "ilogic_loc": "ILOGIC_X0Y152", + "ologic_loc": "OLOGIC_X0Y152", + "idelay_loc": "IDELAY_X0Y152", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[56]", + "owire": "do_buf[56]", + "iwire": "di_buf[56]", + "twire": "t[56]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y152),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y16", + "site": "IOB_X0Y15", + "ilogic_loc": "ILOGIC_X0Y15", + "ologic_loc": "OLOGIC_X0Y15", + "idelay_loc": "IDELAY_X0Y15", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[57]", + "owire": "do_buf[57]", + "iwire": "di_buf[57]", + "twire": "t[57]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y16", + "site": "IOB_X0Y16", + "ilogic_loc": "ILOGIC_X0Y16", + "ologic_loc": "OLOGIC_X0Y16", + "idelay_loc": "IDELAY_X0Y16", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[58]", + "owire": "do_buf[58]", + "iwire": "di_buf[58]", + "twire": "t[58]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 3, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y16),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y16),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y160", + "site": "IOB_X0Y153", + "ilogic_loc": "ILOGIC_X0Y153", + "ologic_loc": "OLOGIC_X0Y153", + "idelay_loc": "IDELAY_X0Y153", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[59]", + "owire": "do_buf[59]", + "iwire": "di_buf[59]", + "twire": "t[59]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y153),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y160", + "site": "IOB_X0Y154", + "ilogic_loc": "ILOGIC_X0Y154", + "ologic_loc": "OLOGIC_X0Y154", + "idelay_loc": "IDELAY_X0Y154", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[60]", + "owire": "do_buf[60]", + "iwire": "di_buf[60]", + "twire": "t[60]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y162", + "site": "IOB_X0Y155", + "ilogic_loc": "ILOGIC_X0Y155", + "ologic_loc": "OLOGIC_X0Y155", + "idelay_loc": "IDELAY_X0Y155", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[61]", + "owire": "do_buf[61]", + "iwire": "di_buf[61]", + "twire": "t[61]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y155),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 5, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y155),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y162", + "site": "IOB_X0Y156", + "ilogic_loc": "ILOGIC_X0Y156", + "ologic_loc": "OLOGIC_X0Y156", + "idelay_loc": "IDELAY_X0Y156", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[62]", + "owire": "do_buf[62]", + "iwire": "di_buf[62]", + "twire": "t[62]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y164", + "site": "IOB_X0Y157", + "ilogic_loc": "ILOGIC_X0Y157", + "ologic_loc": "OLOGIC_X0Y157", + "idelay_loc": "IDELAY_X0Y157", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[63]", + "owire": "do_buf[63]", + "iwire": "di_buf[63]", + "twire": "t[63]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 7, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y157),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y164", + "site": "IOB_X0Y158", + "ilogic_loc": "ILOGIC_X0Y158", + "ologic_loc": "OLOGIC_X0Y158", + "idelay_loc": "IDELAY_X0Y158", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[64]", + "owire": "do_buf[64]", + "iwire": "di_buf[64]", + "twire": "t[64]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y166", + "site": "IOB_X0Y159", + "ilogic_loc": "ILOGIC_X0Y159", + "ologic_loc": "OLOGIC_X0Y159", + "idelay_loc": "IDELAY_X0Y159", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[65]", + "owire": "do_buf[65]", + "iwire": "di_buf[65]", + "twire": "t[65]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 3, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y159),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y159),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y166", + "site": "IOB_X0Y160", + "ilogic_loc": "ILOGIC_X0Y160", + "ologic_loc": "OLOGIC_X0Y160", + "idelay_loc": "IDELAY_X0Y160", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[66]", + "owire": "do_buf[66]", + "iwire": "di_buf[66]", + "twire": "t[66]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y160),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y168", + "site": "IOB_X0Y161", + "ilogic_loc": "ILOGIC_X0Y161", + "ologic_loc": "OLOGIC_X0Y161", + "idelay_loc": "IDELAY_X0Y161", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[67]", + "owire": "do_buf[67]", + "iwire": "di_buf[67]", + "twire": "t[67]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 2, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y161),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y168", + "site": "IOB_X0Y162", + "ilogic_loc": "ILOGIC_X0Y162", + "ologic_loc": "OLOGIC_X0Y162", + "idelay_loc": "IDELAY_X0Y162", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[68]", + "owire": "do_buf[68]", + "iwire": "di_buf[68]", + "twire": "t[68]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y162),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y170", + "site": "IOB_X0Y163", + "ilogic_loc": "ILOGIC_X0Y163", + "ologic_loc": "OLOGIC_X0Y163", + "idelay_loc": "IDELAY_X0Y163", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[69]", + "owire": "do_buf[69]", + "iwire": "di_buf[69]", + "twire": "t[69]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y163),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y170", + "site": "IOB_X0Y164", + "ilogic_loc": "ILOGIC_X0Y164", + "ologic_loc": "OLOGIC_X0Y164", + "idelay_loc": "IDELAY_X0Y164", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[70]", + "owire": "do_buf[70]", + "iwire": "di_buf[70]", + "twire": "t[70]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y172", + "site": "IOB_X0Y165", + "ilogic_loc": "ILOGIC_X0Y165", + "ologic_loc": "OLOGIC_X0Y165", + "idelay_loc": "IDELAY_X0Y165", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[71]", + "owire": "do_buf[71]", + "iwire": "di_buf[71]", + "twire": "t[71]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y172", + "site": "IOB_X0Y166", + "ilogic_loc": "ILOGIC_X0Y166", + "ologic_loc": "OLOGIC_X0Y166", + "idelay_loc": "IDELAY_X0Y166", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[72]", + "owire": "do_buf[72]", + "iwire": "di_buf[72]", + "twire": "t[72]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y166),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y166),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y174", + "site": "IOB_X0Y167", + "ilogic_loc": "ILOGIC_X0Y167", + "ologic_loc": "OLOGIC_X0Y167", + "idelay_loc": "IDELAY_X0Y167", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[73]", + "owire": "do_buf[73]", + "iwire": "di_buf[73]", + "twire": "t[73]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y174", + "site": "IOB_X0Y168", + "ilogic_loc": "ILOGIC_X0Y168", + "ologic_loc": "OLOGIC_X0Y168", + "idelay_loc": "IDELAY_X0Y168", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[74]", + "owire": "do_buf[74]", + "iwire": "di_buf[74]", + "twire": "t[74]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y168),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y176", + "site": "IOB_X0Y169", + "ilogic_loc": "ILOGIC_X0Y169", + "ologic_loc": "OLOGIC_X0Y169", + "idelay_loc": "IDELAY_X0Y169", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[75]", + "owire": "do_buf[75]", + "iwire": "di_buf[75]", + "twire": "t[75]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y176", + "site": "IOB_X0Y170", + "ilogic_loc": "ILOGIC_X0Y170", + "ologic_loc": "OLOGIC_X0Y170", + "idelay_loc": "IDELAY_X0Y170", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[76]", + "owire": "do_buf[76]", + "iwire": "di_buf[76]", + "twire": "t[76]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y178", + "site": "IOB_X0Y171", + "ilogic_loc": "ILOGIC_X0Y171", + "ologic_loc": "OLOGIC_X0Y171", + "idelay_loc": "IDELAY_X0Y171", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[77]", + "owire": "do_buf[77]", + "iwire": "di_buf[77]", + "twire": "t[77]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 2, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y171),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y178", + "site": "IOB_X0Y172", + "ilogic_loc": "ILOGIC_X0Y172", + "ologic_loc": "OLOGIC_X0Y172", + "idelay_loc": "IDELAY_X0Y172", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[78]", + "owire": "do_buf[78]", + "iwire": "di_buf[78]", + "twire": "t[78]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y18", + "site": "IOB_X0Y17", + "ilogic_loc": "ILOGIC_X0Y17", + "ologic_loc": "OLOGIC_X0Y17", + "idelay_loc": "IDELAY_X0Y17", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[79]", + "owire": "do_buf[79]", + "iwire": "di_buf[79]", + "twire": "t[79]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y18", + "site": "IOB_X0Y18", + "ilogic_loc": "ILOGIC_X0Y18", + "ologic_loc": "OLOGIC_X0Y18", + "idelay_loc": "IDELAY_X0Y18", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[80]", + "owire": "do_buf[80]", + "iwire": "di_buf[80]", + "twire": "t[80]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y18),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y18),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y180", + "site": "IOB_X0Y173", + "ilogic_loc": "ILOGIC_X0Y173", + "ologic_loc": "OLOGIC_X0Y173", + "idelay_loc": "IDELAY_X0Y173", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[81]", + "owire": "do_buf[81]", + "iwire": "di_buf[81]", + "twire": "t[81]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y180", + "site": "IOB_X0Y174", + "ilogic_loc": "ILOGIC_X0Y174", + "ologic_loc": "OLOGIC_X0Y174", + "idelay_loc": "IDELAY_X0Y174", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[82]", + "owire": "do_buf[82]", + "iwire": "di_buf[82]", + "twire": "t[82]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "LIOB18_X81Y183", + "site": "IOB_X0Y175", + "ilogic_loc": "ILOGIC_X0Y175", + "ologic_loc": "OLOGIC_X0Y175", + "idelay_loc": "IDELAY_X0Y175", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[83]", + "owire": "do_buf[83]", + "iwire": "di_buf[83]", + "twire": "t[83]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y175),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y183", + "site": "IOB_X0Y176", + "ilogic_loc": "ILOGIC_X0Y176", + "ologic_loc": "OLOGIC_X0Y176", + "idelay_loc": "IDELAY_X0Y176", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[84]", + "owire": "do_buf[84]", + "iwire": "di_buf[84]", + "twire": "t[84]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y185", + "site": "IOB_X0Y177", + "ilogic_loc": "ILOGIC_X0Y177", + "ologic_loc": "OLOGIC_X0Y177", + "idelay_loc": "IDELAY_X0Y177", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[85]", + "owire": "do_buf[85]", + "iwire": "di_buf[85]", + "twire": "t[85]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y185", + "site": "IOB_X0Y178", + "ilogic_loc": "ILOGIC_X0Y178", + "ologic_loc": "OLOGIC_X0Y178", + "idelay_loc": "IDELAY_X0Y178", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[86]", + "owire": "do_buf[86]", + "iwire": "di_buf[86]", + "twire": "t[86]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "LIOB18_X81Y187", + "site": "IOB_X0Y179", + "ilogic_loc": "ILOGIC_X0Y179", + "ologic_loc": "OLOGIC_X0Y179", + "idelay_loc": "IDELAY_X0Y179", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[87]", + "owire": "do_buf[87]", + "iwire": "di_buf[87]", + "twire": "t[87]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y179),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y179),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y187", + "site": "IOB_X0Y180", + "ilogic_loc": "ILOGIC_X0Y180", + "ologic_loc": "OLOGIC_X0Y180", + "idelay_loc": "IDELAY_X0Y180", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[88]", + "owire": "do_buf[88]", + "iwire": "di_buf[88]", + "twire": "t[88]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 3, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y180),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y189", + "site": "IOB_X0Y181", + "ilogic_loc": "ILOGIC_X0Y181", + "ologic_loc": "OLOGIC_X0Y181", + "idelay_loc": "IDELAY_X0Y181", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[89]", + "owire": "do_buf[89]", + "iwire": "di_buf[89]", + "twire": "t[89]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y181),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y189", + "site": "IOB_X0Y182", + "ilogic_loc": "ILOGIC_X0Y182", + "ologic_loc": "OLOGIC_X0Y182", + "idelay_loc": "IDELAY_X0Y182", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[90]", + "owire": "do_buf[90]", + "iwire": "di_buf[90]", + "twire": "t[90]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y191", + "site": "IOB_X0Y183", + "ilogic_loc": "ILOGIC_X0Y183", + "ologic_loc": "OLOGIC_X0Y183", + "idelay_loc": "IDELAY_X0Y183", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[91]", + "owire": "do_buf[91]", + "iwire": "di_buf[91]", + "twire": "t[91]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y191", + "site": "IOB_X0Y184", + "ilogic_loc": "ILOGIC_X0Y184", + "ologic_loc": "OLOGIC_X0Y184", + "idelay_loc": "IDELAY_X0Y184", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[92]", + "owire": "do_buf[92]", + "iwire": "di_buf[92]", + "twire": "t[92]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y193", + "site": "IOB_X0Y185", + "ilogic_loc": "ILOGIC_X0Y185", + "ologic_loc": "OLOGIC_X0Y185", + "idelay_loc": "IDELAY_X0Y185", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[93]", + "owire": "do_buf[93]", + "iwire": "di_buf[93]", + "twire": "t[93]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y185),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y193", + "site": "IOB_X0Y186", + "ilogic_loc": "ILOGIC_X0Y186", + "ologic_loc": "OLOGIC_X0Y186", + "idelay_loc": "IDELAY_X0Y186", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[94]", + "owire": "do_buf[94]", + "iwire": "di_buf[94]", + "twire": "t[94]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y195", + "site": "IOB_X0Y187", + "ilogic_loc": "ILOGIC_X0Y187", + "ologic_loc": "OLOGIC_X0Y187", + "idelay_loc": "IDELAY_X0Y187", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[95]", + "owire": "do_buf[95]", + "iwire": "di_buf[95]", + "twire": "t[95]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y195", + "site": "IOB_X0Y188", + "ilogic_loc": "ILOGIC_X0Y188", + "ologic_loc": "OLOGIC_X0Y188", + "idelay_loc": "IDELAY_X0Y188", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[96]", + "owire": "do_buf[96]", + "iwire": "di_buf[96]", + "twire": "t[96]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y197", + "site": "IOB_X0Y189", + "ilogic_loc": "ILOGIC_X0Y189", + "ologic_loc": "OLOGIC_X0Y189", + "idelay_loc": "IDELAY_X0Y189", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[97]", + "owire": "do_buf[97]", + "iwire": "di_buf[97]", + "twire": "t[97]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 3, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 5, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y189),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y197", + "site": "IOB_X0Y190", + "ilogic_loc": "ILOGIC_X0Y190", + "ologic_loc": "OLOGIC_X0Y190", + "idelay_loc": "IDELAY_X0Y190", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[98]", + "owire": "do_buf[98]", + "iwire": "di_buf[98]", + "twire": "t[98]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 2, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y190),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y199", + "site": "IOB_X0Y191", + "ilogic_loc": "ILOGIC_X0Y191", + "ologic_loc": "OLOGIC_X0Y191", + "idelay_loc": "IDELAY_X0Y191", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[99]", + "owire": "do_buf[99]", + "iwire": "di_buf[99]", + "twire": "t[99]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y199", + "site": "IOB_X0Y192", + "ilogic_loc": "ILOGIC_X0Y192", + "ologic_loc": "OLOGIC_X0Y192", + "idelay_loc": "IDELAY_X0Y192", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[100]", + "owire": "do_buf[100]", + "iwire": "di_buf[100]", + "twire": "t[100]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y192),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y2", + "site": "IOB_X0Y1", + "ilogic_loc": "ILOGIC_X0Y1", + "ologic_loc": "OLOGIC_X0Y1", + "idelay_loc": "IDELAY_X0Y1", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[101]", + "owire": "do_buf[101]", + "iwire": "di_buf[101]", + "twire": "t[101]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y2", + "site": "IOB_X0Y2", + "ilogic_loc": "ILOGIC_X0Y2", + "ologic_loc": "OLOGIC_X0Y2", + "idelay_loc": "IDELAY_X0Y2", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[102]", + "owire": "do_buf[102]", + "iwire": "di_buf[102]", + "twire": "t[102]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y20", + "site": "IOB_X0Y19", + "ilogic_loc": "ILOGIC_X0Y19", + "ologic_loc": "OLOGIC_X0Y19", + "idelay_loc": "IDELAY_X0Y19", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[103]", + "owire": "do_buf[103]", + "iwire": "di_buf[103]", + "twire": "t[103]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y20", + "site": "IOB_X0Y20", + "ilogic_loc": "ILOGIC_X0Y20", + "ologic_loc": "OLOGIC_X0Y20", + "idelay_loc": "IDELAY_X0Y20", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[104]", + "owire": "do_buf[104]", + "iwire": "di_buf[104]", + "twire": "t[104]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y20),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y201", + "site": "IOB_X0Y193", + "ilogic_loc": "ILOGIC_X0Y193", + "ologic_loc": "OLOGIC_X0Y193", + "idelay_loc": "IDELAY_X0Y193", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[105]", + "owire": "do_buf[105]", + "iwire": "di_buf[105]", + "twire": "t[105]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 5, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y193),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y201", + "site": "IOB_X0Y194", + "ilogic_loc": "ILOGIC_X0Y194", + "ologic_loc": "OLOGIC_X0Y194", + "idelay_loc": "IDELAY_X0Y194", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[106]", + "owire": "do_buf[106]", + "iwire": "di_buf[106]", + "twire": "t[106]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y203", + "site": "IOB_X0Y195", + "ilogic_loc": "ILOGIC_X0Y195", + "ologic_loc": "OLOGIC_X0Y195", + "idelay_loc": "IDELAY_X0Y195", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[107]", + "owire": "do_buf[107]", + "iwire": "di_buf[107]", + "twire": "t[107]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y203", + "site": "IOB_X0Y196", + "ilogic_loc": "ILOGIC_X0Y196", + "ologic_loc": "OLOGIC_X0Y196", + "idelay_loc": "IDELAY_X0Y196", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[108]", + "owire": "do_buf[108]", + "iwire": "di_buf[108]", + "twire": "t[108]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y205", + "site": "IOB_X0Y197", + "ilogic_loc": "ILOGIC_X0Y197", + "ologic_loc": "OLOGIC_X0Y197", + "idelay_loc": "IDELAY_X0Y197", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[109]", + "owire": "do_buf[109]", + "iwire": "di_buf[109]", + "twire": "t[109]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 3, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y197),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y197),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y205", + "site": "IOB_X0Y198", + "ilogic_loc": "ILOGIC_X0Y198", + "ologic_loc": "OLOGIC_X0Y198", + "idelay_loc": "IDELAY_X0Y198", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[110]", + "owire": "do_buf[110]", + "iwire": "di_buf[110]", + "twire": "t[110]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 5, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y198),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y210", + "site": "IOB_X0Y201", + "ilogic_loc": "ILOGIC_X0Y201", + "ologic_loc": "OLOGIC_X0Y201", + "idelay_loc": "IDELAY_X0Y201", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[111]", + "owire": "do_buf[111]", + "iwire": "di_buf[111]", + "twire": "t[111]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 3, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y201),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y201),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y210", + "site": "IOB_X0Y202", + "ilogic_loc": "ILOGIC_X0Y202", + "ologic_loc": "OLOGIC_X0Y202", + "idelay_loc": "IDELAY_X0Y202", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[112]", + "owire": "do_buf[112]", + "iwire": "di_buf[112]", + "twire": "t[112]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y212", + "site": "IOB_X0Y203", + "ilogic_loc": "ILOGIC_X0Y203", + "ologic_loc": "OLOGIC_X0Y203", + "idelay_loc": "IDELAY_X0Y203", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[113]", + "owire": "do_buf[113]", + "iwire": "di_buf[113]", + "twire": "t[113]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y212", + "site": "IOB_X0Y204", + "ilogic_loc": "ILOGIC_X0Y204", + "ologic_loc": "OLOGIC_X0Y204", + "idelay_loc": "IDELAY_X0Y204", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[114]", + "owire": "do_buf[114]", + "iwire": "di_buf[114]", + "twire": "t[114]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y214", + "site": "IOB_X0Y205", + "ilogic_loc": "ILOGIC_X0Y205", + "ologic_loc": "OLOGIC_X0Y205", + "idelay_loc": "IDELAY_X0Y205", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[115]", + "owire": "do_buf[115]", + "iwire": "di_buf[115]", + "twire": "t[115]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y214", + "site": "IOB_X0Y206", + "ilogic_loc": "ILOGIC_X0Y206", + "ologic_loc": "OLOGIC_X0Y206", + "idelay_loc": "IDELAY_X0Y206", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[116]", + "owire": "do_buf[116]", + "iwire": "di_buf[116]", + "twire": "t[116]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y216", + "site": "IOB_X0Y207", + "ilogic_loc": "ILOGIC_X0Y207", + "ologic_loc": "OLOGIC_X0Y207", + "idelay_loc": "IDELAY_X0Y207", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[117]", + "owire": "do_buf[117]", + "iwire": "di_buf[117]", + "twire": "t[117]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 5, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y207),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y216", + "site": "IOB_X0Y208", + "ilogic_loc": "ILOGIC_X0Y208", + "ologic_loc": "OLOGIC_X0Y208", + "idelay_loc": "IDELAY_X0Y208", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[118]", + "owire": "do_buf[118]", + "iwire": "di_buf[118]", + "twire": "t[118]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y208),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y208),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y218", + "site": "IOB_X0Y209", + "ilogic_loc": "ILOGIC_X0Y209", + "ologic_loc": "OLOGIC_X0Y209", + "idelay_loc": "IDELAY_X0Y209", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[119]", + "owire": "do_buf[119]", + "iwire": "di_buf[119]", + "twire": "t[119]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y218", + "site": "IOB_X0Y210", + "ilogic_loc": "ILOGIC_X0Y210", + "ologic_loc": "OLOGIC_X0Y210", + "idelay_loc": "IDELAY_X0Y210", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[120]", + "owire": "do_buf[120]", + "iwire": "di_buf[120]", + "twire": "t[120]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "LIOB18_X81Y22", + "site": "IOB_X0Y21", + "ilogic_loc": "ILOGIC_X0Y21", + "ologic_loc": "OLOGIC_X0Y21", + "idelay_loc": "IDELAY_X0Y21", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[121]", + "owire": "do_buf[121]", + "iwire": "di_buf[121]", + "twire": "t[121]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y22", + "site": "IOB_X0Y22", + "ilogic_loc": "ILOGIC_X0Y22", + "ologic_loc": "OLOGIC_X0Y22", + "idelay_loc": "IDELAY_X0Y22", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[122]", + "owire": "do_buf[122]", + "iwire": "di_buf[122]", + "twire": "t[122]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y220", + "site": "IOB_X0Y211", + "ilogic_loc": "ILOGIC_X0Y211", + "ologic_loc": "OLOGIC_X0Y211", + "idelay_loc": "IDELAY_X0Y211", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[123]", + "owire": "do_buf[123]", + "iwire": "di_buf[123]", + "twire": "t[123]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y220", + "site": "IOB_X0Y212", + "ilogic_loc": "ILOGIC_X0Y212", + "ologic_loc": "OLOGIC_X0Y212", + "idelay_loc": "IDELAY_X0Y212", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[124]", + "owire": "do_buf[124]", + "iwire": "di_buf[124]", + "twire": "t[124]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 7, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y212),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y222", + "site": "IOB_X0Y213", + "ilogic_loc": "ILOGIC_X0Y213", + "ologic_loc": "OLOGIC_X0Y213", + "idelay_loc": "IDELAY_X0Y213", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[125]", + "owire": "do_buf[125]", + "iwire": "di_buf[125]", + "twire": "t[125]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y222", + "site": "IOB_X0Y214", + "ilogic_loc": "ILOGIC_X0Y214", + "ologic_loc": "OLOGIC_X0Y214", + "idelay_loc": "IDELAY_X0Y214", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[126]", + "owire": "do_buf[126]", + "iwire": "di_buf[126]", + "twire": "t[126]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y224", + "site": "IOB_X0Y215", + "ilogic_loc": "ILOGIC_X0Y215", + "ologic_loc": "OLOGIC_X0Y215", + "idelay_loc": "IDELAY_X0Y215", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[127]", + "owire": "do_buf[127]", + "iwire": "di_buf[127]", + "twire": "t[127]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y224", + "site": "IOB_X0Y216", + "ilogic_loc": "ILOGIC_X0Y216", + "ologic_loc": "OLOGIC_X0Y216", + "idelay_loc": "IDELAY_X0Y216", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[128]", + "owire": "do_buf[128]", + "iwire": "di_buf[128]", + "twire": "t[128]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y216),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y226", + "site": "IOB_X0Y217", + "ilogic_loc": "ILOGIC_X0Y217", + "ologic_loc": "OLOGIC_X0Y217", + "idelay_loc": "IDELAY_X0Y217", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[129]", + "owire": "do_buf[129]", + "iwire": "di_buf[129]", + "twire": "t[129]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y226", + "site": "IOB_X0Y218", + "ilogic_loc": "ILOGIC_X0Y218", + "ologic_loc": "OLOGIC_X0Y218", + "idelay_loc": "IDELAY_X0Y218", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[130]", + "owire": "do_buf[130]", + "iwire": "di_buf[130]", + "twire": "t[130]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y218),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y218),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y228", + "site": "IOB_X0Y219", + "ilogic_loc": "ILOGIC_X0Y219", + "ologic_loc": "OLOGIC_X0Y219", + "idelay_loc": "IDELAY_X0Y219", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[131]", + "owire": "do_buf[131]", + "iwire": "di_buf[131]", + "twire": "t[131]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 3, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y219),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 3, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y219),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y228", + "site": "IOB_X0Y220", + "ilogic_loc": "ILOGIC_X0Y220", + "ologic_loc": "OLOGIC_X0Y220", + "idelay_loc": "IDELAY_X0Y220", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[132]", + "owire": "do_buf[132]", + "iwire": "di_buf[132]", + "twire": "t[132]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y230", + "site": "IOB_X0Y221", + "ilogic_loc": "ILOGIC_X0Y221", + "ologic_loc": "OLOGIC_X0Y221", + "idelay_loc": "IDELAY_X0Y221", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[133]", + "owire": "do_buf[133]", + "iwire": "di_buf[133]", + "twire": "t[133]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "LIOB18_X81Y230", + "site": "IOB_X0Y222", + "ilogic_loc": "ILOGIC_X0Y222", + "ologic_loc": "OLOGIC_X0Y222", + "idelay_loc": "IDELAY_X0Y222", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[134]", + "owire": "do_buf[134]", + "iwire": "di_buf[134]", + "twire": "t[134]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 2, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y232", + "site": "IOB_X0Y223", + "ilogic_loc": "ILOGIC_X0Y223", + "ologic_loc": "OLOGIC_X0Y223", + "idelay_loc": "IDELAY_X0Y223", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[135]", + "owire": "do_buf[135]", + "iwire": "di_buf[135]", + "twire": "t[135]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y232", + "site": "IOB_X0Y224", + "ilogic_loc": "ILOGIC_X0Y224", + "ologic_loc": "OLOGIC_X0Y224", + "idelay_loc": "IDELAY_X0Y224", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[136]", + "owire": "do_buf[136]", + "iwire": "di_buf[136]", + "twire": "t[136]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y235", + "site": "IOB_X0Y225", + "ilogic_loc": "ILOGIC_X0Y225", + "ologic_loc": "OLOGIC_X0Y225", + "idelay_loc": "IDELAY_X0Y225", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[137]", + "owire": "do_buf[137]", + "iwire": "di_buf[137]", + "twire": "t[137]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y235", + "site": "IOB_X0Y226", + "ilogic_loc": "ILOGIC_X0Y226", + "ologic_loc": "OLOGIC_X0Y226", + "idelay_loc": "IDELAY_X0Y226", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[138]", + "owire": "do_buf[138]", + "iwire": "di_buf[138]", + "twire": "t[138]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y226),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y237", + "site": "IOB_X0Y227", + "ilogic_loc": "ILOGIC_X0Y227", + "ologic_loc": "OLOGIC_X0Y227", + "idelay_loc": "IDELAY_X0Y227", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[139]", + "owire": "do_buf[139]", + "iwire": "di_buf[139]", + "twire": "t[139]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y237", + "site": "IOB_X0Y228", + "ilogic_loc": "ILOGIC_X0Y228", + "ologic_loc": "OLOGIC_X0Y228", + "idelay_loc": "IDELAY_X0Y228", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[140]", + "owire": "do_buf[140]", + "iwire": "di_buf[140]", + "twire": "t[140]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y239", + "site": "IOB_X0Y229", + "ilogic_loc": "ILOGIC_X0Y229", + "ologic_loc": "OLOGIC_X0Y229", + "idelay_loc": "IDELAY_X0Y229", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[141]", + "owire": "do_buf[141]", + "iwire": "di_buf[141]", + "twire": "t[141]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y239", + "site": "IOB_X0Y230", + "ilogic_loc": "ILOGIC_X0Y230", + "ologic_loc": "OLOGIC_X0Y230", + "idelay_loc": "IDELAY_X0Y230", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[142]", + "owire": "do_buf[142]", + "iwire": "di_buf[142]", + "twire": "t[142]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y24", + "site": "IOB_X0Y23", + "ilogic_loc": "ILOGIC_X0Y23", + "ologic_loc": "OLOGIC_X0Y23", + "idelay_loc": "IDELAY_X0Y23", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[143]", + "owire": "do_buf[143]", + "iwire": "di_buf[143]", + "twire": "t[143]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 5, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y23),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y24", + "site": "IOB_X0Y24", + "ilogic_loc": "ILOGIC_X0Y24", + "ologic_loc": "OLOGIC_X0Y24", + "idelay_loc": "IDELAY_X0Y24", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[144]", + "owire": "do_buf[144]", + "iwire": "di_buf[144]", + "twire": "t[144]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y24),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y24),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y241", + "site": "IOB_X0Y231", + "ilogic_loc": "ILOGIC_X0Y231", + "ologic_loc": "OLOGIC_X0Y231", + "idelay_loc": "IDELAY_X0Y231", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[145]", + "owire": "do_buf[145]", + "iwire": "di_buf[145]", + "twire": "t[145]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y231),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y241", + "site": "IOB_X0Y232", + "ilogic_loc": "ILOGIC_X0Y232", + "ologic_loc": "OLOGIC_X0Y232", + "idelay_loc": "IDELAY_X0Y232", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[146]", + "owire": "do_buf[146]", + "iwire": "di_buf[146]", + "twire": "t[146]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y243", + "site": "IOB_X0Y233", + "ilogic_loc": "ILOGIC_X0Y233", + "ologic_loc": "OLOGIC_X0Y233", + "idelay_loc": "IDELAY_X0Y233", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[147]", + "owire": "do_buf[147]", + "iwire": "di_buf[147]", + "twire": "t[147]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y243", + "site": "IOB_X0Y234", + "ilogic_loc": "ILOGIC_X0Y234", + "ologic_loc": "OLOGIC_X0Y234", + "idelay_loc": "IDELAY_X0Y234", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[148]", + "owire": "do_buf[148]", + "iwire": "di_buf[148]", + "twire": "t[148]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y245", + "site": "IOB_X0Y235", + "ilogic_loc": "ILOGIC_X0Y235", + "ologic_loc": "OLOGIC_X0Y235", + "idelay_loc": "IDELAY_X0Y235", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[149]", + "owire": "do_buf[149]", + "iwire": "di_buf[149]", + "twire": "t[149]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y245", + "site": "IOB_X0Y236", + "ilogic_loc": "ILOGIC_X0Y236", + "ologic_loc": "OLOGIC_X0Y236", + "idelay_loc": "IDELAY_X0Y236", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[150]", + "owire": "do_buf[150]", + "iwire": "di_buf[150]", + "twire": "t[150]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y236),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y247", + "site": "IOB_X0Y237", + "ilogic_loc": "ILOGIC_X0Y237", + "ologic_loc": "OLOGIC_X0Y237", + "idelay_loc": "IDELAY_X0Y237", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[151]", + "owire": "do_buf[151]", + "iwire": "di_buf[151]", + "twire": "t[151]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y247", + "site": "IOB_X0Y238", + "ilogic_loc": "ILOGIC_X0Y238", + "ologic_loc": "OLOGIC_X0Y238", + "idelay_loc": "IDELAY_X0Y238", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[152]", + "owire": "do_buf[152]", + "iwire": "di_buf[152]", + "twire": "t[152]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y238),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y249", + "site": "IOB_X0Y239", + "ilogic_loc": "ILOGIC_X0Y239", + "ologic_loc": "OLOGIC_X0Y239", + "idelay_loc": "IDELAY_X0Y239", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[153]", + "owire": "do_buf[153]", + "iwire": "di_buf[153]", + "twire": "t[153]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 2, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y239),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y249", + "site": "IOB_X0Y240", + "ilogic_loc": "ILOGIC_X0Y240", + "ologic_loc": "OLOGIC_X0Y240", + "idelay_loc": "IDELAY_X0Y240", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[154]", + "owire": "do_buf[154]", + "iwire": "di_buf[154]", + "twire": "t[154]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y251", + "site": "IOB_X0Y241", + "ilogic_loc": "ILOGIC_X0Y241", + "ologic_loc": "OLOGIC_X0Y241", + "idelay_loc": "IDELAY_X0Y241", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[155]", + "owire": "do_buf[155]", + "iwire": "di_buf[155]", + "twire": "t[155]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "LIOB18_X81Y251", + "site": "IOB_X0Y242", + "ilogic_loc": "ILOGIC_X0Y242", + "ologic_loc": "OLOGIC_X0Y242", + "idelay_loc": "IDELAY_X0Y242", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[156]", + "owire": "do_buf[156]", + "iwire": "di_buf[156]", + "twire": "t[156]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y253", + "site": "IOB_X0Y243", + "ilogic_loc": "ILOGIC_X0Y243", + "ologic_loc": "OLOGIC_X0Y243", + "idelay_loc": "IDELAY_X0Y243", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[157]", + "owire": "do_buf[157]", + "iwire": "di_buf[157]", + "twire": "t[157]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y253", + "site": "IOB_X0Y244", + "ilogic_loc": "ILOGIC_X0Y244", + "ologic_loc": "OLOGIC_X0Y244", + "idelay_loc": "IDELAY_X0Y244", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[158]", + "owire": "do_buf[158]", + "iwire": "di_buf[158]", + "twire": "t[158]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y244),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y255", + "site": "IOB_X0Y245", + "ilogic_loc": "ILOGIC_X0Y245", + "ologic_loc": "OLOGIC_X0Y245", + "idelay_loc": "IDELAY_X0Y245", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[159]", + "owire": "do_buf[159]", + "iwire": "di_buf[159]", + "twire": "t[159]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y255", + "site": "IOB_X0Y246", + "ilogic_loc": "ILOGIC_X0Y246", + "ologic_loc": "OLOGIC_X0Y246", + "idelay_loc": "IDELAY_X0Y246", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[160]", + "owire": "do_buf[160]", + "iwire": "di_buf[160]", + "twire": "t[160]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y257", + "site": "IOB_X0Y247", + "ilogic_loc": "ILOGIC_X0Y247", + "ologic_loc": "OLOGIC_X0Y247", + "idelay_loc": "IDELAY_X0Y247", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[161]", + "owire": "do_buf[161]", + "iwire": "di_buf[161]", + "twire": "t[161]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 5, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y247),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y247),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y257", + "site": "IOB_X0Y248", + "ilogic_loc": "ILOGIC_X0Y248", + "ologic_loc": "OLOGIC_X0Y248", + "idelay_loc": "IDELAY_X0Y248", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[162]", + "owire": "do_buf[162]", + "iwire": "di_buf[162]", + "twire": "t[162]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y248),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y248),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y262", + "site": "IOB_X0Y251", + "ilogic_loc": "ILOGIC_X0Y251", + "ologic_loc": "OLOGIC_X0Y251", + "idelay_loc": "IDELAY_X0Y251", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[163]", + "owire": "do_buf[163]", + "iwire": "di_buf[163]", + "twire": "t[163]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 7, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y251),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 7, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y251),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y262", + "site": "IOB_X0Y252", + "ilogic_loc": "ILOGIC_X0Y252", + "ologic_loc": "OLOGIC_X0Y252", + "idelay_loc": "IDELAY_X0Y252", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[164]", + "owire": "do_buf[164]", + "iwire": "di_buf[164]", + "twire": "t[164]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y252),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y264", + "site": "IOB_X0Y253", + "ilogic_loc": "ILOGIC_X0Y253", + "ologic_loc": "OLOGIC_X0Y253", + "idelay_loc": "IDELAY_X0Y253", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[165]", + "owire": "do_buf[165]", + "iwire": "di_buf[165]", + "twire": "t[165]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y253),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y253),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y264", + "site": "IOB_X0Y254", + "ilogic_loc": "ILOGIC_X0Y254", + "ologic_loc": "OLOGIC_X0Y254", + "idelay_loc": "IDELAY_X0Y254", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[166]", + "owire": "do_buf[166]", + "iwire": "di_buf[166]", + "twire": "t[166]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 2, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y254),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y254),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y266", + "site": "IOB_X0Y255", + "ilogic_loc": "ILOGIC_X0Y255", + "ologic_loc": "OLOGIC_X0Y255", + "idelay_loc": "IDELAY_X0Y255", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[167]", + "owire": "do_buf[167]", + "iwire": "di_buf[167]", + "twire": "t[167]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y255),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 3, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y255),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y266", + "site": "IOB_X0Y256", + "ilogic_loc": "ILOGIC_X0Y256", + "ologic_loc": "OLOGIC_X0Y256", + "idelay_loc": "IDELAY_X0Y256", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[168]", + "owire": "do_buf[168]", + "iwire": "di_buf[168]", + "twire": "t[168]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y256),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y268", + "site": "IOB_X0Y257", + "ilogic_loc": "ILOGIC_X0Y257", + "ologic_loc": "OLOGIC_X0Y257", + "idelay_loc": "IDELAY_X0Y257", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[169]", + "owire": "do_buf[169]", + "iwire": "di_buf[169]", + "twire": "t[169]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y257),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y268", + "site": "IOB_X0Y258", + "ilogic_loc": "ILOGIC_X0Y258", + "ologic_loc": "OLOGIC_X0Y258", + "idelay_loc": "IDELAY_X0Y258", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[170]", + "owire": "do_buf[170]", + "iwire": "di_buf[170]", + "twire": "t[170]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y258),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y27", + "site": "IOB_X0Y25", + "ilogic_loc": "ILOGIC_X0Y25", + "ologic_loc": "OLOGIC_X0Y25", + "idelay_loc": "IDELAY_X0Y25", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[171]", + "owire": "do_buf[171]", + "iwire": "di_buf[171]", + "twire": "t[171]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y27", + "site": "IOB_X0Y26", + "ilogic_loc": "ILOGIC_X0Y26", + "ologic_loc": "OLOGIC_X0Y26", + "idelay_loc": "IDELAY_X0Y26", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[172]", + "owire": "do_buf[172]", + "iwire": "di_buf[172]", + "twire": "t[172]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 2, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y26),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y270", + "site": "IOB_X0Y259", + "ilogic_loc": "ILOGIC_X0Y259", + "ologic_loc": "OLOGIC_X0Y259", + "idelay_loc": "IDELAY_X0Y259", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[173]", + "owire": "do_buf[173]", + "iwire": "di_buf[173]", + "twire": "t[173]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y270", + "site": "IOB_X0Y260", + "ilogic_loc": "ILOGIC_X0Y260", + "ologic_loc": "OLOGIC_X0Y260", + "idelay_loc": "IDELAY_X0Y260", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[174]", + "owire": "do_buf[174]", + "iwire": "di_buf[174]", + "twire": "t[174]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y272", + "site": "IOB_X0Y261", + "ilogic_loc": "ILOGIC_X0Y261", + "ologic_loc": "OLOGIC_X0Y261", + "idelay_loc": "IDELAY_X0Y261", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[175]", + "owire": "do_buf[175]", + "iwire": "di_buf[175]", + "twire": "t[175]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y272", + "site": "IOB_X0Y262", + "ilogic_loc": "ILOGIC_X0Y262", + "ologic_loc": "OLOGIC_X0Y262", + "idelay_loc": "IDELAY_X0Y262", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[176]", + "owire": "do_buf[176]", + "iwire": "di_buf[176]", + "twire": "t[176]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y274", + "site": "IOB_X0Y263", + "ilogic_loc": "ILOGIC_X0Y263", + "ologic_loc": "OLOGIC_X0Y263", + "idelay_loc": "IDELAY_X0Y263", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[177]", + "owire": "do_buf[177]", + "iwire": "di_buf[177]", + "twire": "t[177]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 3, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y263),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y263),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y274", + "site": "IOB_X0Y264", + "ilogic_loc": "ILOGIC_X0Y264", + "ologic_loc": "OLOGIC_X0Y264", + "idelay_loc": "IDELAY_X0Y264", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[178]", + "owire": "do_buf[178]", + "iwire": "di_buf[178]", + "twire": "t[178]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y276", + "site": "IOB_X0Y265", + "ilogic_loc": "ILOGIC_X0Y265", + "ologic_loc": "OLOGIC_X0Y265", + "idelay_loc": "IDELAY_X0Y265", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[179]", + "owire": "do_buf[179]", + "iwire": "di_buf[179]", + "twire": "t[179]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y276", + "site": "IOB_X0Y266", + "ilogic_loc": "ILOGIC_X0Y266", + "ologic_loc": "OLOGIC_X0Y266", + "idelay_loc": "IDELAY_X0Y266", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[180]", + "owire": "do_buf[180]", + "iwire": "di_buf[180]", + "twire": "t[180]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y266),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y266),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y278", + "site": "IOB_X0Y267", + "ilogic_loc": "ILOGIC_X0Y267", + "ologic_loc": "OLOGIC_X0Y267", + "idelay_loc": "IDELAY_X0Y267", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[181]", + "owire": "do_buf[181]", + "iwire": "di_buf[181]", + "twire": "t[181]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y278", + "site": "IOB_X0Y268", + "ilogic_loc": "ILOGIC_X0Y268", + "ologic_loc": "OLOGIC_X0Y268", + "idelay_loc": "IDELAY_X0Y268", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[182]", + "owire": "do_buf[182]", + "iwire": "di_buf[182]", + "twire": "t[182]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y280", + "site": "IOB_X0Y269", + "ilogic_loc": "ILOGIC_X0Y269", + "ologic_loc": "OLOGIC_X0Y269", + "idelay_loc": "IDELAY_X0Y269", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[183]", + "owire": "do_buf[183]", + "iwire": "di_buf[183]", + "twire": "t[183]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y280", + "site": "IOB_X0Y270", + "ilogic_loc": "ILOGIC_X0Y270", + "ologic_loc": "OLOGIC_X0Y270", + "idelay_loc": "IDELAY_X0Y270", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[184]", + "owire": "do_buf[184]", + "iwire": "di_buf[184]", + "twire": "t[184]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "LIOB18_X81Y282", + "site": "IOB_X0Y271", + "ilogic_loc": "ILOGIC_X0Y271", + "ologic_loc": "OLOGIC_X0Y271", + "idelay_loc": "IDELAY_X0Y271", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[185]", + "owire": "do_buf[185]", + "iwire": "di_buf[185]", + "twire": "t[185]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "LIOB18_X81Y282", + "site": "IOB_X0Y272", + "ilogic_loc": "ILOGIC_X0Y272", + "ologic_loc": "OLOGIC_X0Y272", + "idelay_loc": "IDELAY_X0Y272", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[186]", + "owire": "do_buf[186]", + "iwire": "di_buf[186]", + "twire": "t[186]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y284", + "site": "IOB_X0Y273", + "ilogic_loc": "ILOGIC_X0Y273", + "ologic_loc": "OLOGIC_X0Y273", + "idelay_loc": "IDELAY_X0Y273", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[187]", + "owire": "do_buf[187]", + "iwire": "di_buf[187]", + "twire": "t[187]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y284", + "site": "IOB_X0Y274", + "ilogic_loc": "ILOGIC_X0Y274", + "ologic_loc": "OLOGIC_X0Y274", + "idelay_loc": "IDELAY_X0Y274", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[188]", + "owire": "do_buf[188]", + "iwire": "di_buf[188]", + "twire": "t[188]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y274),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y287", + "site": "IOB_X0Y275", + "ilogic_loc": "ILOGIC_X0Y275", + "ologic_loc": "OLOGIC_X0Y275", + "idelay_loc": "IDELAY_X0Y275", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[189]", + "owire": "do_buf[189]", + "iwire": "di_buf[189]", + "twire": "t[189]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y287", + "site": "IOB_X0Y276", + "ilogic_loc": "ILOGIC_X0Y276", + "ologic_loc": "OLOGIC_X0Y276", + "idelay_loc": "IDELAY_X0Y276", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[190]", + "owire": "do_buf[190]", + "iwire": "di_buf[190]", + "twire": "t[190]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y289", + "site": "IOB_X0Y277", + "ilogic_loc": "ILOGIC_X0Y277", + "ologic_loc": "OLOGIC_X0Y277", + "idelay_loc": "IDELAY_X0Y277", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[191]", + "owire": "do_buf[191]", + "iwire": "di_buf[191]", + "twire": "t[191]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y277),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y289", + "site": "IOB_X0Y278", + "ilogic_loc": "ILOGIC_X0Y278", + "ologic_loc": "OLOGIC_X0Y278", + "idelay_loc": "IDELAY_X0Y278", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[192]", + "owire": "do_buf[192]", + "iwire": "di_buf[192]", + "twire": "t[192]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y29", + "site": "IOB_X0Y27", + "ilogic_loc": "ILOGIC_X0Y27", + "ologic_loc": "OLOGIC_X0Y27", + "idelay_loc": "IDELAY_X0Y27", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[193]", + "owire": "do_buf[193]", + "iwire": "di_buf[193]", + "twire": "t[193]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y27),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y29", + "site": "IOB_X0Y28", + "ilogic_loc": "ILOGIC_X0Y28", + "ologic_loc": "OLOGIC_X0Y28", + "idelay_loc": "IDELAY_X0Y28", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[194]", + "owire": "do_buf[194]", + "iwire": "di_buf[194]", + "twire": "t[194]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y291", + "site": "IOB_X0Y279", + "ilogic_loc": "ILOGIC_X0Y279", + "ologic_loc": "OLOGIC_X0Y279", + "idelay_loc": "IDELAY_X0Y279", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[195]", + "owire": "do_buf[195]", + "iwire": "di_buf[195]", + "twire": "t[195]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y279),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y291", + "site": "IOB_X0Y280", + "ilogic_loc": "ILOGIC_X0Y280", + "ologic_loc": "OLOGIC_X0Y280", + "idelay_loc": "IDELAY_X0Y280", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[196]", + "owire": "do_buf[196]", + "iwire": "di_buf[196]", + "twire": "t[196]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y280),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y280),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y293", + "site": "IOB_X0Y281", + "ilogic_loc": "ILOGIC_X0Y281", + "ologic_loc": "OLOGIC_X0Y281", + "idelay_loc": "IDELAY_X0Y281", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[197]", + "owire": "do_buf[197]", + "iwire": "di_buf[197]", + "twire": "t[197]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y281),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 7, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y281),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y293", + "site": "IOB_X0Y282", + "ilogic_loc": "ILOGIC_X0Y282", + "ologic_loc": "OLOGIC_X0Y282", + "idelay_loc": "IDELAY_X0Y282", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[198]", + "owire": "do_buf[198]", + "iwire": "di_buf[198]", + "twire": "t[198]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 5, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y282),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y295", + "site": "IOB_X0Y283", + "ilogic_loc": "ILOGIC_X0Y283", + "ologic_loc": "OLOGIC_X0Y283", + "idelay_loc": "IDELAY_X0Y283", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[199]", + "owire": "do_buf[199]", + "iwire": "di_buf[199]", + "twire": "t[199]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y295", + "site": "IOB_X0Y284", + "ilogic_loc": "ILOGIC_X0Y284", + "ologic_loc": "OLOGIC_X0Y284", + "idelay_loc": "IDELAY_X0Y284", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[200]", + "owire": "do_buf[200]", + "iwire": "di_buf[200]", + "twire": "t[200]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "LIOB18_X81Y297", + "site": "IOB_X0Y285", + "ilogic_loc": "ILOGIC_X0Y285", + "ologic_loc": "OLOGIC_X0Y285", + "idelay_loc": "IDELAY_X0Y285", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[201]", + "owire": "do_buf[201]", + "iwire": "di_buf[201]", + "twire": "t[201]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y285),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y297", + "site": "IOB_X0Y286", + "ilogic_loc": "ILOGIC_X0Y286", + "ologic_loc": "OLOGIC_X0Y286", + "idelay_loc": "IDELAY_X0Y286", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[202]", + "owire": "do_buf[202]", + "iwire": "di_buf[202]", + "twire": "t[202]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y299", + "site": "IOB_X0Y287", + "ilogic_loc": "ILOGIC_X0Y287", + "ologic_loc": "OLOGIC_X0Y287", + "idelay_loc": "IDELAY_X0Y287", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[203]", + "owire": "do_buf[203]", + "iwire": "di_buf[203]", + "twire": "t[203]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y287),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y287),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y299", + "site": "IOB_X0Y288", + "ilogic_loc": "ILOGIC_X0Y288", + "ologic_loc": "OLOGIC_X0Y288", + "idelay_loc": "IDELAY_X0Y288", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[204]", + "owire": "do_buf[204]", + "iwire": "di_buf[204]", + "twire": "t[204]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y301", + "site": "IOB_X0Y289", + "ilogic_loc": "ILOGIC_X0Y289", + "ologic_loc": "OLOGIC_X0Y289", + "idelay_loc": "IDELAY_X0Y289", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[205]", + "owire": "do_buf[205]", + "iwire": "di_buf[205]", + "twire": "t[205]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y301", + "site": "IOB_X0Y290", + "ilogic_loc": "ILOGIC_X0Y290", + "ologic_loc": "OLOGIC_X0Y290", + "idelay_loc": "IDELAY_X0Y290", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[206]", + "owire": "do_buf[206]", + "iwire": "di_buf[206]", + "twire": "t[206]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y303", + "site": "IOB_X0Y291", + "ilogic_loc": "ILOGIC_X0Y291", + "ologic_loc": "OLOGIC_X0Y291", + "idelay_loc": "IDELAY_X0Y291", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[207]", + "owire": "do_buf[207]", + "iwire": "di_buf[207]", + "twire": "t[207]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y291),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y303", + "site": "IOB_X0Y292", + "ilogic_loc": "ILOGIC_X0Y292", + "ologic_loc": "OLOGIC_X0Y292", + "idelay_loc": "IDELAY_X0Y292", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[208]", + "owire": "do_buf[208]", + "iwire": "di_buf[208]", + "twire": "t[208]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y292),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y305", + "site": "IOB_X0Y293", + "ilogic_loc": "ILOGIC_X0Y293", + "ologic_loc": "OLOGIC_X0Y293", + "idelay_loc": "IDELAY_X0Y293", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[209]", + "owire": "do_buf[209]", + "iwire": "di_buf[209]", + "twire": "t[209]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y293),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y305", + "site": "IOB_X0Y294", + "ilogic_loc": "ILOGIC_X0Y294", + "ologic_loc": "OLOGIC_X0Y294", + "idelay_loc": "IDELAY_X0Y294", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[210]", + "owire": "do_buf[210]", + "iwire": "di_buf[210]", + "twire": "t[210]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y307", + "site": "IOB_X0Y295", + "ilogic_loc": "ILOGIC_X0Y295", + "ologic_loc": "OLOGIC_X0Y295", + "idelay_loc": "IDELAY_X0Y295", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[211]", + "owire": "do_buf[211]", + "iwire": "di_buf[211]", + "twire": "t[211]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y295),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y295),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y307", + "site": "IOB_X0Y296", + "ilogic_loc": "ILOGIC_X0Y296", + "ologic_loc": "OLOGIC_X0Y296", + "idelay_loc": "IDELAY_X0Y296", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[212]", + "owire": "do_buf[212]", + "iwire": "di_buf[212]", + "twire": "t[212]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y296),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y309", + "site": "IOB_X0Y297", + "ilogic_loc": "ILOGIC_X0Y297", + "ologic_loc": "OLOGIC_X0Y297", + "idelay_loc": "IDELAY_X0Y297", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[213]", + "owire": "do_buf[213]", + "iwire": "di_buf[213]", + "twire": "t[213]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y297),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y309", + "site": "IOB_X0Y298", + "ilogic_loc": "ILOGIC_X0Y298", + "ologic_loc": "OLOGIC_X0Y298", + "idelay_loc": "IDELAY_X0Y298", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[214]", + "owire": "do_buf[214]", + "iwire": "di_buf[214]", + "twire": "t[214]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y298),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y31", + "site": "IOB_X0Y29", + "ilogic_loc": "ILOGIC_X0Y29", + "ologic_loc": "OLOGIC_X0Y29", + "idelay_loc": "IDELAY_X0Y29", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[215]", + "owire": "do_buf[215]", + "iwire": "di_buf[215]", + "twire": "t[215]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 5, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y31", + "site": "IOB_X0Y30", + "ilogic_loc": "ILOGIC_X0Y30", + "ologic_loc": "OLOGIC_X0Y30", + "idelay_loc": "IDELAY_X0Y30", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[216]", + "owire": "do_buf[216]", + "iwire": "di_buf[216]", + "twire": "t[216]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y314", + "site": "IOB_X0Y301", + "ilogic_loc": "ILOGIC_X0Y301", + "ologic_loc": "OLOGIC_X0Y301", + "idelay_loc": "IDELAY_X0Y301", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[217]", + "owire": "do_buf[217]", + "iwire": "di_buf[217]", + "twire": "t[217]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y301),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y314", + "site": "IOB_X0Y302", + "ilogic_loc": "ILOGIC_X0Y302", + "ologic_loc": "OLOGIC_X0Y302", + "idelay_loc": "IDELAY_X0Y302", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[218]", + "owire": "do_buf[218]", + "iwire": "di_buf[218]", + "twire": "t[218]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 5, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y302),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y316", + "site": "IOB_X0Y303", + "ilogic_loc": "ILOGIC_X0Y303", + "ologic_loc": "OLOGIC_X0Y303", + "idelay_loc": "IDELAY_X0Y303", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[219]", + "owire": "do_buf[219]", + "iwire": "di_buf[219]", + "twire": "t[219]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "LIOB18_X81Y316", + "site": "IOB_X0Y304", + "ilogic_loc": "ILOGIC_X0Y304", + "ologic_loc": "OLOGIC_X0Y304", + "idelay_loc": "IDELAY_X0Y304", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[220]", + "owire": "do_buf[220]", + "iwire": "di_buf[220]", + "twire": "t[220]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "LIOB18_X81Y318", + "site": "IOB_X0Y305", + "ilogic_loc": "ILOGIC_X0Y305", + "ologic_loc": "OLOGIC_X0Y305", + "idelay_loc": "IDELAY_X0Y305", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[221]", + "owire": "do_buf[221]", + "iwire": "di_buf[221]", + "twire": "t[221]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y318", + "site": "IOB_X0Y306", + "ilogic_loc": "ILOGIC_X0Y306", + "ologic_loc": "OLOGIC_X0Y306", + "idelay_loc": "IDELAY_X0Y306", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[222]", + "owire": "do_buf[222]", + "iwire": "di_buf[222]", + "twire": "t[222]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y320", + "site": "IOB_X0Y307", + "ilogic_loc": "ILOGIC_X0Y307", + "ologic_loc": "OLOGIC_X0Y307", + "idelay_loc": "IDELAY_X0Y307", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[223]", + "owire": "do_buf[223]", + "iwire": "di_buf[223]", + "twire": "t[223]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y320", + "site": "IOB_X0Y308", + "ilogic_loc": "ILOGIC_X0Y308", + "ologic_loc": "OLOGIC_X0Y308", + "idelay_loc": "IDELAY_X0Y308", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[224]", + "owire": "do_buf[224]", + "iwire": "di_buf[224]", + "twire": "t[224]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y322", + "site": "IOB_X0Y309", + "ilogic_loc": "ILOGIC_X0Y309", + "ologic_loc": "OLOGIC_X0Y309", + "idelay_loc": "IDELAY_X0Y309", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[225]", + "owire": "do_buf[225]", + "iwire": "di_buf[225]", + "twire": "t[225]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y322", + "site": "IOB_X0Y310", + "ilogic_loc": "ILOGIC_X0Y310", + "ologic_loc": "OLOGIC_X0Y310", + "idelay_loc": "IDELAY_X0Y310", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[226]", + "owire": "do_buf[226]", + "iwire": "di_buf[226]", + "twire": "t[226]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y310),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y324", + "site": "IOB_X0Y311", + "ilogic_loc": "ILOGIC_X0Y311", + "ologic_loc": "OLOGIC_X0Y311", + "idelay_loc": "IDELAY_X0Y311", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[227]", + "owire": "do_buf[227]", + "iwire": "di_buf[227]", + "twire": "t[227]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y324", + "site": "IOB_X0Y312", + "ilogic_loc": "ILOGIC_X0Y312", + "ologic_loc": "OLOGIC_X0Y312", + "idelay_loc": "IDELAY_X0Y312", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[228]", + "owire": "do_buf[228]", + "iwire": "di_buf[228]", + "twire": "t[228]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "LIOB18_X81Y326", + "site": "IOB_X0Y313", + "ilogic_loc": "ILOGIC_X0Y313", + "ologic_loc": "OLOGIC_X0Y313", + "idelay_loc": "IDELAY_X0Y313", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[229]", + "owire": "do_buf[229]", + "iwire": "di_buf[229]", + "twire": "t[229]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y326", + "site": "IOB_X0Y314", + "ilogic_loc": "ILOGIC_X0Y314", + "ologic_loc": "OLOGIC_X0Y314", + "idelay_loc": "IDELAY_X0Y314", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[230]", + "owire": "do_buf[230]", + "iwire": "di_buf[230]", + "twire": "t[230]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y328", + "site": "IOB_X0Y315", + "ilogic_loc": "ILOGIC_X0Y315", + "ologic_loc": "OLOGIC_X0Y315", + "idelay_loc": "IDELAY_X0Y315", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[231]", + "owire": "do_buf[231]", + "iwire": "di_buf[231]", + "twire": "t[231]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y315),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y315),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y328", + "site": "IOB_X0Y316", + "ilogic_loc": "ILOGIC_X0Y316", + "ologic_loc": "OLOGIC_X0Y316", + "idelay_loc": "IDELAY_X0Y316", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[232]", + "owire": "do_buf[232]", + "iwire": "di_buf[232]", + "twire": "t[232]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 5, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y316),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y33", + "site": "IOB_X0Y31", + "ilogic_loc": "ILOGIC_X0Y31", + "ologic_loc": "OLOGIC_X0Y31", + "idelay_loc": "IDELAY_X0Y31", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[233]", + "owire": "do_buf[233]", + "iwire": "di_buf[233]", + "twire": "t[233]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y33", + "site": "IOB_X0Y32", + "ilogic_loc": "ILOGIC_X0Y32", + "ologic_loc": "OLOGIC_X0Y32", + "idelay_loc": "IDELAY_X0Y32", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[234]", + "owire": "do_buf[234]", + "iwire": "di_buf[234]", + "twire": "t[234]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y330", + "site": "IOB_X0Y317", + "ilogic_loc": "ILOGIC_X0Y317", + "ologic_loc": "OLOGIC_X0Y317", + "idelay_loc": "IDELAY_X0Y317", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[235]", + "owire": "do_buf[235]", + "iwire": "di_buf[235]", + "twire": "t[235]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y330", + "site": "IOB_X0Y318", + "ilogic_loc": "ILOGIC_X0Y318", + "ologic_loc": "OLOGIC_X0Y318", + "idelay_loc": "IDELAY_X0Y318", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[236]", + "owire": "do_buf[236]", + "iwire": "di_buf[236]", + "twire": "t[236]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y332", + "site": "IOB_X0Y319", + "ilogic_loc": "ILOGIC_X0Y319", + "ologic_loc": "OLOGIC_X0Y319", + "idelay_loc": "IDELAY_X0Y319", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[237]", + "owire": "do_buf[237]", + "iwire": "di_buf[237]", + "twire": "t[237]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y332", + "site": "IOB_X0Y320", + "ilogic_loc": "ILOGIC_X0Y320", + "ologic_loc": "OLOGIC_X0Y320", + "idelay_loc": "IDELAY_X0Y320", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[238]", + "owire": "do_buf[238]", + "iwire": "di_buf[238]", + "twire": "t[238]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y320),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 7, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y320),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y334", + "site": "IOB_X0Y321", + "ilogic_loc": "ILOGIC_X0Y321", + "ologic_loc": "OLOGIC_X0Y321", + "idelay_loc": "IDELAY_X0Y321", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[239]", + "owire": "do_buf[239]", + "iwire": "di_buf[239]", + "twire": "t[239]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y334", + "site": "IOB_X0Y322", + "ilogic_loc": "ILOGIC_X0Y322", + "ologic_loc": "OLOGIC_X0Y322", + "idelay_loc": "IDELAY_X0Y322", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[240]", + "owire": "do_buf[240]", + "iwire": "di_buf[240]", + "twire": "t[240]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 7, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y322),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y322),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y336", + "site": "IOB_X0Y323", + "ilogic_loc": "ILOGIC_X0Y323", + "ologic_loc": "OLOGIC_X0Y323", + "idelay_loc": "IDELAY_X0Y323", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[241]", + "owire": "do_buf[241]", + "iwire": "di_buf[241]", + "twire": "t[241]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y336", + "site": "IOB_X0Y324", + "ilogic_loc": "ILOGIC_X0Y324", + "ologic_loc": "OLOGIC_X0Y324", + "idelay_loc": "IDELAY_X0Y324", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[242]", + "owire": "do_buf[242]", + "iwire": "di_buf[242]", + "twire": "t[242]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y339", + "site": "IOB_X0Y325", + "ilogic_loc": "ILOGIC_X0Y325", + "ologic_loc": "OLOGIC_X0Y325", + "idelay_loc": "IDELAY_X0Y325", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[243]", + "owire": "do_buf[243]", + "iwire": "di_buf[243]", + "twire": "t[243]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 2, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y325),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 7, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y325),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y339", + "site": "IOB_X0Y326", + "ilogic_loc": "ILOGIC_X0Y326", + "ologic_loc": "OLOGIC_X0Y326", + "idelay_loc": "IDELAY_X0Y326", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[244]", + "owire": "do_buf[244]", + "iwire": "di_buf[244]", + "twire": "t[244]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "LIOB18_X81Y341", + "site": "IOB_X0Y327", + "ilogic_loc": "ILOGIC_X0Y327", + "ologic_loc": "OLOGIC_X0Y327", + "idelay_loc": "IDELAY_X0Y327", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[245]", + "owire": "do_buf[245]", + "iwire": "di_buf[245]", + "twire": "t[245]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 3, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y327),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y327),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y341", + "site": "IOB_X0Y328", + "ilogic_loc": "ILOGIC_X0Y328", + "ologic_loc": "OLOGIC_X0Y328", + "idelay_loc": "IDELAY_X0Y328", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[246]", + "owire": "do_buf[246]", + "iwire": "di_buf[246]", + "twire": "t[246]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y328),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y328),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y343", + "site": "IOB_X0Y329", + "ilogic_loc": "ILOGIC_X0Y329", + "ologic_loc": "OLOGIC_X0Y329", + "idelay_loc": "IDELAY_X0Y329", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[247]", + "owire": "do_buf[247]", + "iwire": "di_buf[247]", + "twire": "t[247]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y343", + "site": "IOB_X0Y330", + "ilogic_loc": "ILOGIC_X0Y330", + "ologic_loc": "OLOGIC_X0Y330", + "idelay_loc": "IDELAY_X0Y330", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[248]", + "owire": "do_buf[248]", + "iwire": "di_buf[248]", + "twire": "t[248]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 2, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y330),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y330),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y345", + "site": "IOB_X0Y331", + "ilogic_loc": "ILOGIC_X0Y331", + "ologic_loc": "OLOGIC_X0Y331", + "idelay_loc": "IDELAY_X0Y331", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[249]", + "owire": "do_buf[249]", + "iwire": "di_buf[249]", + "twire": "t[249]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "LIOB18_X81Y345", + "site": "IOB_X0Y332", + "ilogic_loc": "ILOGIC_X0Y332", + "ologic_loc": "OLOGIC_X0Y332", + "idelay_loc": "IDELAY_X0Y332", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[250]", + "owire": "do_buf[250]", + "iwire": "di_buf[250]", + "twire": "t[250]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 5, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y332),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y347", + "site": "IOB_X0Y333", + "ilogic_loc": "ILOGIC_X0Y333", + "ologic_loc": "OLOGIC_X0Y333", + "idelay_loc": "IDELAY_X0Y333", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[251]", + "owire": "do_buf[251]", + "iwire": "di_buf[251]", + "twire": "t[251]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y347", + "site": "IOB_X0Y334", + "ilogic_loc": "ILOGIC_X0Y334", + "ologic_loc": "OLOGIC_X0Y334", + "idelay_loc": "IDELAY_X0Y334", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[252]", + "owire": "do_buf[252]", + "iwire": "di_buf[252]", + "twire": "t[252]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y349", + "site": "IOB_X0Y335", + "ilogic_loc": "ILOGIC_X0Y335", + "ologic_loc": "OLOGIC_X0Y335", + "idelay_loc": "IDELAY_X0Y335", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[253]", + "owire": "do_buf[253]", + "iwire": "di_buf[253]", + "twire": "t[253]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y349", + "site": "IOB_X0Y336", + "ilogic_loc": "ILOGIC_X0Y336", + "ologic_loc": "OLOGIC_X0Y336", + "idelay_loc": "IDELAY_X0Y336", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[254]", + "owire": "do_buf[254]", + "iwire": "di_buf[254]", + "twire": "t[254]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "LIOB18_X81Y35", + "site": "IOB_X0Y33", + "ilogic_loc": "ILOGIC_X0Y33", + "ologic_loc": "OLOGIC_X0Y33", + "idelay_loc": "IDELAY_X0Y33", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[255]", + "owire": "do_buf[255]", + "iwire": "di_buf[255]", + "twire": "t[255]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 3, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y35", + "site": "IOB_X0Y34", + "ilogic_loc": "ILOGIC_X0Y34", + "ologic_loc": "OLOGIC_X0Y34", + "idelay_loc": "IDELAY_X0Y34", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[256]", + "owire": "do_buf[256]", + "iwire": "di_buf[256]", + "twire": "t[256]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y34),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y34),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y351", + "site": "IOB_X0Y337", + "ilogic_loc": "ILOGIC_X0Y337", + "ologic_loc": "OLOGIC_X0Y337", + "idelay_loc": "IDELAY_X0Y337", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[257]", + "owire": "do_buf[257]", + "iwire": "di_buf[257]", + "twire": "t[257]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y337),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y351", + "site": "IOB_X0Y338", + "ilogic_loc": "ILOGIC_X0Y338", + "ologic_loc": "OLOGIC_X0Y338", + "idelay_loc": "IDELAY_X0Y338", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[258]", + "owire": "do_buf[258]", + "iwire": "di_buf[258]", + "twire": "t[258]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y338),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y338),\n ", + "DISABLE_CLOCKS": 1 + }, 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".DDLY(idelay_IOB_X0Y339),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y339),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y353", + "site": "IOB_X0Y340", + "ilogic_loc": "ILOGIC_X0Y340", + "ologic_loc": "OLOGIC_X0Y340", + "idelay_loc": "IDELAY_X0Y340", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[260]", + "owire": "do_buf[260]", + "iwire": "di_buf[260]", + "twire": "t[260]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y355", + "site": "IOB_X0Y341", + "ilogic_loc": "ILOGIC_X0Y341", + "ologic_loc": "OLOGIC_X0Y341", + "idelay_loc": "IDELAY_X0Y341", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[261]", + "owire": "do_buf[261]", + "iwire": "di_buf[261]", + "twire": "t[261]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y355", + "site": "IOB_X0Y342", + "ilogic_loc": "ILOGIC_X0Y342", + "ologic_loc": "OLOGIC_X0Y342", + "idelay_loc": "IDELAY_X0Y342", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[262]", + "owire": "do_buf[262]", + "iwire": "di_buf[262]", + "twire": "t[262]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y342),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y357", + "site": "IOB_X0Y343", + "ilogic_loc": "ILOGIC_X0Y343", + "ologic_loc": "OLOGIC_X0Y343", + "idelay_loc": "IDELAY_X0Y343", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[263]", + "owire": "do_buf[263]", + "iwire": "di_buf[263]", + "twire": "t[263]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 2, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y343),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y357", + "site": "IOB_X0Y344", + "ilogic_loc": "ILOGIC_X0Y344", + "ologic_loc": "OLOGIC_X0Y344", + "idelay_loc": "IDELAY_X0Y344", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[264]", + "owire": "do_buf[264]", + "iwire": "di_buf[264]", + "twire": "t[264]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y344),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y359", + "site": "IOB_X0Y345", + "ilogic_loc": "ILOGIC_X0Y345", + "ologic_loc": "OLOGIC_X0Y345", + "idelay_loc": "IDELAY_X0Y345", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[265]", + "owire": "do_buf[265]", + "iwire": "di_buf[265]", + "twire": "t[265]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y359", + "site": "IOB_X0Y346", + "ilogic_loc": "ILOGIC_X0Y346", + "ologic_loc": "OLOGIC_X0Y346", + "idelay_loc": "IDELAY_X0Y346", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[266]", + "owire": "do_buf[266]", + "iwire": "di_buf[266]", + "twire": "t[266]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y346),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y361", + "site": "IOB_X0Y347", + "ilogic_loc": "ILOGIC_X0Y347", + "ologic_loc": "OLOGIC_X0Y347", + "idelay_loc": "IDELAY_X0Y347", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[267]", + "owire": "do_buf[267]", + "iwire": "di_buf[267]", + "twire": "t[267]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y361", + "site": "IOB_X0Y348", + "ilogic_loc": "ILOGIC_X0Y348", + "ologic_loc": "OLOGIC_X0Y348", + "idelay_loc": "IDELAY_X0Y348", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[268]", + "owire": "do_buf[268]", + "iwire": "di_buf[268]", + "twire": "t[268]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 3, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y37", + "site": "IOB_X0Y35", + "ilogic_loc": "ILOGIC_X0Y35", + "ologic_loc": "OLOGIC_X0Y35", + "idelay_loc": "IDELAY_X0Y35", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[269]", + "owire": "do_buf[269]", + "iwire": "di_buf[269]", + "twire": "t[269]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y37", + "site": "IOB_X0Y36", + "ilogic_loc": "ILOGIC_X0Y36", + "ologic_loc": "OLOGIC_X0Y36", + "idelay_loc": "IDELAY_X0Y36", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[270]", + "owire": "do_buf[270]", + "iwire": "di_buf[270]", + "twire": "t[270]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 7, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y36),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y39", + "site": "IOB_X0Y37", + "ilogic_loc": "ILOGIC_X0Y37", + "ologic_loc": "OLOGIC_X0Y37", + "idelay_loc": "IDELAY_X0Y37", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[271]", + "owire": "do_buf[271]", + "iwire": "di_buf[271]", + "twire": "t[271]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y39", + "site": "IOB_X0Y38", + "ilogic_loc": "ILOGIC_X0Y38", + "ologic_loc": "OLOGIC_X0Y38", + "idelay_loc": "IDELAY_X0Y38", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[272]", + "owire": "do_buf[272]", + "iwire": "di_buf[272]", + "twire": "t[272]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 3, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y4", + "site": "IOB_X0Y3", + "ilogic_loc": "ILOGIC_X0Y3", + "ologic_loc": "OLOGIC_X0Y3", + "idelay_loc": "IDELAY_X0Y3", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[273]", + "owire": "do_buf[273]", + "iwire": "di_buf[273]", + "twire": "t[273]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y4", + "site": "IOB_X0Y4", + "ilogic_loc": "ILOGIC_X0Y4", + "ologic_loc": "OLOGIC_X0Y4", + "idelay_loc": "IDELAY_X0Y4", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[274]", + "owire": "do_buf[274]", + "iwire": "di_buf[274]", + "twire": "t[274]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 3, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y4),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y4),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y41", + "site": "IOB_X0Y39", + "ilogic_loc": "ILOGIC_X0Y39", + "ologic_loc": "OLOGIC_X0Y39", + "idelay_loc": "IDELAY_X0Y39", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[275]", + "owire": "do_buf[275]", + "iwire": "di_buf[275]", + "twire": "t[275]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y41", + "site": "IOB_X0Y40", + "ilogic_loc": "ILOGIC_X0Y40", + "ologic_loc": "OLOGIC_X0Y40", + "idelay_loc": "IDELAY_X0Y40", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[276]", + "owire": "do_buf[276]", + "iwire": "di_buf[276]", + "twire": "t[276]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "LIOB18_X81Y43", + "site": "IOB_X0Y41", + "ilogic_loc": "ILOGIC_X0Y41", + "ologic_loc": "OLOGIC_X0Y41", + "idelay_loc": "IDELAY_X0Y41", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[277]", + "owire": "do_buf[277]", + "iwire": "di_buf[277]", + "twire": "t[277]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "LIOB18_X81Y43", + "site": "IOB_X0Y42", + "ilogic_loc": "ILOGIC_X0Y42", + "ologic_loc": "OLOGIC_X0Y42", + "idelay_loc": "IDELAY_X0Y42", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[278]", + "owire": "do_buf[278]", + "iwire": "di_buf[278]", + "twire": "t[278]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y45", + "site": "IOB_X0Y43", + "ilogic_loc": "ILOGIC_X0Y43", + "ologic_loc": "OLOGIC_X0Y43", + "idelay_loc": "IDELAY_X0Y43", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[279]", + "owire": "do_buf[279]", + "iwire": "di_buf[279]", + "twire": "t[279]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y45", + "site": "IOB_X0Y44", + "ilogic_loc": "ILOGIC_X0Y44", + "ologic_loc": "OLOGIC_X0Y44", + "idelay_loc": "IDELAY_X0Y44", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[280]", + "owire": "do_buf[280]", + "iwire": "di_buf[280]", + "twire": "t[280]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y47", + "site": "IOB_X0Y45", + "ilogic_loc": "ILOGIC_X0Y45", + "ologic_loc": "OLOGIC_X0Y45", + "idelay_loc": "IDELAY_X0Y45", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[281]", + "owire": "do_buf[281]", + "iwire": "di_buf[281]", + "twire": "t[281]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y47", + "site": "IOB_X0Y46", + "ilogic_loc": "ILOGIC_X0Y46", + "ologic_loc": "OLOGIC_X0Y46", + "idelay_loc": "IDELAY_X0Y46", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[282]", + "owire": "do_buf[282]", + "iwire": "di_buf[282]", + "twire": "t[282]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "LIOB18_X81Y49", + "site": "IOB_X0Y47", + "ilogic_loc": "ILOGIC_X0Y47", + "ologic_loc": "OLOGIC_X0Y47", + "idelay_loc": "IDELAY_X0Y47", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[283]", + "owire": "do_buf[283]", + "iwire": "di_buf[283]", + "twire": "t[283]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "LIOB18_X81Y49", + "site": "IOB_X0Y48", + "ilogic_loc": "ILOGIC_X0Y48", + "ologic_loc": "OLOGIC_X0Y48", + "idelay_loc": "IDELAY_X0Y48", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[284]", + "owire": "do_buf[284]", + "iwire": "di_buf[284]", + "twire": "t[284]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "LIOB18_X81Y54", + "site": "IOB_X0Y51", + "ilogic_loc": "ILOGIC_X0Y51", + "ologic_loc": "OLOGIC_X0Y51", + "idelay_loc": "IDELAY_X0Y51", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[285]", + "owire": "do_buf[285]", + "iwire": "di_buf[285]", + "twire": "t[285]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "LIOB18_X81Y54", + "site": "IOB_X0Y52", + "ilogic_loc": "ILOGIC_X0Y52", + "ologic_loc": "OLOGIC_X0Y52", + "idelay_loc": "IDELAY_X0Y52", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[286]", + "owire": "do_buf[286]", + "iwire": "di_buf[286]", + "twire": "t[286]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 2, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y56", + "site": "IOB_X0Y53", + "ilogic_loc": "ILOGIC_X0Y53", + "ologic_loc": "OLOGIC_X0Y53", + "idelay_loc": "IDELAY_X0Y53", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[287]", + "owire": "do_buf[287]", + "iwire": "di_buf[287]", + "twire": "t[287]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y53),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 2, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y53),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y56", + "site": "IOB_X0Y54", + "ilogic_loc": "ILOGIC_X0Y54", + "ologic_loc": "OLOGIC_X0Y54", + "idelay_loc": "IDELAY_X0Y54", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[288]", + "owire": "do_buf[288]", + "iwire": "di_buf[288]", + "twire": "t[288]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 7, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y58", + "site": "IOB_X0Y55", + "ilogic_loc": "ILOGIC_X0Y55", + "ologic_loc": "OLOGIC_X0Y55", + "idelay_loc": "IDELAY_X0Y55", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[289]", + "owire": "do_buf[289]", + "iwire": "di_buf[289]", + "twire": "t[289]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "LIOB18_X81Y58", + "site": "IOB_X0Y56", + "ilogic_loc": "ILOGIC_X0Y56", + "ologic_loc": "OLOGIC_X0Y56", + "idelay_loc": "IDELAY_X0Y56", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[290]", + "owire": "do_buf[290]", + "iwire": "di_buf[290]", + "twire": "t[290]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y6", + "site": "IOB_X0Y5", + "ilogic_loc": "ILOGIC_X0Y5", + "ologic_loc": "OLOGIC_X0Y5", + "idelay_loc": "IDELAY_X0Y5", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[291]", + "owire": "do_buf[291]", + "iwire": "di_buf[291]", + "twire": "t[291]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y5),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y5),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y6", + "site": "IOB_X0Y6", + "ilogic_loc": "ILOGIC_X0Y6", + "ologic_loc": "OLOGIC_X0Y6", + "idelay_loc": "IDELAY_X0Y6", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[292]", + "owire": "do_buf[292]", + "iwire": "di_buf[292]", + "twire": "t[292]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y60", + "site": "IOB_X0Y57", + "ilogic_loc": "ILOGIC_X0Y57", + "ologic_loc": "OLOGIC_X0Y57", + "idelay_loc": "IDELAY_X0Y57", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[293]", + "owire": "do_buf[293]", + "iwire": "di_buf[293]", + "twire": "t[293]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 7, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y57),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y57),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y60", + "site": "IOB_X0Y58", + "ilogic_loc": "ILOGIC_X0Y58", + "ologic_loc": "OLOGIC_X0Y58", + "idelay_loc": "IDELAY_X0Y58", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[294]", + "owire": "do_buf[294]", + "iwire": "di_buf[294]", + "twire": "t[294]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y62", + "site": "IOB_X0Y59", + "ilogic_loc": "ILOGIC_X0Y59", + "ologic_loc": "OLOGIC_X0Y59", + "idelay_loc": "IDELAY_X0Y59", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[295]", + "owire": "do_buf[295]", + "iwire": "di_buf[295]", + "twire": "t[295]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y59),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y59),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y62", + "site": "IOB_X0Y60", + "ilogic_loc": "ILOGIC_X0Y60", + "ologic_loc": "OLOGIC_X0Y60", + "idelay_loc": "IDELAY_X0Y60", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[296]", + "owire": "do_buf[296]", + "iwire": "di_buf[296]", + "twire": "t[296]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "LIOB18_X81Y64", + "site": "IOB_X0Y61", + "ilogic_loc": "ILOGIC_X0Y61", + "ologic_loc": "OLOGIC_X0Y61", + "idelay_loc": "IDELAY_X0Y61", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[297]", + "owire": "do_buf[297]", + "iwire": "di_buf[297]", + "twire": "t[297]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y61),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y64", + "site": "IOB_X0Y62", + "ilogic_loc": "ILOGIC_X0Y62", + "ologic_loc": "OLOGIC_X0Y62", + "idelay_loc": "IDELAY_X0Y62", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[298]", + "owire": "do_buf[298]", + "iwire": "di_buf[298]", + "twire": "t[298]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 7, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y62),", + "ODATA_RATE": "\"DDR\"", + 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"owire": "do_buf[302]", + "iwire": "di_buf[302]", + "twire": "t[302]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y70", + "site": "IOB_X0Y67", + "ilogic_loc": "ILOGIC_X0Y67", + "ologic_loc": "OLOGIC_X0Y67", + "idelay_loc": "IDELAY_X0Y67", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[303]", + "owire": "do_buf[303]", + "iwire": "di_buf[303]", + "twire": "t[303]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": 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"\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y72", + "site": "IOB_X0Y69", + "ilogic_loc": "ILOGIC_X0Y69", + "ologic_loc": "OLOGIC_X0Y69", + "idelay_loc": "IDELAY_X0Y69", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[305]", + "owire": "do_buf[305]", + "iwire": "di_buf[305]", + "twire": "t[305]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y72", + "site": "IOB_X0Y70", + "ilogic_loc": "ILOGIC_X0Y70", + "ologic_loc": "OLOGIC_X0Y70", + "idelay_loc": "IDELAY_X0Y70", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[306]", + "owire": "do_buf[306]", + "iwire": "di_buf[306]", + "twire": "t[306]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y70),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y74", + "site": "IOB_X0Y71", + "ilogic_loc": "ILOGIC_X0Y71", + "ologic_loc": "OLOGIC_X0Y71", + "idelay_loc": "IDELAY_X0Y71", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[307]", + "owire": "do_buf[307]", + "iwire": "di_buf[307]", + "twire": "t[307]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y71),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y74", + "site": "IOB_X0Y72", + "ilogic_loc": "ILOGIC_X0Y72", + "ologic_loc": "OLOGIC_X0Y72", + "idelay_loc": "IDELAY_X0Y72", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[308]", + "owire": "do_buf[308]", + "iwire": "di_buf[308]", + "twire": "t[308]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y72),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 3, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y72),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y76", + "site": "IOB_X0Y73", + "ilogic_loc": "ILOGIC_X0Y73", + "ologic_loc": "OLOGIC_X0Y73", + "idelay_loc": "IDELAY_X0Y73", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[309]", + "owire": "do_buf[309]", + "iwire": "di_buf[309]", + "twire": "t[309]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "LIOB18_X81Y76", + "site": "IOB_X0Y74", + "ilogic_loc": "ILOGIC_X0Y74", + "ologic_loc": "OLOGIC_X0Y74", + "idelay_loc": "IDELAY_X0Y74", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[310]", + "owire": "do_buf[310]", + "iwire": "di_buf[310]", + "twire": "t[310]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y74),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 2, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y74),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y79", + "site": "IOB_X0Y75", + "ilogic_loc": "ILOGIC_X0Y75", + "ologic_loc": "OLOGIC_X0Y75", + "idelay_loc": "IDELAY_X0Y75", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[311]", + "owire": "do_buf[311]", + "iwire": "di_buf[311]", + "twire": "t[311]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y79", + "site": "IOB_X0Y76", + "ilogic_loc": "ILOGIC_X0Y76", + "ologic_loc": "OLOGIC_X0Y76", + "idelay_loc": "IDELAY_X0Y76", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[312]", + "owire": "do_buf[312]", + "iwire": "di_buf[312]", + "twire": "t[312]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y76),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y8", + "site": "IOB_X0Y7", + "ilogic_loc": "ILOGIC_X0Y7", + "ologic_loc": "OLOGIC_X0Y7", + "idelay_loc": "IDELAY_X0Y7", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[313]", + "owire": "do_buf[313]", + "iwire": "di_buf[313]", + "twire": "t[313]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "LIOB18_X81Y8", + "site": "IOB_X0Y8", + "ilogic_loc": "ILOGIC_X0Y8", + "ologic_loc": "OLOGIC_X0Y8", + "idelay_loc": "IDELAY_X0Y8", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[314]", + "owire": "do_buf[314]", + "iwire": "di_buf[314]", + "twire": "t[314]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 2, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y8),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y81", + "site": "IOB_X0Y77", + "ilogic_loc": "ILOGIC_X0Y77", + "ologic_loc": "OLOGIC_X0Y77", + "idelay_loc": "IDELAY_X0Y77", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[315]", + "owire": "do_buf[315]", + "iwire": "di_buf[315]", + "twire": "t[315]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 5, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y77),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 2, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y77),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y81", + "site": "IOB_X0Y78", + "ilogic_loc": "ILOGIC_X0Y78", + "ologic_loc": "OLOGIC_X0Y78", + "idelay_loc": "IDELAY_X0Y78", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[316]", + "owire": "do_buf[316]", + "iwire": "di_buf[316]", + "twire": "t[316]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y78),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y78),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y83", + "site": "IOB_X0Y79", + "ilogic_loc": "ILOGIC_X0Y79", + "ologic_loc": "OLOGIC_X0Y79", + "idelay_loc": "IDELAY_X0Y79", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[317]", + "owire": "do_buf[317]", + "iwire": "di_buf[317]", + "twire": "t[317]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y83", + "site": "IOB_X0Y80", + "ilogic_loc": "ILOGIC_X0Y80", + "ologic_loc": "OLOGIC_X0Y80", + "idelay_loc": "IDELAY_X0Y80", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[318]", + "owire": "do_buf[318]", + "iwire": "di_buf[318]", + "twire": "t[318]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 7, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y80),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 3, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y80),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y85", + "site": "IOB_X0Y81", + "ilogic_loc": "ILOGIC_X0Y81", + "ologic_loc": "OLOGIC_X0Y81", + "idelay_loc": "IDELAY_X0Y81", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[319]", + "owire": "do_buf[319]", + "iwire": "di_buf[319]", + "twire": "t[319]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "LIOB18_X81Y85", + "site": "IOB_X0Y82", + "ilogic_loc": "ILOGIC_X0Y82", + "ologic_loc": "OLOGIC_X0Y82", + "idelay_loc": "IDELAY_X0Y82", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[320]", + "owire": "do_buf[320]", + "iwire": "di_buf[320]", + "twire": "t[320]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y82),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y82),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y87", + "site": "IOB_X0Y83", + "ilogic_loc": "ILOGIC_X0Y83", + "ologic_loc": "OLOGIC_X0Y83", + "idelay_loc": "IDELAY_X0Y83", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[321]", + "owire": "do_buf[321]", + "iwire": "di_buf[321]", + "twire": "t[321]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y87", + "site": "IOB_X0Y84", + "ilogic_loc": "ILOGIC_X0Y84", + "ologic_loc": "OLOGIC_X0Y84", + "idelay_loc": "IDELAY_X0Y84", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[322]", + "owire": "do_buf[322]", + "iwire": "di_buf[322]", + "twire": "t[322]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y89", + "site": "IOB_X0Y85", + "ilogic_loc": "ILOGIC_X0Y85", + "ologic_loc": "OLOGIC_X0Y85", + "idelay_loc": "IDELAY_X0Y85", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[323]", + "owire": "do_buf[323]", + "iwire": "di_buf[323]", + "twire": "t[323]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y89", + "site": "IOB_X0Y86", + "ilogic_loc": "ILOGIC_X0Y86", + "ologic_loc": "OLOGIC_X0Y86", + "idelay_loc": "IDELAY_X0Y86", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[324]", + "owire": "do_buf[324]", + "iwire": "di_buf[324]", + "twire": "t[324]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y86),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y91", + "site": "IOB_X0Y87", + "ilogic_loc": "ILOGIC_X0Y87", + "ologic_loc": "OLOGIC_X0Y87", + "idelay_loc": "IDELAY_X0Y87", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[325]", + "owire": "do_buf[325]", + "iwire": "di_buf[325]", + "twire": "t[325]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "LIOB18_X81Y91", + "site": "IOB_X0Y88", + "ilogic_loc": "ILOGIC_X0Y88", + "ologic_loc": "OLOGIC_X0Y88", + "idelay_loc": "IDELAY_X0Y88", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[326]", + "owire": "do_buf[326]", + "iwire": "di_buf[326]", + "twire": "t[326]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "LIOB18_X81Y93", + "site": "IOB_X0Y89", + "ilogic_loc": "ILOGIC_X0Y89", + "ologic_loc": "OLOGIC_X0Y89", + "idelay_loc": "IDELAY_X0Y89", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[327]", + "owire": "do_buf[327]", + "iwire": "di_buf[327]", + "twire": "t[327]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "LIOB18_X81Y93", + "site": "IOB_X0Y90", + "ilogic_loc": "ILOGIC_X0Y90", + "ologic_loc": "OLOGIC_X0Y90", + "idelay_loc": "IDELAY_X0Y90", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[328]", + "owire": "do_buf[328]", + "iwire": "di_buf[328]", + "twire": "t[328]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 7, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y90),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y95", + "site": "IOB_X0Y91", + "ilogic_loc": "ILOGIC_X0Y91", + "ologic_loc": "OLOGIC_X0Y91", + "idelay_loc": "IDELAY_X0Y91", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[329]", + "owire": "do_buf[329]", + "iwire": "di_buf[329]", + "twire": "t[329]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y91),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 7, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y91),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y95", + "site": "IOB_X0Y92", + "ilogic_loc": "ILOGIC_X0Y92", + "ologic_loc": "OLOGIC_X0Y92", + "idelay_loc": "IDELAY_X0Y92", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[330]", + "owire": "do_buf[330]", + "iwire": "di_buf[330]", + "twire": "t[330]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y92),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "LIOB18_X81Y97", + "site": "IOB_X0Y93", + "ilogic_loc": "ILOGIC_X0Y93", + "ologic_loc": "OLOGIC_X0Y93", + "idelay_loc": "IDELAY_X0Y93", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[331]", + "owire": "do_buf[331]", + "iwire": "di_buf[331]", + "twire": "t[331]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y93),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y97", + "site": "IOB_X0Y94", + "ilogic_loc": "ILOGIC_X0Y94", + "ologic_loc": "OLOGIC_X0Y94", + "idelay_loc": "IDELAY_X0Y94", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[332]", + "owire": "do_buf[332]", + "iwire": "di_buf[332]", + "twire": "t[332]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y99", + "site": "IOB_X0Y95", + "ilogic_loc": "ILOGIC_X0Y95", + "ologic_loc": "OLOGIC_X0Y95", + "idelay_loc": "IDELAY_X0Y95", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[333]", + "owire": "do_buf[333]", + "iwire": "di_buf[333]", + "twire": "t[333]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y95),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 7, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y95),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "LIOB18_X81Y99", + "site": "IOB_X0Y96", + "ilogic_loc": "ILOGIC_X0Y96", + "ologic_loc": "OLOGIC_X0Y96", + "idelay_loc": "IDELAY_X0Y96", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[334]", + "owire": "do_buf[334]", + "iwire": "di_buf[334]", + "twire": "t[334]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X0Y96),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X0Y96),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y10", + "site": "IOB_X1Y9", + "ilogic_loc": "ILOGIC_X1Y9", + "ologic_loc": "OLOGIC_X1Y9", + "idelay_loc": "IDELAY_X1Y9", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[335]", + "owire": "do_buf[335]", + "iwire": "di_buf[335]", + "twire": "t[335]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 2, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y9),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y10", + "site": "IOB_X1Y10", + "ilogic_loc": "ILOGIC_X1Y10", + "ologic_loc": "OLOGIC_X1Y10", + "idelay_loc": "IDELAY_X1Y10", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[336]", + "owire": "do_buf[336]", + "iwire": "di_buf[336]", + "twire": "t[336]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y10),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y101", + "site": "IOB_X1Y97", + "ilogic_loc": "ILOGIC_X1Y97", + "ologic_loc": "OLOGIC_X1Y97", + "idelay_loc": "IDELAY_X1Y97", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[337]", + "owire": "do_buf[337]", + "iwire": "di_buf[337]", + "twire": "t[337]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y101", + "site": "IOB_X1Y98", + "ilogic_loc": "ILOGIC_X1Y98", + "ologic_loc": "OLOGIC_X1Y98", + "idelay_loc": "IDELAY_X1Y98", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[338]", + "owire": "do_buf[338]", + "iwire": "di_buf[338]", + "twire": "t[338]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y106", + "site": "IOB_X1Y101", + "ilogic_loc": "ILOGIC_X1Y101", + "ologic_loc": "OLOGIC_X1Y101", + "idelay_loc": "IDELAY_X1Y101", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[339]", + "owire": "do_buf[339]", + "iwire": "di_buf[339]", + "twire": "t[339]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y106", + "site": "IOB_X1Y102", + "ilogic_loc": "ILOGIC_X1Y102", + "ologic_loc": "OLOGIC_X1Y102", + "idelay_loc": "IDELAY_X1Y102", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[340]", + "owire": "do_buf[340]", + "iwire": "di_buf[340]", + "twire": "t[340]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 2, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y102),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 2, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y102),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y108", + "site": "IOB_X1Y103", + "ilogic_loc": "ILOGIC_X1Y103", + "ologic_loc": "OLOGIC_X1Y103", + "idelay_loc": "IDELAY_X1Y103", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[341]", + "owire": "do_buf[341]", + "iwire": "di_buf[341]", + "twire": "t[341]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y103),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y103),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y108", + "site": "IOB_X1Y104", + "ilogic_loc": "ILOGIC_X1Y104", + "ologic_loc": "OLOGIC_X1Y104", + "idelay_loc": "IDELAY_X1Y104", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[342]", + "owire": "do_buf[342]", + "iwire": "di_buf[342]", + "twire": "t[342]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 7, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y104),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y110", + "site": "IOB_X1Y105", + "ilogic_loc": "ILOGIC_X1Y105", + "ologic_loc": "OLOGIC_X1Y105", + "idelay_loc": "IDELAY_X1Y105", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[343]", + "owire": "do_buf[343]", + "iwire": "di_buf[343]", + "twire": "t[343]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y110", + "site": "IOB_X1Y106", + "ilogic_loc": "ILOGIC_X1Y106", + "ologic_loc": "OLOGIC_X1Y106", + "idelay_loc": "IDELAY_X1Y106", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[344]", + "owire": "do_buf[344]", + "iwire": "di_buf[344]", + "twire": "t[344]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y106),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y106),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y112", + "site": "IOB_X1Y107", + "ilogic_loc": "ILOGIC_X1Y107", + "ologic_loc": "OLOGIC_X1Y107", + "idelay_loc": "IDELAY_X1Y107", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[345]", + "owire": "do_buf[345]", + "iwire": "di_buf[345]", + "twire": "t[345]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 5, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y112", + "site": "IOB_X1Y108", + "ilogic_loc": "ILOGIC_X1Y108", + "ologic_loc": "OLOGIC_X1Y108", + "idelay_loc": "IDELAY_X1Y108", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[346]", + "owire": "do_buf[346]", + "iwire": "di_buf[346]", + "twire": "t[346]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 2, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y108),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y114", + "site": "IOB_X1Y109", + "ilogic_loc": "ILOGIC_X1Y109", + "ologic_loc": "OLOGIC_X1Y109", + "idelay_loc": "IDELAY_X1Y109", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[347]", + "owire": "do_buf[347]", + "iwire": "di_buf[347]", + "twire": "t[347]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y114", + "site": "IOB_X1Y110", + "ilogic_loc": "ILOGIC_X1Y110", + "ologic_loc": "OLOGIC_X1Y110", + "idelay_loc": "IDELAY_X1Y110", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[348]", + "owire": "do_buf[348]", + "iwire": "di_buf[348]", + "twire": "t[348]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y110),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 7, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y110),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y116", + "site": "IOB_X1Y111", + "ilogic_loc": "ILOGIC_X1Y111", + "ologic_loc": "OLOGIC_X1Y111", + "idelay_loc": "IDELAY_X1Y111", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[349]", + "owire": "do_buf[349]", + "iwire": "di_buf[349]", + "twire": "t[349]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y111),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y116", + "site": "IOB_X1Y112", + "ilogic_loc": "ILOGIC_X1Y112", + "ologic_loc": "OLOGIC_X1Y112", + "idelay_loc": "IDELAY_X1Y112", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[350]", + "owire": "do_buf[350]", + "iwire": "di_buf[350]", + "twire": "t[350]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y112),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y112),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y118", + "site": "IOB_X1Y113", + "ilogic_loc": "ILOGIC_X1Y113", + "ologic_loc": "OLOGIC_X1Y113", + "idelay_loc": "IDELAY_X1Y113", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[351]", + "owire": "do_buf[351]", + "iwire": "di_buf[351]", + "twire": "t[351]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y118", + "site": "IOB_X1Y114", + "ilogic_loc": "ILOGIC_X1Y114", + "ologic_loc": "OLOGIC_X1Y114", + "idelay_loc": "IDELAY_X1Y114", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[352]", + "owire": "do_buf[352]", + "iwire": "di_buf[352]", + "twire": "t[352]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y114),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y114),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y12", + "site": "IOB_X1Y11", + "ilogic_loc": "ILOGIC_X1Y11", + "ologic_loc": "OLOGIC_X1Y11", + "idelay_loc": "IDELAY_X1Y11", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[353]", + "owire": "do_buf[353]", + "iwire": "di_buf[353]", + "twire": "t[353]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y12", + "site": "IOB_X1Y12", + "ilogic_loc": "ILOGIC_X1Y12", + "ologic_loc": "OLOGIC_X1Y12", + "idelay_loc": "IDELAY_X1Y12", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[354]", + "owire": "do_buf[354]", + "iwire": "di_buf[354]", + "twire": "t[354]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y120", + "site": "IOB_X1Y115", + "ilogic_loc": "ILOGIC_X1Y115", + "ologic_loc": "OLOGIC_X1Y115", + "idelay_loc": "IDELAY_X1Y115", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[355]", + "owire": "do_buf[355]", + "iwire": "di_buf[355]", + "twire": "t[355]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y120", + "site": "IOB_X1Y116", + "ilogic_loc": "ILOGIC_X1Y116", + "ologic_loc": "OLOGIC_X1Y116", + "idelay_loc": "IDELAY_X1Y116", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[356]", + "owire": "do_buf[356]", + "iwire": "di_buf[356]", + "twire": "t[356]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y122", + "site": "IOB_X1Y117", + "ilogic_loc": "ILOGIC_X1Y117", + "ologic_loc": "OLOGIC_X1Y117", + "idelay_loc": "IDELAY_X1Y117", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[357]", + "owire": "do_buf[357]", + "iwire": "di_buf[357]", + "twire": "t[357]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 7, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y117),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y122", + "site": "IOB_X1Y118", + "ilogic_loc": "ILOGIC_X1Y118", + "ologic_loc": "OLOGIC_X1Y118", + "idelay_loc": "IDELAY_X1Y118", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[358]", + "owire": "do_buf[358]", + "iwire": "di_buf[358]", + "twire": "t[358]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y124", + "site": "IOB_X1Y119", + "ilogic_loc": "ILOGIC_X1Y119", + "ologic_loc": "OLOGIC_X1Y119", + "idelay_loc": "IDELAY_X1Y119", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[359]", + "owire": "do_buf[359]", + "iwire": "di_buf[359]", + "twire": "t[359]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y119),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y119),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y124", + "site": "IOB_X1Y120", + "ilogic_loc": "ILOGIC_X1Y120", + "ologic_loc": "OLOGIC_X1Y120", + "idelay_loc": "IDELAY_X1Y120", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[360]", + "owire": "do_buf[360]", + "iwire": "di_buf[360]", + "twire": "t[360]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y126", + "site": "IOB_X1Y121", + "ilogic_loc": "ILOGIC_X1Y121", + "ologic_loc": "OLOGIC_X1Y121", + "idelay_loc": "IDELAY_X1Y121", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[361]", + "owire": "do_buf[361]", + "iwire": "di_buf[361]", + "twire": "t[361]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y126", + "site": "IOB_X1Y122", + "ilogic_loc": "ILOGIC_X1Y122", + "ologic_loc": "OLOGIC_X1Y122", + "idelay_loc": "IDELAY_X1Y122", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[362]", + "owire": "do_buf[362]", + "iwire": "di_buf[362]", + "twire": "t[362]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y128", + "site": "IOB_X1Y123", + "ilogic_loc": "ILOGIC_X1Y123", + "ologic_loc": "OLOGIC_X1Y123", + "idelay_loc": "IDELAY_X1Y123", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[363]", + "owire": "do_buf[363]", + "iwire": "di_buf[363]", + "twire": "t[363]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y128", + "site": "IOB_X1Y124", + "ilogic_loc": "ILOGIC_X1Y124", + "ologic_loc": "OLOGIC_X1Y124", + "idelay_loc": "IDELAY_X1Y124", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[364]", + "owire": "do_buf[364]", + "iwire": "di_buf[364]", + "twire": "t[364]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y124),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 3, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y124),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y131", + "site": "IOB_X1Y125", + "ilogic_loc": "ILOGIC_X1Y125", + "ologic_loc": "OLOGIC_X1Y125", + "idelay_loc": "IDELAY_X1Y125", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[365]", + "owire": "do_buf[365]", + "iwire": "di_buf[365]", + "twire": "t[365]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y131", + "site": "IOB_X1Y126", + "ilogic_loc": "ILOGIC_X1Y126", + "ologic_loc": "OLOGIC_X1Y126", + "idelay_loc": "IDELAY_X1Y126", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[366]", + "owire": "do_buf[366]", + "iwire": "di_buf[366]", + "twire": "t[366]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y133", + "site": "IOB_X1Y127", + "ilogic_loc": "ILOGIC_X1Y127", + "ologic_loc": "OLOGIC_X1Y127", + "idelay_loc": "IDELAY_X1Y127", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[367]", + "owire": "do_buf[367]", + "iwire": "di_buf[367]", + "twire": "t[367]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y133", + "site": "IOB_X1Y128", + "ilogic_loc": "ILOGIC_X1Y128", + "ologic_loc": "OLOGIC_X1Y128", + "idelay_loc": "IDELAY_X1Y128", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[368]", + "owire": "do_buf[368]", + "iwire": "di_buf[368]", + "twire": "t[368]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y128),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y135", + "site": "IOB_X1Y129", + "ilogic_loc": "ILOGIC_X1Y129", + "ologic_loc": "OLOGIC_X1Y129", + "idelay_loc": "IDELAY_X1Y129", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[369]", + "owire": "do_buf[369]", + "iwire": "di_buf[369]", + "twire": "t[369]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y129),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y135", + "site": "IOB_X1Y130", + "ilogic_loc": "ILOGIC_X1Y130", + "ologic_loc": "OLOGIC_X1Y130", + "idelay_loc": "IDELAY_X1Y130", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[370]", + "owire": "do_buf[370]", + "iwire": "di_buf[370]", + "twire": "t[370]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y137", + "site": "IOB_X1Y131", + "ilogic_loc": "ILOGIC_X1Y131", + "ologic_loc": "OLOGIC_X1Y131", + "idelay_loc": "IDELAY_X1Y131", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[371]", + "owire": "do_buf[371]", + "iwire": "di_buf[371]", + "twire": "t[371]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 7, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y137", + "site": "IOB_X1Y132", + "ilogic_loc": "ILOGIC_X1Y132", + "ologic_loc": "OLOGIC_X1Y132", + "idelay_loc": "IDELAY_X1Y132", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[372]", + "owire": "do_buf[372]", + "iwire": "di_buf[372]", + "twire": "t[372]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y132),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y139", + "site": "IOB_X1Y133", + "ilogic_loc": "ILOGIC_X1Y133", + "ologic_loc": "OLOGIC_X1Y133", + "idelay_loc": "IDELAY_X1Y133", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[373]", + "owire": "do_buf[373]", + "iwire": "di_buf[373]", + "twire": "t[373]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 7, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y139", + "site": "IOB_X1Y134", + "ilogic_loc": "ILOGIC_X1Y134", + "ologic_loc": "OLOGIC_X1Y134", + "idelay_loc": "IDELAY_X1Y134", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[374]", + "owire": "do_buf[374]", + "iwire": "di_buf[374]", + "twire": "t[374]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y14", + "site": "IOB_X1Y13", + "ilogic_loc": "ILOGIC_X1Y13", + "ologic_loc": "OLOGIC_X1Y13", + "idelay_loc": "IDELAY_X1Y13", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[375]", + "owire": "do_buf[375]", + "iwire": "di_buf[375]", + "twire": "t[375]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y14", + "site": "IOB_X1Y14", + "ilogic_loc": "ILOGIC_X1Y14", + "ologic_loc": "OLOGIC_X1Y14", + "idelay_loc": "IDELAY_X1Y14", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[376]", + "owire": "do_buf[376]", + "iwire": "di_buf[376]", + "twire": "t[376]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y141", + "site": "IOB_X1Y135", + "ilogic_loc": "ILOGIC_X1Y135", + "ologic_loc": "OLOGIC_X1Y135", + "idelay_loc": "IDELAY_X1Y135", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[377]", + "owire": "do_buf[377]", + "iwire": "di_buf[377]", + "twire": "t[377]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y141", + "site": "IOB_X1Y136", + "ilogic_loc": "ILOGIC_X1Y136", + "ologic_loc": "OLOGIC_X1Y136", + "idelay_loc": "IDELAY_X1Y136", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[378]", + "owire": "do_buf[378]", + "iwire": "di_buf[378]", + "twire": "t[378]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y143", + "site": "IOB_X1Y137", + "ilogic_loc": "ILOGIC_X1Y137", + "ologic_loc": "OLOGIC_X1Y137", + "idelay_loc": "IDELAY_X1Y137", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[379]", + "owire": "do_buf[379]", + "iwire": "di_buf[379]", + "twire": "t[379]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y137),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y143", + "site": "IOB_X1Y138", + "ilogic_loc": "ILOGIC_X1Y138", + "ologic_loc": "OLOGIC_X1Y138", + "idelay_loc": "IDELAY_X1Y138", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[380]", + "owire": "do_buf[380]", + "iwire": "di_buf[380]", + "twire": "t[380]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y138),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y138),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y145", + "site": "IOB_X1Y139", + "ilogic_loc": "ILOGIC_X1Y139", + "ologic_loc": "OLOGIC_X1Y139", + "idelay_loc": "IDELAY_X1Y139", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[381]", + "owire": "do_buf[381]", + "iwire": "di_buf[381]", + "twire": "t[381]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 7, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y139),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y145", + "site": "IOB_X1Y140", + "ilogic_loc": "ILOGIC_X1Y140", + "ologic_loc": "OLOGIC_X1Y140", + "idelay_loc": "IDELAY_X1Y140", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[382]", + "owire": "do_buf[382]", + "iwire": "di_buf[382]", + "twire": "t[382]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y147", + "site": "IOB_X1Y141", + "ilogic_loc": "ILOGIC_X1Y141", + "ologic_loc": "OLOGIC_X1Y141", + "idelay_loc": "IDELAY_X1Y141", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[383]", + "owire": "do_buf[383]", + "iwire": "di_buf[383]", + "twire": "t[383]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y147", + "site": "IOB_X1Y142", + "ilogic_loc": "ILOGIC_X1Y142", + "ologic_loc": "OLOGIC_X1Y142", + "idelay_loc": "IDELAY_X1Y142", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[384]", + "owire": "do_buf[384]", + "iwire": "di_buf[384]", + "twire": "t[384]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y149", + "site": "IOB_X1Y143", + "ilogic_loc": "ILOGIC_X1Y143", + "ologic_loc": "OLOGIC_X1Y143", + "idelay_loc": "IDELAY_X1Y143", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[385]", + "owire": "do_buf[385]", + "iwire": "di_buf[385]", + "twire": "t[385]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y149", + "site": "IOB_X1Y144", + "ilogic_loc": "ILOGIC_X1Y144", + "ologic_loc": "OLOGIC_X1Y144", + "idelay_loc": "IDELAY_X1Y144", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[386]", + "owire": "do_buf[386]", + "iwire": "di_buf[386]", + "twire": "t[386]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y151", + "site": "IOB_X1Y145", + "ilogic_loc": "ILOGIC_X1Y145", + "ologic_loc": "OLOGIC_X1Y145", + "idelay_loc": "IDELAY_X1Y145", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[387]", + "owire": "do_buf[387]", + "iwire": "di_buf[387]", + "twire": "t[387]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y151", + "site": "IOB_X1Y146", + "ilogic_loc": "ILOGIC_X1Y146", + "ologic_loc": "OLOGIC_X1Y146", + "idelay_loc": "IDELAY_X1Y146", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[388]", + "owire": "do_buf[388]", + "iwire": "di_buf[388]", + "twire": "t[388]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 5, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y146),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y153", + "site": "IOB_X1Y147", + "ilogic_loc": "ILOGIC_X1Y147", + "ologic_loc": "OLOGIC_X1Y147", + "idelay_loc": "IDELAY_X1Y147", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[389]", + "owire": "do_buf[389]", + "iwire": "di_buf[389]", + "twire": "t[389]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y153", + "site": "IOB_X1Y148", + "ilogic_loc": "ILOGIC_X1Y148", + "ologic_loc": "OLOGIC_X1Y148", + "idelay_loc": "IDELAY_X1Y148", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[390]", + "owire": "do_buf[390]", + "iwire": "di_buf[390]", + "twire": "t[390]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 3, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y148),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y158", + "site": "IOB_X1Y151", + "ilogic_loc": "ILOGIC_X1Y151", + "ologic_loc": "OLOGIC_X1Y151", + "idelay_loc": "IDELAY_X1Y151", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[391]", + "owire": "do_buf[391]", + "iwire": "di_buf[391]", + "twire": "t[391]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y158", + "site": "IOB_X1Y152", + "ilogic_loc": "ILOGIC_X1Y152", + "ologic_loc": "OLOGIC_X1Y152", + "idelay_loc": "IDELAY_X1Y152", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[392]", + "owire": "do_buf[392]", + "iwire": "di_buf[392]", + "twire": "t[392]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y16", + "site": "IOB_X1Y15", + "ilogic_loc": "ILOGIC_X1Y15", + "ologic_loc": "OLOGIC_X1Y15", + "idelay_loc": "IDELAY_X1Y15", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[393]", + "owire": "do_buf[393]", + "iwire": "di_buf[393]", + "twire": "t[393]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 5, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y15),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 5, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y15),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y16", + "site": "IOB_X1Y16", + "ilogic_loc": "ILOGIC_X1Y16", + "ologic_loc": "OLOGIC_X1Y16", + "idelay_loc": "IDELAY_X1Y16", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[394]", + "owire": "do_buf[394]", + "iwire": "di_buf[394]", + "twire": "t[394]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y160", + "site": "IOB_X1Y153", + "ilogic_loc": "ILOGIC_X1Y153", + "ologic_loc": "OLOGIC_X1Y153", + "idelay_loc": "IDELAY_X1Y153", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[395]", + "owire": "do_buf[395]", + "iwire": "di_buf[395]", + "twire": "t[395]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y160", + "site": "IOB_X1Y154", + "ilogic_loc": "ILOGIC_X1Y154", + "ologic_loc": "OLOGIC_X1Y154", + "idelay_loc": "IDELAY_X1Y154", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[396]", + "owire": "do_buf[396]", + "iwire": "di_buf[396]", + "twire": "t[396]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y162", + "site": "IOB_X1Y155", + "ilogic_loc": "ILOGIC_X1Y155", + "ologic_loc": "OLOGIC_X1Y155", + "idelay_loc": "IDELAY_X1Y155", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[397]", + "owire": "do_buf[397]", + "iwire": "di_buf[397]", + "twire": "t[397]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y162", + "site": "IOB_X1Y156", + "ilogic_loc": "ILOGIC_X1Y156", + "ologic_loc": "OLOGIC_X1Y156", + "idelay_loc": "IDELAY_X1Y156", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[398]", + "owire": "do_buf[398]", + "iwire": "di_buf[398]", + "twire": "t[398]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y164", + "site": "IOB_X1Y157", + "ilogic_loc": "ILOGIC_X1Y157", + "ologic_loc": "OLOGIC_X1Y157", + "idelay_loc": "IDELAY_X1Y157", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[399]", + "owire": "do_buf[399]", + "iwire": "di_buf[399]", + "twire": "t[399]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y164", + "site": "IOB_X1Y158", + "ilogic_loc": "ILOGIC_X1Y158", + "ologic_loc": "OLOGIC_X1Y158", + "idelay_loc": "IDELAY_X1Y158", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[400]", + "owire": "do_buf[400]", + "iwire": "di_buf[400]", + "twire": "t[400]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y166", + "site": "IOB_X1Y159", + "ilogic_loc": "ILOGIC_X1Y159", + "ologic_loc": "OLOGIC_X1Y159", + "idelay_loc": "IDELAY_X1Y159", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[401]", + "owire": "do_buf[401]", + "iwire": "di_buf[401]", + "twire": "t[401]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y166", + "site": "IOB_X1Y160", + "ilogic_loc": "ILOGIC_X1Y160", + "ologic_loc": "OLOGIC_X1Y160", + "idelay_loc": "IDELAY_X1Y160", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[402]", + "owire": "do_buf[402]", + "iwire": "di_buf[402]", + "twire": "t[402]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y160),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y160),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y168", + "site": "IOB_X1Y161", + "ilogic_loc": "ILOGIC_X1Y161", + "ologic_loc": "OLOGIC_X1Y161", + "idelay_loc": "IDELAY_X1Y161", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[403]", + "owire": "do_buf[403]", + "iwire": "di_buf[403]", + "twire": "t[403]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y161),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y161),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y168", + "site": "IOB_X1Y162", + "ilogic_loc": "ILOGIC_X1Y162", + "ologic_loc": "OLOGIC_X1Y162", + "idelay_loc": "IDELAY_X1Y162", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[404]", + "owire": "do_buf[404]", + "iwire": "di_buf[404]", + "twire": "t[404]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y162),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 5, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y162),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y170", + "site": "IOB_X1Y163", + "ilogic_loc": "ILOGIC_X1Y163", + "ologic_loc": "OLOGIC_X1Y163", + "idelay_loc": "IDELAY_X1Y163", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[405]", + "owire": "do_buf[405]", + "iwire": "di_buf[405]", + "twire": "t[405]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y163),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y170", + "site": "IOB_X1Y164", + "ilogic_loc": "ILOGIC_X1Y164", + "ologic_loc": "OLOGIC_X1Y164", + "idelay_loc": "IDELAY_X1Y164", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[406]", + "owire": "do_buf[406]", + "iwire": "di_buf[406]", + "twire": "t[406]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y172", + "site": "IOB_X1Y165", + "ilogic_loc": "ILOGIC_X1Y165", + "ologic_loc": "OLOGIC_X1Y165", + "idelay_loc": "IDELAY_X1Y165", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[407]", + "owire": "do_buf[407]", + "iwire": "di_buf[407]", + "twire": "t[407]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y172", + "site": "IOB_X1Y166", + "ilogic_loc": "ILOGIC_X1Y166", + "ologic_loc": "OLOGIC_X1Y166", + "idelay_loc": "IDELAY_X1Y166", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[408]", + "owire": "do_buf[408]", + "iwire": "di_buf[408]", + "twire": "t[408]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y166),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y174", + "site": "IOB_X1Y167", + "ilogic_loc": "ILOGIC_X1Y167", + "ologic_loc": "OLOGIC_X1Y167", + "idelay_loc": "IDELAY_X1Y167", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[409]", + "owire": "do_buf[409]", + "iwire": "di_buf[409]", + "twire": "t[409]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y174", + "site": "IOB_X1Y168", + "ilogic_loc": "ILOGIC_X1Y168", + "ologic_loc": "OLOGIC_X1Y168", + "idelay_loc": "IDELAY_X1Y168", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[410]", + "owire": "do_buf[410]", + "iwire": "di_buf[410]", + "twire": "t[410]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y176", + "site": "IOB_X1Y169", + "ilogic_loc": "ILOGIC_X1Y169", + "ologic_loc": "OLOGIC_X1Y169", + "idelay_loc": "IDELAY_X1Y169", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[411]", + "owire": "do_buf[411]", + "iwire": "di_buf[411]", + "twire": "t[411]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 3, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y169),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y176", + "site": "IOB_X1Y170", + "ilogic_loc": "ILOGIC_X1Y170", + "ologic_loc": "OLOGIC_X1Y170", + "idelay_loc": "IDELAY_X1Y170", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[412]", + "owire": "do_buf[412]", + "iwire": "di_buf[412]", + "twire": "t[412]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y178", + "site": "IOB_X1Y171", + "ilogic_loc": "ILOGIC_X1Y171", + "ologic_loc": "OLOGIC_X1Y171", + "idelay_loc": "IDELAY_X1Y171", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[413]", + "owire": "do_buf[413]", + "iwire": "di_buf[413]", + "twire": "t[413]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 3, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y171),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y171),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y178", + "site": "IOB_X1Y172", + "ilogic_loc": "ILOGIC_X1Y172", + "ologic_loc": "OLOGIC_X1Y172", + "idelay_loc": "IDELAY_X1Y172", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[414]", + "owire": "do_buf[414]", + "iwire": "di_buf[414]", + "twire": "t[414]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y18", + "site": "IOB_X1Y17", + "ilogic_loc": "ILOGIC_X1Y17", + "ologic_loc": "OLOGIC_X1Y17", + "idelay_loc": "IDELAY_X1Y17", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[415]", + "owire": "do_buf[415]", + "iwire": "di_buf[415]", + "twire": "t[415]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y18", + "site": "IOB_X1Y18", + "ilogic_loc": "ILOGIC_X1Y18", + "ologic_loc": "OLOGIC_X1Y18", + "idelay_loc": "IDELAY_X1Y18", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[416]", + "owire": "do_buf[416]", + "iwire": "di_buf[416]", + "twire": "t[416]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y180", + "site": "IOB_X1Y173", + "ilogic_loc": "ILOGIC_X1Y173", + "ologic_loc": "OLOGIC_X1Y173", + "idelay_loc": "IDELAY_X1Y173", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[417]", + "owire": "do_buf[417]", + "iwire": "di_buf[417]", + "twire": "t[417]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y180", + "site": "IOB_X1Y174", + "ilogic_loc": "ILOGIC_X1Y174", + "ologic_loc": "OLOGIC_X1Y174", + "idelay_loc": "IDELAY_X1Y174", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[418]", + "owire": "do_buf[418]", + "iwire": "di_buf[418]", + "twire": "t[418]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y183", + "site": "IOB_X1Y175", + "ilogic_loc": "ILOGIC_X1Y175", + "ologic_loc": "OLOGIC_X1Y175", + "idelay_loc": "IDELAY_X1Y175", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[419]", + "owire": "do_buf[419]", + "iwire": "di_buf[419]", + "twire": "t[419]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y183", + "site": "IOB_X1Y176", + "ilogic_loc": "ILOGIC_X1Y176", + "ologic_loc": "OLOGIC_X1Y176", + "idelay_loc": "IDELAY_X1Y176", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[420]", + "owire": "do_buf[420]", + "iwire": "di_buf[420]", + "twire": "t[420]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y185", + "site": "IOB_X1Y177", + "ilogic_loc": "ILOGIC_X1Y177", + "ologic_loc": "OLOGIC_X1Y177", + "idelay_loc": "IDELAY_X1Y177", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[421]", + "owire": "do_buf[421]", + "iwire": "di_buf[421]", + "twire": "t[421]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y177),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y177),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y185", + "site": "IOB_X1Y178", + "ilogic_loc": "ILOGIC_X1Y178", + "ologic_loc": "OLOGIC_X1Y178", + "idelay_loc": "IDELAY_X1Y178", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[422]", + "owire": "do_buf[422]", + "iwire": "di_buf[422]", + "twire": "t[422]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y187", + "site": "IOB_X1Y179", + "ilogic_loc": "ILOGIC_X1Y179", + "ologic_loc": "OLOGIC_X1Y179", + "idelay_loc": "IDELAY_X1Y179", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[423]", + "owire": "do_buf[423]", + "iwire": "di_buf[423]", + "twire": "t[423]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y179),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 2, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y179),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y187", + "site": "IOB_X1Y180", + "ilogic_loc": "ILOGIC_X1Y180", + "ologic_loc": "OLOGIC_X1Y180", + "idelay_loc": "IDELAY_X1Y180", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[424]", + "owire": "do_buf[424]", + "iwire": "di_buf[424]", + "twire": "t[424]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y189", + "site": "IOB_X1Y181", + "ilogic_loc": "ILOGIC_X1Y181", + "ologic_loc": "OLOGIC_X1Y181", + "idelay_loc": "IDELAY_X1Y181", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[425]", + "owire": "do_buf[425]", + "iwire": "di_buf[425]", + "twire": "t[425]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y181),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y189", + "site": "IOB_X1Y182", + "ilogic_loc": "ILOGIC_X1Y182", + "ologic_loc": "OLOGIC_X1Y182", + "idelay_loc": "IDELAY_X1Y182", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[426]", + "owire": "do_buf[426]", + "iwire": "di_buf[426]", + "twire": "t[426]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y191", + "site": "IOB_X1Y183", + "ilogic_loc": "ILOGIC_X1Y183", + "ologic_loc": "OLOGIC_X1Y183", + "idelay_loc": "IDELAY_X1Y183", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[427]", + "owire": "do_buf[427]", + "iwire": "di_buf[427]", + "twire": "t[427]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y191", + "site": "IOB_X1Y184", + "ilogic_loc": "ILOGIC_X1Y184", + "ologic_loc": "OLOGIC_X1Y184", + "idelay_loc": "IDELAY_X1Y184", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[428]", + "owire": "do_buf[428]", + "iwire": "di_buf[428]", + "twire": "t[428]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y184),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y184),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y193", + "site": "IOB_X1Y185", + "ilogic_loc": "ILOGIC_X1Y185", + "ologic_loc": "OLOGIC_X1Y185", + "idelay_loc": "IDELAY_X1Y185", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[429]", + "owire": "do_buf[429]", + "iwire": "di_buf[429]", + "twire": "t[429]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y193", + "site": "IOB_X1Y186", + "ilogic_loc": "ILOGIC_X1Y186", + "ologic_loc": "OLOGIC_X1Y186", + "idelay_loc": "IDELAY_X1Y186", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[430]", + "owire": "do_buf[430]", + "iwire": "di_buf[430]", + "twire": "t[430]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y186),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y195", + "site": "IOB_X1Y187", + "ilogic_loc": "ILOGIC_X1Y187", + "ologic_loc": "OLOGIC_X1Y187", + "idelay_loc": "IDELAY_X1Y187", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[431]", + "owire": "do_buf[431]", + "iwire": "di_buf[431]", + "twire": "t[431]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y187),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y195", + "site": "IOB_X1Y188", + "ilogic_loc": "ILOGIC_X1Y188", + "ologic_loc": "OLOGIC_X1Y188", + "idelay_loc": "IDELAY_X1Y188", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[432]", + "owire": "do_buf[432]", + "iwire": "di_buf[432]", + "twire": "t[432]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y188),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y188),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y197", + "site": "IOB_X1Y189", + "ilogic_loc": "ILOGIC_X1Y189", + "ologic_loc": "OLOGIC_X1Y189", + "idelay_loc": "IDELAY_X1Y189", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[433]", + "owire": "do_buf[433]", + "iwire": "di_buf[433]", + "twire": "t[433]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y197", + "site": "IOB_X1Y190", + "ilogic_loc": "ILOGIC_X1Y190", + "ologic_loc": "OLOGIC_X1Y190", + "idelay_loc": "IDELAY_X1Y190", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[434]", + "owire": "do_buf[434]", + "iwire": "di_buf[434]", + "twire": "t[434]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y199", + "site": "IOB_X1Y191", + "ilogic_loc": "ILOGIC_X1Y191", + "ologic_loc": "OLOGIC_X1Y191", + "idelay_loc": "IDELAY_X1Y191", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[435]", + "owire": "do_buf[435]", + "iwire": "di_buf[435]", + "twire": "t[435]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y191),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y191),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y199", + "site": "IOB_X1Y192", + "ilogic_loc": "ILOGIC_X1Y192", + "ologic_loc": "OLOGIC_X1Y192", + "idelay_loc": "IDELAY_X1Y192", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[436]", + "owire": "do_buf[436]", + "iwire": "di_buf[436]", + "twire": "t[436]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y192),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y2", + "site": "IOB_X1Y1", + "ilogic_loc": "ILOGIC_X1Y1", + "ologic_loc": "OLOGIC_X1Y1", + "idelay_loc": "IDELAY_X1Y1", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[437]", + "owire": "do_buf[437]", + "iwire": "di_buf[437]", + "twire": "t[437]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y1),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 3, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y1),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y2", + "site": "IOB_X1Y2", + "ilogic_loc": "ILOGIC_X1Y2", + "ologic_loc": "OLOGIC_X1Y2", + "idelay_loc": "IDELAY_X1Y2", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[438]", + "owire": "do_buf[438]", + "iwire": "di_buf[438]", + "twire": "t[438]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y20", + "site": "IOB_X1Y19", + "ilogic_loc": "ILOGIC_X1Y19", + "ologic_loc": "OLOGIC_X1Y19", + "idelay_loc": "IDELAY_X1Y19", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[439]", + "owire": "do_buf[439]", + "iwire": "di_buf[439]", + "twire": "t[439]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y19),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y20", + "site": "IOB_X1Y20", + "ilogic_loc": "ILOGIC_X1Y20", + "ologic_loc": "OLOGIC_X1Y20", + "idelay_loc": "IDELAY_X1Y20", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[440]", + "owire": "do_buf[440]", + "iwire": "di_buf[440]", + "twire": "t[440]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 2, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 2, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y20),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y201", + "site": "IOB_X1Y193", + "ilogic_loc": "ILOGIC_X1Y193", + "ologic_loc": "OLOGIC_X1Y193", + "idelay_loc": "IDELAY_X1Y193", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[441]", + "owire": "do_buf[441]", + "iwire": "di_buf[441]", + "twire": "t[441]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y201", + "site": "IOB_X1Y194", + "ilogic_loc": "ILOGIC_X1Y194", + "ologic_loc": "OLOGIC_X1Y194", + "idelay_loc": "IDELAY_X1Y194", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[442]", + "owire": "do_buf[442]", + "iwire": "di_buf[442]", + "twire": "t[442]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y203", + "site": "IOB_X1Y195", + "ilogic_loc": "ILOGIC_X1Y195", + "ologic_loc": "OLOGIC_X1Y195", + "idelay_loc": "IDELAY_X1Y195", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[443]", + "owire": "do_buf[443]", + "iwire": "di_buf[443]", + "twire": "t[443]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y203", + "site": "IOB_X1Y196", + "ilogic_loc": "ILOGIC_X1Y196", + "ologic_loc": "OLOGIC_X1Y196", + "idelay_loc": "IDELAY_X1Y196", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[444]", + "owire": "do_buf[444]", + "iwire": "di_buf[444]", + "twire": "t[444]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y205", + "site": "IOB_X1Y197", + "ilogic_loc": "ILOGIC_X1Y197", + "ologic_loc": "OLOGIC_X1Y197", + "idelay_loc": "IDELAY_X1Y197", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[445]", + "owire": "do_buf[445]", + "iwire": "di_buf[445]", + "twire": "t[445]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y197),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y197),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y205", + "site": "IOB_X1Y198", + "ilogic_loc": "ILOGIC_X1Y198", + "ologic_loc": "OLOGIC_X1Y198", + "idelay_loc": "IDELAY_X1Y198", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[446]", + "owire": "do_buf[446]", + "iwire": "di_buf[446]", + "twire": "t[446]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 5, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y198),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y210", + "site": "IOB_X1Y201", + "ilogic_loc": "ILOGIC_X1Y201", + "ologic_loc": "OLOGIC_X1Y201", + "idelay_loc": "IDELAY_X1Y201", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[447]", + "owire": "do_buf[447]", + "iwire": "di_buf[447]", + "twire": "t[447]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y201),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y201),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y210", + "site": "IOB_X1Y202", + "ilogic_loc": "ILOGIC_X1Y202", + "ologic_loc": "OLOGIC_X1Y202", + "idelay_loc": "IDELAY_X1Y202", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[448]", + "owire": "do_buf[448]", + "iwire": "di_buf[448]", + "twire": "t[448]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y202),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y212", + "site": "IOB_X1Y203", + "ilogic_loc": "ILOGIC_X1Y203", + "ologic_loc": "OLOGIC_X1Y203", + "idelay_loc": "IDELAY_X1Y203", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[449]", + "owire": "do_buf[449]", + "iwire": "di_buf[449]", + "twire": "t[449]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y203),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y203),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y212", + "site": "IOB_X1Y204", + "ilogic_loc": "ILOGIC_X1Y204", + "ologic_loc": "OLOGIC_X1Y204", + "idelay_loc": "IDELAY_X1Y204", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[450]", + "owire": "do_buf[450]", + "iwire": "di_buf[450]", + "twire": "t[450]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y214", + "site": "IOB_X1Y205", + "ilogic_loc": "ILOGIC_X1Y205", + "ologic_loc": "OLOGIC_X1Y205", + "idelay_loc": "IDELAY_X1Y205", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[451]", + "owire": "do_buf[451]", + "iwire": "di_buf[451]", + "twire": "t[451]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y205),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y214", + "site": "IOB_X1Y206", + "ilogic_loc": "ILOGIC_X1Y206", + "ologic_loc": "OLOGIC_X1Y206", + "idelay_loc": "IDELAY_X1Y206", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[452]", + "owire": "do_buf[452]", + "iwire": "di_buf[452]", + "twire": "t[452]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y206),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y216", + "site": "IOB_X1Y207", + "ilogic_loc": "ILOGIC_X1Y207", + "ologic_loc": "OLOGIC_X1Y207", + "idelay_loc": "IDELAY_X1Y207", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[453]", + "owire": "do_buf[453]", + "iwire": "di_buf[453]", + "twire": "t[453]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 5, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y216", + "site": "IOB_X1Y208", + "ilogic_loc": "ILOGIC_X1Y208", + "ologic_loc": "OLOGIC_X1Y208", + "idelay_loc": "IDELAY_X1Y208", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[454]", + "owire": "do_buf[454]", + "iwire": "di_buf[454]", + "twire": "t[454]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y218", + "site": "IOB_X1Y209", + "ilogic_loc": "ILOGIC_X1Y209", + "ologic_loc": "OLOGIC_X1Y209", + "idelay_loc": "IDELAY_X1Y209", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[455]", + "owire": "do_buf[455]", + "iwire": "di_buf[455]", + "twire": "t[455]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y209),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y218", + "site": "IOB_X1Y210", + "ilogic_loc": "ILOGIC_X1Y210", + "ologic_loc": "OLOGIC_X1Y210", + "idelay_loc": "IDELAY_X1Y210", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[456]", + "owire": "do_buf[456]", + "iwire": "di_buf[456]", + "twire": "t[456]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y210),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y22", + "site": "IOB_X1Y21", + "ilogic_loc": "ILOGIC_X1Y21", + "ologic_loc": "OLOGIC_X1Y21", + "idelay_loc": "IDELAY_X1Y21", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[457]", + "owire": "do_buf[457]", + "iwire": "di_buf[457]", + "twire": "t[457]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y22", + "site": "IOB_X1Y22", + "ilogic_loc": "ILOGIC_X1Y22", + "ologic_loc": "OLOGIC_X1Y22", + "idelay_loc": "IDELAY_X1Y22", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[458]", + "owire": "do_buf[458]", + "iwire": "di_buf[458]", + "twire": "t[458]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y220", + "site": "IOB_X1Y211", + "ilogic_loc": "ILOGIC_X1Y211", + "ologic_loc": "OLOGIC_X1Y211", + "idelay_loc": "IDELAY_X1Y211", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[459]", + "owire": "do_buf[459]", + "iwire": "di_buf[459]", + "twire": "t[459]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y220", + "site": "IOB_X1Y212", + "ilogic_loc": "ILOGIC_X1Y212", + "ologic_loc": "OLOGIC_X1Y212", + "idelay_loc": "IDELAY_X1Y212", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[460]", + "owire": "do_buf[460]", + "iwire": "di_buf[460]", + "twire": "t[460]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y222", + "site": "IOB_X1Y213", + "ilogic_loc": "ILOGIC_X1Y213", + "ologic_loc": "OLOGIC_X1Y213", + "idelay_loc": "IDELAY_X1Y213", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[461]", + "owire": "do_buf[461]", + "iwire": "di_buf[461]", + "twire": "t[461]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y213),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y222", + "site": "IOB_X1Y214", + "ilogic_loc": "ILOGIC_X1Y214", + "ologic_loc": "OLOGIC_X1Y214", + "idelay_loc": "IDELAY_X1Y214", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[462]", + "owire": "do_buf[462]", + "iwire": "di_buf[462]", + "twire": "t[462]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y224", + "site": "IOB_X1Y215", + "ilogic_loc": "ILOGIC_X1Y215", + "ologic_loc": "OLOGIC_X1Y215", + "idelay_loc": "IDELAY_X1Y215", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[463]", + "owire": "do_buf[463]", + "iwire": "di_buf[463]", + "twire": "t[463]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y215),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y224", + "site": "IOB_X1Y216", + "ilogic_loc": "ILOGIC_X1Y216", + "ologic_loc": "OLOGIC_X1Y216", + "idelay_loc": "IDELAY_X1Y216", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[464]", + "owire": "do_buf[464]", + "iwire": "di_buf[464]", + "twire": "t[464]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 3, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y226", + "site": "IOB_X1Y217", + "ilogic_loc": "ILOGIC_X1Y217", + "ologic_loc": "OLOGIC_X1Y217", + "idelay_loc": "IDELAY_X1Y217", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[465]", + "owire": "do_buf[465]", + "iwire": "di_buf[465]", + "twire": "t[465]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y226", + "site": "IOB_X1Y218", + "ilogic_loc": "ILOGIC_X1Y218", + "ologic_loc": "OLOGIC_X1Y218", + "idelay_loc": "IDELAY_X1Y218", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[466]", + "owire": "do_buf[466]", + "iwire": "di_buf[466]", + "twire": "t[466]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y218),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y228", + "site": "IOB_X1Y219", + "ilogic_loc": "ILOGIC_X1Y219", + "ologic_loc": "OLOGIC_X1Y219", + "idelay_loc": "IDELAY_X1Y219", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[467]", + "owire": "do_buf[467]", + "iwire": "di_buf[467]", + "twire": "t[467]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y228", + "site": "IOB_X1Y220", + "ilogic_loc": "ILOGIC_X1Y220", + "ologic_loc": "OLOGIC_X1Y220", + "idelay_loc": "IDELAY_X1Y220", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[468]", + "owire": "do_buf[468]", + "iwire": "di_buf[468]", + "twire": "t[468]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y220),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y220),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y230", + "site": "IOB_X1Y221", + "ilogic_loc": "ILOGIC_X1Y221", + "ologic_loc": "OLOGIC_X1Y221", + "idelay_loc": "IDELAY_X1Y221", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[469]", + "owire": "do_buf[469]", + "iwire": "di_buf[469]", + "twire": "t[469]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y230", + "site": "IOB_X1Y222", + "ilogic_loc": "ILOGIC_X1Y222", + "ologic_loc": "OLOGIC_X1Y222", + "idelay_loc": "IDELAY_X1Y222", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[470]", + "owire": "do_buf[470]", + "iwire": "di_buf[470]", + "twire": "t[470]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 3, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y222),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y232", + "site": "IOB_X1Y223", + "ilogic_loc": "ILOGIC_X1Y223", + "ologic_loc": "OLOGIC_X1Y223", + "idelay_loc": "IDELAY_X1Y223", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[471]", + "owire": "do_buf[471]", + "iwire": "di_buf[471]", + "twire": "t[471]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y232", + "site": "IOB_X1Y224", + "ilogic_loc": "ILOGIC_X1Y224", + "ologic_loc": "OLOGIC_X1Y224", + "idelay_loc": "IDELAY_X1Y224", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[472]", + "owire": "do_buf[472]", + "iwire": "di_buf[472]", + "twire": "t[472]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y235", + "site": "IOB_X1Y225", + "ilogic_loc": "ILOGIC_X1Y225", + "ologic_loc": "OLOGIC_X1Y225", + "idelay_loc": "IDELAY_X1Y225", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[473]", + "owire": "do_buf[473]", + "iwire": "di_buf[473]", + "twire": "t[473]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y225),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y225),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y235", + "site": "IOB_X1Y226", + "ilogic_loc": "ILOGIC_X1Y226", + "ologic_loc": "OLOGIC_X1Y226", + "idelay_loc": "IDELAY_X1Y226", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[474]", + "owire": "do_buf[474]", + "iwire": "di_buf[474]", + "twire": "t[474]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y237", + "site": "IOB_X1Y227", + "ilogic_loc": "ILOGIC_X1Y227", + "ologic_loc": "OLOGIC_X1Y227", + "idelay_loc": "IDELAY_X1Y227", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[475]", + "owire": "do_buf[475]", + "iwire": "di_buf[475]", + "twire": "t[475]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y237", + "site": "IOB_X1Y228", + "ilogic_loc": "ILOGIC_X1Y228", + "ologic_loc": "OLOGIC_X1Y228", + "idelay_loc": "IDELAY_X1Y228", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[476]", + "owire": "do_buf[476]", + "iwire": "di_buf[476]", + "twire": "t[476]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y239", + "site": "IOB_X1Y229", + "ilogic_loc": "ILOGIC_X1Y229", + "ologic_loc": "OLOGIC_X1Y229", + "idelay_loc": "IDELAY_X1Y229", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[477]", + "owire": "do_buf[477]", + "iwire": "di_buf[477]", + "twire": "t[477]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y239", + "site": "IOB_X1Y230", + "ilogic_loc": "ILOGIC_X1Y230", + "ologic_loc": "OLOGIC_X1Y230", + "idelay_loc": "IDELAY_X1Y230", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[478]", + "owire": "do_buf[478]", + "iwire": "di_buf[478]", + "twire": "t[478]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y230),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 2, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y230),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y24", + "site": "IOB_X1Y23", + "ilogic_loc": "ILOGIC_X1Y23", + "ologic_loc": "OLOGIC_X1Y23", + "idelay_loc": "IDELAY_X1Y23", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[479]", + "owire": "do_buf[479]", + "iwire": "di_buf[479]", + "twire": "t[479]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 5, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y23),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y23),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y24", + "site": "IOB_X1Y24", + "ilogic_loc": "ILOGIC_X1Y24", + "ologic_loc": "OLOGIC_X1Y24", + "idelay_loc": "IDELAY_X1Y24", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[480]", + "owire": "do_buf[480]", + "iwire": "di_buf[480]", + "twire": "t[480]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y241", + "site": "IOB_X1Y231", + "ilogic_loc": "ILOGIC_X1Y231", + "ologic_loc": "OLOGIC_X1Y231", + "idelay_loc": "IDELAY_X1Y231", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[481]", + "owire": "do_buf[481]", + "iwire": "di_buf[481]", + "twire": "t[481]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y241", + "site": "IOB_X1Y232", + "ilogic_loc": "ILOGIC_X1Y232", + "ologic_loc": "OLOGIC_X1Y232", + "idelay_loc": "IDELAY_X1Y232", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[482]", + "owire": "do_buf[482]", + "iwire": "di_buf[482]", + "twire": "t[482]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y243", + "site": "IOB_X1Y233", + "ilogic_loc": "ILOGIC_X1Y233", + "ologic_loc": "OLOGIC_X1Y233", + "idelay_loc": "IDELAY_X1Y233", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[483]", + "owire": "do_buf[483]", + "iwire": "di_buf[483]", + "twire": "t[483]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y233),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y233),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y243", + "site": "IOB_X1Y234", + "ilogic_loc": "ILOGIC_X1Y234", + "ologic_loc": "OLOGIC_X1Y234", + "idelay_loc": "IDELAY_X1Y234", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[484]", + "owire": "do_buf[484]", + "iwire": "di_buf[484]", + "twire": "t[484]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y245", + "site": "IOB_X1Y235", + "ilogic_loc": "ILOGIC_X1Y235", + "ologic_loc": "OLOGIC_X1Y235", + "idelay_loc": "IDELAY_X1Y235", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[485]", + "owire": "do_buf[485]", + "iwire": "di_buf[485]", + "twire": "t[485]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y235),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y235),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y245", + "site": "IOB_X1Y236", + "ilogic_loc": "ILOGIC_X1Y236", + "ologic_loc": "OLOGIC_X1Y236", + "idelay_loc": "IDELAY_X1Y236", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[486]", + "owire": "do_buf[486]", + "iwire": "di_buf[486]", + "twire": "t[486]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y247", + "site": "IOB_X1Y237", + "ilogic_loc": "ILOGIC_X1Y237", + "ologic_loc": "OLOGIC_X1Y237", + "idelay_loc": "IDELAY_X1Y237", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[487]", + "owire": "do_buf[487]", + "iwire": "di_buf[487]", + "twire": "t[487]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 2, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y237),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y247", + "site": "IOB_X1Y238", + "ilogic_loc": "ILOGIC_X1Y238", + "ologic_loc": "OLOGIC_X1Y238", + "idelay_loc": "IDELAY_X1Y238", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[488]", + "owire": "do_buf[488]", + "iwire": "di_buf[488]", + "twire": "t[488]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y249", + "site": "IOB_X1Y239", + "ilogic_loc": "ILOGIC_X1Y239", + "ologic_loc": "OLOGIC_X1Y239", + "idelay_loc": "IDELAY_X1Y239", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[489]", + "owire": "do_buf[489]", + "iwire": "di_buf[489]", + "twire": "t[489]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y249", + "site": "IOB_X1Y240", + "ilogic_loc": "ILOGIC_X1Y240", + "ologic_loc": "OLOGIC_X1Y240", + "idelay_loc": "IDELAY_X1Y240", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[490]", + "owire": "do_buf[490]", + "iwire": "di_buf[490]", + "twire": "t[490]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y240),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y240),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y251", + "site": "IOB_X1Y241", + "ilogic_loc": "ILOGIC_X1Y241", + "ologic_loc": "OLOGIC_X1Y241", + "idelay_loc": "IDELAY_X1Y241", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[491]", + "owire": "do_buf[491]", + "iwire": "di_buf[491]", + "twire": "t[491]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y251", + "site": "IOB_X1Y242", + "ilogic_loc": "ILOGIC_X1Y242", + "ologic_loc": "OLOGIC_X1Y242", + "idelay_loc": "IDELAY_X1Y242", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[492]", + "owire": "do_buf[492]", + "iwire": "di_buf[492]", + "twire": "t[492]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y242),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y242),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y253", + "site": "IOB_X1Y243", + "ilogic_loc": "ILOGIC_X1Y243", + "ologic_loc": "OLOGIC_X1Y243", + "idelay_loc": "IDELAY_X1Y243", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[493]", + "owire": "do_buf[493]", + "iwire": "di_buf[493]", + "twire": "t[493]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y253", + "site": "IOB_X1Y244", + "ilogic_loc": "ILOGIC_X1Y244", + "ologic_loc": "OLOGIC_X1Y244", + "idelay_loc": "IDELAY_X1Y244", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[494]", + "owire": "do_buf[494]", + "iwire": "di_buf[494]", + "twire": "t[494]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y244),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y244),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y255", + "site": "IOB_X1Y245", + "ilogic_loc": "ILOGIC_X1Y245", + "ologic_loc": "OLOGIC_X1Y245", + "idelay_loc": "IDELAY_X1Y245", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[495]", + "owire": "do_buf[495]", + "iwire": "di_buf[495]", + "twire": "t[495]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y255", + "site": "IOB_X1Y246", + "ilogic_loc": "ILOGIC_X1Y246", + "ologic_loc": "OLOGIC_X1Y246", + "idelay_loc": "IDELAY_X1Y246", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[496]", + "owire": "do_buf[496]", + "iwire": "di_buf[496]", + "twire": "t[496]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y246),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y246),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y257", + "site": "IOB_X1Y247", + "ilogic_loc": "ILOGIC_X1Y247", + "ologic_loc": "OLOGIC_X1Y247", + "idelay_loc": "IDELAY_X1Y247", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[497]", + "owire": "do_buf[497]", + "iwire": "di_buf[497]", + "twire": "t[497]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y247),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y247),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y257", + "site": "IOB_X1Y248", + "ilogic_loc": "ILOGIC_X1Y248", + "ologic_loc": "OLOGIC_X1Y248", + "idelay_loc": "IDELAY_X1Y248", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[498]", + "owire": "do_buf[498]", + "iwire": "di_buf[498]", + "twire": "t[498]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y262", + "site": "IOB_X1Y251", + "ilogic_loc": "ILOGIC_X1Y251", + "ologic_loc": "OLOGIC_X1Y251", + "idelay_loc": "IDELAY_X1Y251", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[499]", + "owire": "do_buf[499]", + "iwire": "di_buf[499]", + "twire": "t[499]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y262", + "site": "IOB_X1Y252", + "ilogic_loc": "ILOGIC_X1Y252", + "ologic_loc": "OLOGIC_X1Y252", + "idelay_loc": "IDELAY_X1Y252", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[500]", + "owire": "do_buf[500]", + "iwire": "di_buf[500]", + "twire": "t[500]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y252),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y252),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y264", + "site": "IOB_X1Y253", + "ilogic_loc": "ILOGIC_X1Y253", + "ologic_loc": "OLOGIC_X1Y253", + "idelay_loc": "IDELAY_X1Y253", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[501]", + "owire": "do_buf[501]", + "iwire": "di_buf[501]", + "twire": "t[501]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y264", + "site": "IOB_X1Y254", + "ilogic_loc": "ILOGIC_X1Y254", + "ologic_loc": "OLOGIC_X1Y254", + "idelay_loc": "IDELAY_X1Y254", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[502]", + "owire": "do_buf[502]", + "iwire": "di_buf[502]", + "twire": "t[502]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y254),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 7, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y254),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y266", + "site": "IOB_X1Y255", + "ilogic_loc": "ILOGIC_X1Y255", + "ologic_loc": "OLOGIC_X1Y255", + "idelay_loc": "IDELAY_X1Y255", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[503]", + "owire": "do_buf[503]", + "iwire": "di_buf[503]", + "twire": "t[503]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y255),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y266", + "site": "IOB_X1Y256", + "ilogic_loc": "ILOGIC_X1Y256", + "ologic_loc": "OLOGIC_X1Y256", + "idelay_loc": "IDELAY_X1Y256", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[504]", + "owire": "do_buf[504]", + "iwire": "di_buf[504]", + "twire": "t[504]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y256),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y256),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y268", + "site": "IOB_X1Y257", + "ilogic_loc": "ILOGIC_X1Y257", + "ologic_loc": "OLOGIC_X1Y257", + "idelay_loc": "IDELAY_X1Y257", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[505]", + "owire": "do_buf[505]", + "iwire": "di_buf[505]", + "twire": "t[505]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y257),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y257),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y268", + "site": "IOB_X1Y258", + "ilogic_loc": "ILOGIC_X1Y258", + "ologic_loc": "OLOGIC_X1Y258", + "idelay_loc": "IDELAY_X1Y258", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[506]", + "owire": "do_buf[506]", + "iwire": "di_buf[506]", + "twire": "t[506]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y258),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y27", + "site": "IOB_X1Y25", + "ilogic_loc": "ILOGIC_X1Y25", + "ologic_loc": "OLOGIC_X1Y25", + "idelay_loc": "IDELAY_X1Y25", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[507]", + "owire": "do_buf[507]", + "iwire": "di_buf[507]", + "twire": "t[507]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y27", + "site": "IOB_X1Y26", + "ilogic_loc": "ILOGIC_X1Y26", + "ologic_loc": "OLOGIC_X1Y26", + "idelay_loc": "IDELAY_X1Y26", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[508]", + "owire": "do_buf[508]", + "iwire": "di_buf[508]", + "twire": "t[508]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y270", + "site": "IOB_X1Y259", + "ilogic_loc": "ILOGIC_X1Y259", + "ologic_loc": "OLOGIC_X1Y259", + "idelay_loc": "IDELAY_X1Y259", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[509]", + "owire": "do_buf[509]", + "iwire": "di_buf[509]", + "twire": "t[509]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y270", + "site": "IOB_X1Y260", + "ilogic_loc": "ILOGIC_X1Y260", + "ologic_loc": "OLOGIC_X1Y260", + "idelay_loc": "IDELAY_X1Y260", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[510]", + "owire": "do_buf[510]", + "iwire": "di_buf[510]", + "twire": "t[510]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y260),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y260),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y272", + "site": "IOB_X1Y261", + "ilogic_loc": "ILOGIC_X1Y261", + "ologic_loc": "OLOGIC_X1Y261", + "idelay_loc": "IDELAY_X1Y261", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[511]", + "owire": "do_buf[511]", + "iwire": "di_buf[511]", + "twire": "t[511]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y272", + "site": "IOB_X1Y262", + "ilogic_loc": "ILOGIC_X1Y262", + "ologic_loc": "OLOGIC_X1Y262", + "idelay_loc": "IDELAY_X1Y262", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[512]", + "owire": "do_buf[512]", + "iwire": "di_buf[512]", + "twire": "t[512]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y274", + "site": "IOB_X1Y263", + "ilogic_loc": "ILOGIC_X1Y263", + "ologic_loc": "OLOGIC_X1Y263", + "idelay_loc": "IDELAY_X1Y263", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[513]", + "owire": "do_buf[513]", + "iwire": "di_buf[513]", + "twire": "t[513]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y263),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y263),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y274", + "site": "IOB_X1Y264", + "ilogic_loc": "ILOGIC_X1Y264", + "ologic_loc": "OLOGIC_X1Y264", + "idelay_loc": "IDELAY_X1Y264", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[514]", + "owire": "do_buf[514]", + "iwire": "di_buf[514]", + "twire": "t[514]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y276", + "site": "IOB_X1Y265", + "ilogic_loc": "ILOGIC_X1Y265", + "ologic_loc": "OLOGIC_X1Y265", + "idelay_loc": "IDELAY_X1Y265", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[515]", + "owire": "do_buf[515]", + "iwire": "di_buf[515]", + "twire": "t[515]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y276", + "site": "IOB_X1Y266", + "ilogic_loc": "ILOGIC_X1Y266", + "ologic_loc": "OLOGIC_X1Y266", + "idelay_loc": "IDELAY_X1Y266", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[516]", + "owire": "do_buf[516]", + "iwire": "di_buf[516]", + "twire": "t[516]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 5, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y266),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y278", + "site": "IOB_X1Y267", + "ilogic_loc": "ILOGIC_X1Y267", + "ologic_loc": "OLOGIC_X1Y267", + "idelay_loc": "IDELAY_X1Y267", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[517]", + "owire": "do_buf[517]", + "iwire": "di_buf[517]", + "twire": "t[517]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y267),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y267),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y278", + "site": "IOB_X1Y268", + "ilogic_loc": "ILOGIC_X1Y268", + "ologic_loc": "OLOGIC_X1Y268", + "idelay_loc": "IDELAY_X1Y268", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[518]", + "owire": "do_buf[518]", + "iwire": "di_buf[518]", + "twire": "t[518]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y280", + "site": "IOB_X1Y269", + "ilogic_loc": "ILOGIC_X1Y269", + "ologic_loc": "OLOGIC_X1Y269", + "idelay_loc": "IDELAY_X1Y269", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[519]", + "owire": "do_buf[519]", + "iwire": "di_buf[519]", + "twire": "t[519]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 5, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y269),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y280", + "site": "IOB_X1Y270", + "ilogic_loc": "ILOGIC_X1Y270", + "ologic_loc": "OLOGIC_X1Y270", + "idelay_loc": "IDELAY_X1Y270", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[520]", + "owire": "do_buf[520]", + "iwire": "di_buf[520]", + "twire": "t[520]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y282", + "site": "IOB_X1Y271", + "ilogic_loc": "ILOGIC_X1Y271", + "ologic_loc": "OLOGIC_X1Y271", + "idelay_loc": "IDELAY_X1Y271", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[521]", + "owire": "do_buf[521]", + "iwire": "di_buf[521]", + "twire": "t[521]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y282", + "site": "IOB_X1Y272", + "ilogic_loc": "ILOGIC_X1Y272", + "ologic_loc": "OLOGIC_X1Y272", + "idelay_loc": "IDELAY_X1Y272", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[522]", + "owire": "do_buf[522]", + "iwire": "di_buf[522]", + "twire": "t[522]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y272),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y284", + "site": "IOB_X1Y273", + "ilogic_loc": "ILOGIC_X1Y273", + "ologic_loc": "OLOGIC_X1Y273", + "idelay_loc": "IDELAY_X1Y273", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[523]", + "owire": "do_buf[523]", + "iwire": "di_buf[523]", + "twire": "t[523]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y273),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y284", + "site": "IOB_X1Y274", + "ilogic_loc": "ILOGIC_X1Y274", + "ologic_loc": "OLOGIC_X1Y274", + "idelay_loc": "IDELAY_X1Y274", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[524]", + "owire": "do_buf[524]", + "iwire": "di_buf[524]", + "twire": "t[524]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 7, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y274),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 3, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y274),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y287", + "site": "IOB_X1Y275", + "ilogic_loc": "ILOGIC_X1Y275", + "ologic_loc": "OLOGIC_X1Y275", + "idelay_loc": "IDELAY_X1Y275", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[525]", + "owire": "do_buf[525]", + "iwire": "di_buf[525]", + "twire": "t[525]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y287", + "site": "IOB_X1Y276", + "ilogic_loc": "ILOGIC_X1Y276", + "ologic_loc": "OLOGIC_X1Y276", + "idelay_loc": "IDELAY_X1Y276", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[526]", + "owire": "do_buf[526]", + "iwire": "di_buf[526]", + "twire": "t[526]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y276),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 2, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y276),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y289", + "site": "IOB_X1Y277", + "ilogic_loc": "ILOGIC_X1Y277", + "ologic_loc": "OLOGIC_X1Y277", + "idelay_loc": "IDELAY_X1Y277", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[527]", + "owire": "do_buf[527]", + "iwire": "di_buf[527]", + "twire": "t[527]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 5, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y277),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y277),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y289", + "site": "IOB_X1Y278", + "ilogic_loc": "ILOGIC_X1Y278", + "ologic_loc": "OLOGIC_X1Y278", + "idelay_loc": "IDELAY_X1Y278", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[528]", + "owire": "do_buf[528]", + "iwire": "di_buf[528]", + "twire": "t[528]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y29", + "site": "IOB_X1Y27", + "ilogic_loc": "ILOGIC_X1Y27", + "ologic_loc": "OLOGIC_X1Y27", + "idelay_loc": "IDELAY_X1Y27", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[529]", + "owire": "do_buf[529]", + "iwire": "di_buf[529]", + "twire": "t[529]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y29", + "site": "IOB_X1Y28", + "ilogic_loc": "ILOGIC_X1Y28", + "ologic_loc": "OLOGIC_X1Y28", + "idelay_loc": "IDELAY_X1Y28", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[530]", + "owire": "do_buf[530]", + "iwire": "di_buf[530]", + "twire": "t[530]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y291", + "site": "IOB_X1Y279", + "ilogic_loc": "ILOGIC_X1Y279", + "ologic_loc": "OLOGIC_X1Y279", + "idelay_loc": "IDELAY_X1Y279", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[531]", + "owire": "do_buf[531]", + "iwire": "di_buf[531]", + "twire": "t[531]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y291", + "site": "IOB_X1Y280", + "ilogic_loc": "ILOGIC_X1Y280", + "ologic_loc": "OLOGIC_X1Y280", + "idelay_loc": "IDELAY_X1Y280", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[532]", + "owire": "do_buf[532]", + "iwire": "di_buf[532]", + "twire": "t[532]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y293", + "site": "IOB_X1Y281", + "ilogic_loc": "ILOGIC_X1Y281", + "ologic_loc": "OLOGIC_X1Y281", + "idelay_loc": "IDELAY_X1Y281", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[533]", + "owire": "do_buf[533]", + "iwire": "di_buf[533]", + "twire": "t[533]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y293", + "site": "IOB_X1Y282", + "ilogic_loc": "ILOGIC_X1Y282", + "ologic_loc": "OLOGIC_X1Y282", + "idelay_loc": "IDELAY_X1Y282", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[534]", + "owire": "do_buf[534]", + "iwire": "di_buf[534]", + "twire": "t[534]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y295", + "site": "IOB_X1Y283", + "ilogic_loc": "ILOGIC_X1Y283", + "ologic_loc": "OLOGIC_X1Y283", + "idelay_loc": "IDELAY_X1Y283", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[535]", + "owire": "do_buf[535]", + "iwire": "di_buf[535]", + "twire": "t[535]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y295", + "site": "IOB_X1Y284", + "ilogic_loc": "ILOGIC_X1Y284", + "ologic_loc": "OLOGIC_X1Y284", + "idelay_loc": "IDELAY_X1Y284", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[536]", + "owire": "do_buf[536]", + "iwire": "di_buf[536]", + "twire": "t[536]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y297", + "site": "IOB_X1Y285", + "ilogic_loc": "ILOGIC_X1Y285", + "ologic_loc": "OLOGIC_X1Y285", + "idelay_loc": "IDELAY_X1Y285", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[537]", + "owire": "do_buf[537]", + "iwire": "di_buf[537]", + "twire": "t[537]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y297", + "site": "IOB_X1Y286", + "ilogic_loc": "ILOGIC_X1Y286", + "ologic_loc": "OLOGIC_X1Y286", + "idelay_loc": "IDELAY_X1Y286", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[538]", + "owire": "do_buf[538]", + "iwire": "di_buf[538]", + "twire": "t[538]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y299", + "site": "IOB_X1Y287", + "ilogic_loc": "ILOGIC_X1Y287", + "ologic_loc": "OLOGIC_X1Y287", + "idelay_loc": "IDELAY_X1Y287", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[539]", + "owire": "do_buf[539]", + "iwire": "di_buf[539]", + "twire": "t[539]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y299", + "site": "IOB_X1Y288", + "ilogic_loc": "ILOGIC_X1Y288", + "ologic_loc": "OLOGIC_X1Y288", + "idelay_loc": "IDELAY_X1Y288", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[540]", + "owire": "do_buf[540]", + "iwire": "di_buf[540]", + "twire": "t[540]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y288),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y301", + "site": "IOB_X1Y289", + "ilogic_loc": "ILOGIC_X1Y289", + "ologic_loc": "OLOGIC_X1Y289", + "idelay_loc": "IDELAY_X1Y289", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[541]", + "owire": "do_buf[541]", + "iwire": "di_buf[541]", + "twire": "t[541]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y301", + "site": "IOB_X1Y290", + "ilogic_loc": "ILOGIC_X1Y290", + "ologic_loc": "OLOGIC_X1Y290", + "idelay_loc": "IDELAY_X1Y290", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[542]", + "owire": "do_buf[542]", + "iwire": "di_buf[542]", + "twire": "t[542]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y290),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y303", + "site": "IOB_X1Y291", + "ilogic_loc": "ILOGIC_X1Y291", + "ologic_loc": "OLOGIC_X1Y291", + "idelay_loc": "IDELAY_X1Y291", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[543]", + "owire": "do_buf[543]", + "iwire": "di_buf[543]", + "twire": "t[543]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y291),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y303", + "site": "IOB_X1Y292", + "ilogic_loc": "ILOGIC_X1Y292", + "ologic_loc": "OLOGIC_X1Y292", + "idelay_loc": "IDELAY_X1Y292", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[544]", + "owire": "do_buf[544]", + "iwire": "di_buf[544]", + "twire": "t[544]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 5, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y305", + "site": "IOB_X1Y293", + "ilogic_loc": "ILOGIC_X1Y293", + "ologic_loc": "OLOGIC_X1Y293", + "idelay_loc": "IDELAY_X1Y293", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[545]", + "owire": "do_buf[545]", + "iwire": "di_buf[545]", + "twire": "t[545]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y293),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 5, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y293),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y305", + "site": "IOB_X1Y294", + "ilogic_loc": "ILOGIC_X1Y294", + "ologic_loc": "OLOGIC_X1Y294", + "idelay_loc": "IDELAY_X1Y294", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[546]", + "owire": "do_buf[546]", + "iwire": "di_buf[546]", + "twire": "t[546]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y307", + "site": "IOB_X1Y295", + "ilogic_loc": "ILOGIC_X1Y295", + "ologic_loc": "OLOGIC_X1Y295", + "idelay_loc": "IDELAY_X1Y295", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[547]", + "owire": "do_buf[547]", + "iwire": "di_buf[547]", + "twire": "t[547]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y295),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y307", + "site": "IOB_X1Y296", + "ilogic_loc": "ILOGIC_X1Y296", + "ologic_loc": "OLOGIC_X1Y296", + "idelay_loc": "IDELAY_X1Y296", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[548]", + "owire": "do_buf[548]", + "iwire": "di_buf[548]", + "twire": "t[548]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y309", + "site": "IOB_X1Y297", + "ilogic_loc": "ILOGIC_X1Y297", + "ologic_loc": "OLOGIC_X1Y297", + "idelay_loc": "IDELAY_X1Y297", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[549]", + "owire": "do_buf[549]", + "iwire": "di_buf[549]", + "twire": "t[549]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y297),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y297),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y309", + "site": "IOB_X1Y298", + "ilogic_loc": "ILOGIC_X1Y298", + "ologic_loc": "OLOGIC_X1Y298", + "idelay_loc": "IDELAY_X1Y298", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[550]", + "owire": "do_buf[550]", + "iwire": "di_buf[550]", + "twire": "t[550]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y298),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y31", + "site": "IOB_X1Y29", + "ilogic_loc": "ILOGIC_X1Y29", + "ologic_loc": "OLOGIC_X1Y29", + "idelay_loc": "IDELAY_X1Y29", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[551]", + "owire": "do_buf[551]", + "iwire": "di_buf[551]", + "twire": "t[551]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y31", + "site": "IOB_X1Y30", + "ilogic_loc": "ILOGIC_X1Y30", + "ologic_loc": "OLOGIC_X1Y30", + "idelay_loc": "IDELAY_X1Y30", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[552]", + "owire": "do_buf[552]", + "iwire": "di_buf[552]", + "twire": "t[552]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 2, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y314", + "site": "IOB_X1Y301", + "ilogic_loc": "ILOGIC_X1Y301", + "ologic_loc": "OLOGIC_X1Y301", + "idelay_loc": "IDELAY_X1Y301", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[553]", + "owire": "do_buf[553]", + "iwire": "di_buf[553]", + "twire": "t[553]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y314", + "site": "IOB_X1Y302", + "ilogic_loc": "ILOGIC_X1Y302", + "ologic_loc": "OLOGIC_X1Y302", + "idelay_loc": "IDELAY_X1Y302", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[554]", + "owire": "do_buf[554]", + "iwire": "di_buf[554]", + "twire": "t[554]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y302),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y302),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y316", + "site": "IOB_X1Y303", + "ilogic_loc": "ILOGIC_X1Y303", + "ologic_loc": "OLOGIC_X1Y303", + "idelay_loc": "IDELAY_X1Y303", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[555]", + "owire": "do_buf[555]", + "iwire": "di_buf[555]", + "twire": "t[555]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y316", + "site": "IOB_X1Y304", + "ilogic_loc": "ILOGIC_X1Y304", + "ologic_loc": "OLOGIC_X1Y304", + "idelay_loc": "IDELAY_X1Y304", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[556]", + "owire": "do_buf[556]", + "iwire": "di_buf[556]", + "twire": "t[556]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y318", + "site": "IOB_X1Y305", + "ilogic_loc": "ILOGIC_X1Y305", + "ologic_loc": "OLOGIC_X1Y305", + "idelay_loc": "IDELAY_X1Y305", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[557]", + "owire": "do_buf[557]", + "iwire": "di_buf[557]", + "twire": "t[557]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y318", + "site": "IOB_X1Y306", + "ilogic_loc": "ILOGIC_X1Y306", + "ologic_loc": "OLOGIC_X1Y306", + "idelay_loc": "IDELAY_X1Y306", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[558]", + "owire": "do_buf[558]", + "iwire": "di_buf[558]", + "twire": "t[558]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y320", + "site": "IOB_X1Y307", + "ilogic_loc": "ILOGIC_X1Y307", + "ologic_loc": "OLOGIC_X1Y307", + "idelay_loc": "IDELAY_X1Y307", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[559]", + "owire": "do_buf[559]", + "iwire": "di_buf[559]", + "twire": "t[559]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 5, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y307),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y307),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y320", + "site": "IOB_X1Y308", + "ilogic_loc": "ILOGIC_X1Y308", + "ologic_loc": "OLOGIC_X1Y308", + "idelay_loc": "IDELAY_X1Y308", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[560]", + "owire": "do_buf[560]", + "iwire": "di_buf[560]", + "twire": "t[560]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y322", + "site": "IOB_X1Y309", + "ilogic_loc": "ILOGIC_X1Y309", + "ologic_loc": "OLOGIC_X1Y309", + "idelay_loc": "IDELAY_X1Y309", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[561]", + "owire": "do_buf[561]", + "iwire": "di_buf[561]", + "twire": "t[561]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y309),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y322", + "site": "IOB_X1Y310", + "ilogic_loc": "ILOGIC_X1Y310", + "ologic_loc": "OLOGIC_X1Y310", + "idelay_loc": "IDELAY_X1Y310", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[562]", + "owire": "do_buf[562]", + "iwire": "di_buf[562]", + "twire": "t[562]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y324", + "site": "IOB_X1Y311", + "ilogic_loc": "ILOGIC_X1Y311", + "ologic_loc": "OLOGIC_X1Y311", + "idelay_loc": "IDELAY_X1Y311", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[563]", + "owire": "do_buf[563]", + "iwire": "di_buf[563]", + "twire": "t[563]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y324", + "site": "IOB_X1Y312", + "ilogic_loc": "ILOGIC_X1Y312", + "ologic_loc": "OLOGIC_X1Y312", + "idelay_loc": "IDELAY_X1Y312", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[564]", + "owire": "do_buf[564]", + "iwire": "di_buf[564]", + "twire": "t[564]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y312),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y312),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y326", + "site": "IOB_X1Y313", + "ilogic_loc": "ILOGIC_X1Y313", + "ologic_loc": "OLOGIC_X1Y313", + "idelay_loc": "IDELAY_X1Y313", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[565]", + "owire": "do_buf[565]", + "iwire": "di_buf[565]", + "twire": "t[565]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y326", + "site": "IOB_X1Y314", + "ilogic_loc": "ILOGIC_X1Y314", + "ologic_loc": "OLOGIC_X1Y314", + "idelay_loc": "IDELAY_X1Y314", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[566]", + "owire": "do_buf[566]", + "iwire": "di_buf[566]", + "twire": "t[566]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y328", + "site": "IOB_X1Y315", + "ilogic_loc": "ILOGIC_X1Y315", + "ologic_loc": "OLOGIC_X1Y315", + "idelay_loc": "IDELAY_X1Y315", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[567]", + "owire": "do_buf[567]", + "iwire": "di_buf[567]", + "twire": "t[567]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y328", + "site": "IOB_X1Y316", + "ilogic_loc": "ILOGIC_X1Y316", + "ologic_loc": "OLOGIC_X1Y316", + "idelay_loc": "IDELAY_X1Y316", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[568]", + "owire": "do_buf[568]", + "iwire": "di_buf[568]", + "twire": "t[568]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y33", + "site": "IOB_X1Y31", + "ilogic_loc": "ILOGIC_X1Y31", + "ologic_loc": "OLOGIC_X1Y31", + "idelay_loc": "IDELAY_X1Y31", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[569]", + "owire": "do_buf[569]", + "iwire": "di_buf[569]", + "twire": "t[569]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y33", + "site": "IOB_X1Y32", + "ilogic_loc": "ILOGIC_X1Y32", + "ologic_loc": "OLOGIC_X1Y32", + "idelay_loc": "IDELAY_X1Y32", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[570]", + "owire": "do_buf[570]", + "iwire": "di_buf[570]", + "twire": "t[570]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y32),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y330", + "site": "IOB_X1Y317", + "ilogic_loc": "ILOGIC_X1Y317", + "ologic_loc": "OLOGIC_X1Y317", + "idelay_loc": "IDELAY_X1Y317", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[571]", + "owire": "do_buf[571]", + "iwire": "di_buf[571]", + "twire": "t[571]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y330", + "site": "IOB_X1Y318", + "ilogic_loc": "ILOGIC_X1Y318", + "ologic_loc": "OLOGIC_X1Y318", + "idelay_loc": "IDELAY_X1Y318", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[572]", + "owire": "do_buf[572]", + "iwire": "di_buf[572]", + "twire": "t[572]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y332", + "site": "IOB_X1Y319", + "ilogic_loc": "ILOGIC_X1Y319", + "ologic_loc": "OLOGIC_X1Y319", + "idelay_loc": "IDELAY_X1Y319", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[573]", + "owire": "do_buf[573]", + "iwire": "di_buf[573]", + "twire": "t[573]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y332", + "site": "IOB_X1Y320", + "ilogic_loc": "ILOGIC_X1Y320", + "ologic_loc": "OLOGIC_X1Y320", + "idelay_loc": "IDELAY_X1Y320", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[574]", + "owire": "do_buf[574]", + "iwire": "di_buf[574]", + "twire": "t[574]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y320),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y334", + "site": "IOB_X1Y321", + "ilogic_loc": "ILOGIC_X1Y321", + "ologic_loc": "OLOGIC_X1Y321", + "idelay_loc": "IDELAY_X1Y321", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[575]", + "owire": "do_buf[575]", + "iwire": "di_buf[575]", + "twire": "t[575]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y334", + "site": "IOB_X1Y322", + "ilogic_loc": "ILOGIC_X1Y322", + "ologic_loc": "OLOGIC_X1Y322", + "idelay_loc": "IDELAY_X1Y322", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[576]", + "owire": "do_buf[576]", + "iwire": "di_buf[576]", + "twire": "t[576]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y336", + "site": "IOB_X1Y323", + "ilogic_loc": "ILOGIC_X1Y323", + "ologic_loc": "OLOGIC_X1Y323", + "idelay_loc": "IDELAY_X1Y323", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[577]", + "owire": "do_buf[577]", + "iwire": "di_buf[577]", + "twire": "t[577]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y323),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y323),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y336", + "site": "IOB_X1Y324", + "ilogic_loc": "ILOGIC_X1Y324", + "ologic_loc": "OLOGIC_X1Y324", + "idelay_loc": "IDELAY_X1Y324", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[578]", + "owire": "do_buf[578]", + "iwire": "di_buf[578]", + "twire": "t[578]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y324),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y339", + "site": "IOB_X1Y325", + "ilogic_loc": "ILOGIC_X1Y325", + "ologic_loc": "OLOGIC_X1Y325", + "idelay_loc": "IDELAY_X1Y325", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[579]", + "owire": "do_buf[579]", + "iwire": "di_buf[579]", + "twire": "t[579]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y339", + "site": "IOB_X1Y326", + "ilogic_loc": "ILOGIC_X1Y326", + "ologic_loc": "OLOGIC_X1Y326", + "idelay_loc": "IDELAY_X1Y326", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[580]", + "owire": "do_buf[580]", + "iwire": "di_buf[580]", + "twire": "t[580]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y326),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y341", + "site": "IOB_X1Y327", + "ilogic_loc": "ILOGIC_X1Y327", + "ologic_loc": "OLOGIC_X1Y327", + "idelay_loc": "IDELAY_X1Y327", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[581]", + "owire": "do_buf[581]", + "iwire": "di_buf[581]", + "twire": "t[581]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y341", + "site": "IOB_X1Y328", + "ilogic_loc": "ILOGIC_X1Y328", + "ologic_loc": "OLOGIC_X1Y328", + "idelay_loc": "IDELAY_X1Y328", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[582]", + "owire": "do_buf[582]", + "iwire": "di_buf[582]", + "twire": "t[582]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y328),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y328),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y343", + "site": "IOB_X1Y329", + "ilogic_loc": "ILOGIC_X1Y329", + "ologic_loc": "OLOGIC_X1Y329", + "idelay_loc": "IDELAY_X1Y329", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[583]", + "owire": "do_buf[583]", + "iwire": "di_buf[583]", + "twire": "t[583]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y343", + "site": "IOB_X1Y330", + "ilogic_loc": "ILOGIC_X1Y330", + "ologic_loc": "OLOGIC_X1Y330", + "idelay_loc": "IDELAY_X1Y330", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[584]", + "owire": "do_buf[584]", + "iwire": "di_buf[584]", + "twire": "t[584]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y345", + "site": "IOB_X1Y331", + "ilogic_loc": "ILOGIC_X1Y331", + "ologic_loc": "OLOGIC_X1Y331", + "idelay_loc": "IDELAY_X1Y331", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[585]", + "owire": "do_buf[585]", + "iwire": "di_buf[585]", + "twire": "t[585]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y331),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y331),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y345", + "site": "IOB_X1Y332", + "ilogic_loc": "ILOGIC_X1Y332", + "ologic_loc": "OLOGIC_X1Y332", + "idelay_loc": "IDELAY_X1Y332", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[586]", + "owire": "do_buf[586]", + "iwire": "di_buf[586]", + "twire": "t[586]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 5, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y332),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y347", + "site": "IOB_X1Y333", + "ilogic_loc": "ILOGIC_X1Y333", + "ologic_loc": "OLOGIC_X1Y333", + "idelay_loc": "IDELAY_X1Y333", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[587]", + "owire": "do_buf[587]", + "iwire": "di_buf[587]", + "twire": "t[587]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y333),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y347", + "site": "IOB_X1Y334", + "ilogic_loc": "ILOGIC_X1Y334", + "ologic_loc": "OLOGIC_X1Y334", + "idelay_loc": "IDELAY_X1Y334", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[588]", + "owire": "do_buf[588]", + "iwire": "di_buf[588]", + "twire": "t[588]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y334),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 5, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y334),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y349", + "site": "IOB_X1Y335", + "ilogic_loc": "ILOGIC_X1Y335", + "ologic_loc": "OLOGIC_X1Y335", + "idelay_loc": "IDELAY_X1Y335", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[589]", + "owire": "do_buf[589]", + "iwire": "di_buf[589]", + "twire": "t[589]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y349", + "site": "IOB_X1Y336", + "ilogic_loc": "ILOGIC_X1Y336", + "ologic_loc": "OLOGIC_X1Y336", + "idelay_loc": "IDELAY_X1Y336", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[590]", + "owire": "do_buf[590]", + "iwire": "di_buf[590]", + "twire": "t[590]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y336),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y336),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y35", + "site": "IOB_X1Y33", + "ilogic_loc": "ILOGIC_X1Y33", + "ologic_loc": "OLOGIC_X1Y33", + "idelay_loc": "IDELAY_X1Y33", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[591]", + "owire": "do_buf[591]", + "iwire": "di_buf[591]", + "twire": "t[591]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y35", + "site": "IOB_X1Y34", + "ilogic_loc": "ILOGIC_X1Y34", + "ologic_loc": "OLOGIC_X1Y34", + "idelay_loc": "IDELAY_X1Y34", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[592]", + "owire": "do_buf[592]", + "iwire": "di_buf[592]", + "twire": "t[592]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y351", + "site": "IOB_X1Y337", + "ilogic_loc": "ILOGIC_X1Y337", + "ologic_loc": "OLOGIC_X1Y337", + "idelay_loc": "IDELAY_X1Y337", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[593]", + "owire": "do_buf[593]", + "iwire": "di_buf[593]", + "twire": "t[593]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y351", + "site": "IOB_X1Y338", + "ilogic_loc": "ILOGIC_X1Y338", + "ologic_loc": "OLOGIC_X1Y338", + "idelay_loc": "IDELAY_X1Y338", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[594]", + "owire": "do_buf[594]", + "iwire": "di_buf[594]", + "twire": "t[594]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y338),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y353", + "site": "IOB_X1Y339", + "ilogic_loc": "ILOGIC_X1Y339", + "ologic_loc": "OLOGIC_X1Y339", + "idelay_loc": "IDELAY_X1Y339", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[595]", + "owire": "do_buf[595]", + "iwire": "di_buf[595]", + "twire": "t[595]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 3, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y339),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y353", + "site": "IOB_X1Y340", + "ilogic_loc": "ILOGIC_X1Y340", + "ologic_loc": "OLOGIC_X1Y340", + "idelay_loc": "IDELAY_X1Y340", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[596]", + "owire": "do_buf[596]", + "iwire": "di_buf[596]", + "twire": "t[596]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 3, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y340),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y340),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y355", + "site": "IOB_X1Y341", + "ilogic_loc": "ILOGIC_X1Y341", + "ologic_loc": "OLOGIC_X1Y341", + "idelay_loc": "IDELAY_X1Y341", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[597]", + "owire": "do_buf[597]", + "iwire": "di_buf[597]", + "twire": "t[597]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y355", + "site": "IOB_X1Y342", + "ilogic_loc": "ILOGIC_X1Y342", + "ologic_loc": "OLOGIC_X1Y342", + "idelay_loc": "IDELAY_X1Y342", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[598]", + "owire": "do_buf[598]", + "iwire": "di_buf[598]", + "twire": "t[598]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y342),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y342),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y357", + "site": "IOB_X1Y343", + "ilogic_loc": "ILOGIC_X1Y343", + "ologic_loc": "OLOGIC_X1Y343", + "idelay_loc": "IDELAY_X1Y343", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[599]", + "owire": "do_buf[599]", + "iwire": "di_buf[599]", + "twire": "t[599]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y357", + "site": "IOB_X1Y344", + "ilogic_loc": "ILOGIC_X1Y344", + "ologic_loc": "OLOGIC_X1Y344", + "idelay_loc": "IDELAY_X1Y344", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[600]", + "owire": "do_buf[600]", + "iwire": "di_buf[600]", + "twire": "t[600]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y359", + "site": "IOB_X1Y345", + "ilogic_loc": "ILOGIC_X1Y345", + "ologic_loc": "OLOGIC_X1Y345", + "idelay_loc": "IDELAY_X1Y345", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[601]", + "owire": "do_buf[601]", + "iwire": "di_buf[601]", + "twire": "t[601]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y359", + "site": "IOB_X1Y346", + "ilogic_loc": "ILOGIC_X1Y346", + "ologic_loc": "OLOGIC_X1Y346", + "idelay_loc": "IDELAY_X1Y346", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[602]", + "owire": "do_buf[602]", + "iwire": "di_buf[602]", + "twire": "t[602]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y346),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y361", + "site": "IOB_X1Y347", + "ilogic_loc": "ILOGIC_X1Y347", + "ologic_loc": "OLOGIC_X1Y347", + "idelay_loc": "IDELAY_X1Y347", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[603]", + "owire": "do_buf[603]", + "iwire": "di_buf[603]", + "twire": "t[603]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 3, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y347),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y361", + "site": "IOB_X1Y348", + "ilogic_loc": "ILOGIC_X1Y348", + "ologic_loc": "OLOGIC_X1Y348", + "idelay_loc": "IDELAY_X1Y348", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[604]", + "owire": "do_buf[604]", + "iwire": "di_buf[604]", + "twire": "t[604]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y37", + "site": "IOB_X1Y35", + "ilogic_loc": "ILOGIC_X1Y35", + "ologic_loc": "OLOGIC_X1Y35", + "idelay_loc": "IDELAY_X1Y35", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[605]", + "owire": "do_buf[605]", + "iwire": "di_buf[605]", + "twire": "t[605]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 7, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y35),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y35),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y37", + "site": "IOB_X1Y36", + "ilogic_loc": "ILOGIC_X1Y36", + "ologic_loc": "OLOGIC_X1Y36", + "idelay_loc": "IDELAY_X1Y36", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[606]", + "owire": "do_buf[606]", + "iwire": "di_buf[606]", + "twire": "t[606]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y36),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y39", + "site": "IOB_X1Y37", + "ilogic_loc": "ILOGIC_X1Y37", + "ologic_loc": "OLOGIC_X1Y37", + "idelay_loc": "IDELAY_X1Y37", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[607]", + "owire": "do_buf[607]", + "iwire": "di_buf[607]", + "twire": "t[607]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y37),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y37),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y39", + "site": "IOB_X1Y38", + "ilogic_loc": "ILOGIC_X1Y38", + "ologic_loc": "OLOGIC_X1Y38", + "idelay_loc": "IDELAY_X1Y38", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[608]", + "owire": "do_buf[608]", + "iwire": "di_buf[608]", + "twire": "t[608]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y4", + "site": "IOB_X1Y3", + "ilogic_loc": "ILOGIC_X1Y3", + "ologic_loc": "OLOGIC_X1Y3", + "idelay_loc": "IDELAY_X1Y3", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[609]", + "owire": "do_buf[609]", + "iwire": "di_buf[609]", + "twire": "t[609]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y4", + "site": "IOB_X1Y4", + "ilogic_loc": "ILOGIC_X1Y4", + "ologic_loc": "OLOGIC_X1Y4", + "idelay_loc": "IDELAY_X1Y4", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[610]", + "owire": "do_buf[610]", + "iwire": "di_buf[610]", + "twire": "t[610]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y41", + "site": "IOB_X1Y39", + "ilogic_loc": "ILOGIC_X1Y39", + "ologic_loc": "OLOGIC_X1Y39", + "idelay_loc": "IDELAY_X1Y39", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[611]", + "owire": "do_buf[611]", + "iwire": "di_buf[611]", + "twire": "t[611]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y41", + "site": "IOB_X1Y40", + "ilogic_loc": "ILOGIC_X1Y40", + "ologic_loc": "OLOGIC_X1Y40", + "idelay_loc": "IDELAY_X1Y40", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 16, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[612]", + "owire": "do_buf[612]", + "iwire": "di_buf[612]", + "twire": "t[612]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y43", + "site": "IOB_X1Y41", + "ilogic_loc": "ILOGIC_X1Y41", + "ologic_loc": "OLOGIC_X1Y41", + "idelay_loc": "IDELAY_X1Y41", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[613]", + "owire": "do_buf[613]", + "iwire": "di_buf[613]", + "twire": "t[613]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y43", + "site": "IOB_X1Y42", + "ilogic_loc": "ILOGIC_X1Y42", + "ologic_loc": "OLOGIC_X1Y42", + "idelay_loc": "IDELAY_X1Y42", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[614]", + "owire": "do_buf[614]", + "iwire": "di_buf[614]", + "twire": "t[614]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y45", + "site": "IOB_X1Y43", + "ilogic_loc": "ILOGIC_X1Y43", + "ologic_loc": "OLOGIC_X1Y43", + "idelay_loc": "IDELAY_X1Y43", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[615]", + "owire": "do_buf[615]", + "iwire": "di_buf[615]", + "twire": "t[615]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y45", + "site": "IOB_X1Y44", + "ilogic_loc": "ILOGIC_X1Y44", + "ologic_loc": "OLOGIC_X1Y44", + "idelay_loc": "IDELAY_X1Y44", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[616]", + "owire": "do_buf[616]", + "iwire": "di_buf[616]", + "twire": "t[616]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y47", + "site": "IOB_X1Y45", + "ilogic_loc": "ILOGIC_X1Y45", + "ologic_loc": "OLOGIC_X1Y45", + "idelay_loc": "IDELAY_X1Y45", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[617]", + "owire": "do_buf[617]", + "iwire": "di_buf[617]", + "twire": "t[617]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 3, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y47", + "site": "IOB_X1Y46", + "ilogic_loc": "ILOGIC_X1Y46", + "ologic_loc": "OLOGIC_X1Y46", + "idelay_loc": "IDELAY_X1Y46", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[618]", + "owire": "do_buf[618]", + "iwire": "di_buf[618]", + "twire": "t[618]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y49", + "site": "IOB_X1Y47", + "ilogic_loc": "ILOGIC_X1Y47", + "ologic_loc": "OLOGIC_X1Y47", + "idelay_loc": "IDELAY_X1Y47", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[619]", + "owire": "do_buf[619]", + "iwire": "di_buf[619]", + "twire": "t[619]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y49", + "site": "IOB_X1Y48", + "ilogic_loc": "ILOGIC_X1Y48", + "ologic_loc": "OLOGIC_X1Y48", + "idelay_loc": "IDELAY_X1Y48", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[620]", + "owire": "do_buf[620]", + "iwire": "di_buf[620]", + "twire": "t[620]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y54", + "site": "IOB_X1Y51", + "ilogic_loc": "ILOGIC_X1Y51", + "ologic_loc": "OLOGIC_X1Y51", + "idelay_loc": "IDELAY_X1Y51", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[621]", + "owire": "do_buf[621]", + "iwire": "di_buf[621]", + "twire": "t[621]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y51),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y54", + "site": "IOB_X1Y52", + "ilogic_loc": "ILOGIC_X1Y52", + "ologic_loc": "OLOGIC_X1Y52", + "idelay_loc": "IDELAY_X1Y52", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[622]", + "owire": "do_buf[622]", + "iwire": "di_buf[622]", + "twire": "t[622]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y52),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y56", + "site": "IOB_X1Y53", + "ilogic_loc": "ILOGIC_X1Y53", + "ologic_loc": "OLOGIC_X1Y53", + "idelay_loc": "IDELAY_X1Y53", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[623]", + "owire": "do_buf[623]", + "iwire": "di_buf[623]", + "twire": "t[623]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y56", + "site": "IOB_X1Y54", + "ilogic_loc": "ILOGIC_X1Y54", + "ologic_loc": "OLOGIC_X1Y54", + "idelay_loc": "IDELAY_X1Y54", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[624]", + "owire": "do_buf[624]", + "iwire": "di_buf[624]", + "twire": "t[624]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y54),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y58", + "site": "IOB_X1Y55", + "ilogic_loc": "ILOGIC_X1Y55", + "ologic_loc": "OLOGIC_X1Y55", + "idelay_loc": "IDELAY_X1Y55", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[625]", + "owire": "do_buf[625]", + "iwire": "di_buf[625]", + "twire": "t[625]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y55),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y58", + "site": "IOB_X1Y56", + "ilogic_loc": "ILOGIC_X1Y56", + "ologic_loc": "OLOGIC_X1Y56", + "idelay_loc": "IDELAY_X1Y56", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[626]", + "owire": "do_buf[626]", + "iwire": "di_buf[626]", + "twire": "t[626]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y6", + "site": "IOB_X1Y5", + "ilogic_loc": "ILOGIC_X1Y5", + "ologic_loc": "OLOGIC_X1Y5", + "idelay_loc": "IDELAY_X1Y5", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[627]", + "owire": "do_buf[627]", + "iwire": "di_buf[627]", + "twire": "t[627]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y6", + "site": "IOB_X1Y6", + "ilogic_loc": "ILOGIC_X1Y6", + "ologic_loc": "OLOGIC_X1Y6", + "idelay_loc": "IDELAY_X1Y6", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[628]", + "owire": "do_buf[628]", + "iwire": "di_buf[628]", + "twire": "t[628]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y60", + "site": "IOB_X1Y57", + "ilogic_loc": "ILOGIC_X1Y57", + "ologic_loc": "OLOGIC_X1Y57", + "idelay_loc": "IDELAY_X1Y57", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[629]", + "owire": "do_buf[629]", + "iwire": "di_buf[629]", + "twire": "t[629]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y60", + "site": "IOB_X1Y58", + "ilogic_loc": "ILOGIC_X1Y58", + "ologic_loc": "OLOGIC_X1Y58", + "idelay_loc": "IDELAY_X1Y58", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[630]", + "owire": "do_buf[630]", + "iwire": "di_buf[630]", + "twire": "t[630]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y62", + "site": "IOB_X1Y59", + "ilogic_loc": "ILOGIC_X1Y59", + "ologic_loc": "OLOGIC_X1Y59", + "idelay_loc": "IDELAY_X1Y59", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[631]", + "owire": "do_buf[631]", + "iwire": "di_buf[631]", + "twire": "t[631]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y59),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y62", + "site": "IOB_X1Y60", + "ilogic_loc": "ILOGIC_X1Y60", + "ologic_loc": "OLOGIC_X1Y60", + "idelay_loc": "IDELAY_X1Y60", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[632]", + "owire": "do_buf[632]", + "iwire": "di_buf[632]", + "twire": "t[632]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 2, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y60),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y64", + "site": "IOB_X1Y61", + "ilogic_loc": "ILOGIC_X1Y61", + "ologic_loc": "OLOGIC_X1Y61", + "idelay_loc": "IDELAY_X1Y61", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[633]", + "owire": "do_buf[633]", + "iwire": "di_buf[633]", + "twire": "t[633]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y64", + "site": "IOB_X1Y62", + "ilogic_loc": "ILOGIC_X1Y62", + "ologic_loc": "OLOGIC_X1Y62", + "idelay_loc": "IDELAY_X1Y62", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[634]", + "owire": "do_buf[634]", + "iwire": "di_buf[634]", + "twire": "t[634]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y62),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y62),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y66", + "site": "IOB_X1Y63", + "ilogic_loc": "ILOGIC_X1Y63", + "ologic_loc": "OLOGIC_X1Y63", + "idelay_loc": "IDELAY_X1Y63", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[635]", + "owire": "do_buf[635]", + "iwire": "di_buf[635]", + "twire": "t[635]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 2, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y63),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y66", + "site": "IOB_X1Y64", + "ilogic_loc": "ILOGIC_X1Y64", + "ologic_loc": "OLOGIC_X1Y64", + "idelay_loc": "IDELAY_X1Y64", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[636]", + "owire": "do_buf[636]", + "iwire": "di_buf[636]", + "twire": "t[636]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y64),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y64),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y68", + "site": "IOB_X1Y65", + "ilogic_loc": "ILOGIC_X1Y65", + "ologic_loc": "OLOGIC_X1Y65", + "idelay_loc": "IDELAY_X1Y65", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 4, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[637]", + "owire": "do_buf[637]", + "iwire": "di_buf[637]", + "twire": "t[637]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y68", + "site": "IOB_X1Y66", + "ilogic_loc": "ILOGIC_X1Y66", + "ologic_loc": "OLOGIC_X1Y66", + "idelay_loc": "IDELAY_X1Y66", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[638]", + "owire": "do_buf[638]", + "iwire": "di_buf[638]", + "twire": "t[638]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 5, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y66),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y70", + "site": "IOB_X1Y67", + "ilogic_loc": "ILOGIC_X1Y67", + "ologic_loc": "OLOGIC_X1Y67", + "idelay_loc": "IDELAY_X1Y67", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[639]", + "owire": "do_buf[639]", + "iwire": "di_buf[639]", + "twire": "t[639]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y67),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y67),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y70", + "site": "IOB_X1Y68", + "ilogic_loc": "ILOGIC_X1Y68", + "ologic_loc": "OLOGIC_X1Y68", + "idelay_loc": "IDELAY_X1Y68", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[640]", + "owire": "do_buf[640]", + "iwire": "di_buf[640]", + "twire": "t[640]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"" + }, + { + "tile": "RIOB18_X312Y72", + "site": "IOB_X1Y69", + "ilogic_loc": "ILOGIC_X1Y69", + "ologic_loc": "OLOGIC_X1Y69", + "idelay_loc": "IDELAY_X1Y69", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[641]", + "owire": "do_buf[641]", + "iwire": "di_buf[641]", + "twire": "t[641]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y69),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y69),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y72", + "site": "IOB_X1Y70", + "ilogic_loc": "ILOGIC_X1Y70", + "ologic_loc": "OLOGIC_X1Y70", + "idelay_loc": "IDELAY_X1Y70", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[642]", + "owire": "do_buf[642]", + "iwire": "di_buf[642]", + "twire": "t[642]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y70),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"SLAVE\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y70),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y74", + "site": "IOB_X1Y71", + "ilogic_loc": "ILOGIC_X1Y71", + "ologic_loc": "OLOGIC_X1Y71", + "idelay_loc": "IDELAY_X1Y71", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[643]", + "owire": "do_buf[643]", + "iwire": "di_buf[643]", + "twire": "t[643]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y71),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y71),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y74", + "site": "IOB_X1Y72", + "ilogic_loc": "ILOGIC_X1Y72", + "ologic_loc": "OLOGIC_X1Y72", + "idelay_loc": "IDELAY_X1Y72", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[644]", + "owire": "do_buf[644]", + "iwire": "di_buf[644]", + "twire": "t[644]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y76", + "site": "IOB_X1Y73", + "ilogic_loc": "ILOGIC_X1Y73", + "ologic_loc": "OLOGIC_X1Y73", + "idelay_loc": "IDELAY_X1Y73", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[645]", + "owire": "do_buf[645]", + "iwire": "di_buf[645]", + "twire": "t[645]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y73),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 8, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y73),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y76", + "site": "IOB_X1Y74", + "ilogic_loc": "ILOGIC_X1Y74", + "ologic_loc": "OLOGIC_X1Y74", + "idelay_loc": "IDELAY_X1Y74", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[646]", + "owire": "do_buf[646]", + "iwire": "di_buf[646]", + "twire": "t[646]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "idelay", + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y79", + "site": "IOB_X1Y75", + "ilogic_loc": "ILOGIC_X1Y75", + "ologic_loc": "OLOGIC_X1Y75", + "idelay_loc": "IDELAY_X1Y75", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[647]", + "owire": "do_buf[647]", + "iwire": "di_buf[647]", + "twire": "t[647]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y79", + "site": "IOB_X1Y76", + "ilogic_loc": "ILOGIC_X1Y76", + "ologic_loc": "OLOGIC_X1Y76", + "idelay_loc": "IDELAY_X1Y76", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[648]", + "owire": "do_buf[648]", + "iwire": "di_buf[648]", + "twire": "t[648]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y76),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y8", + "site": "IOB_X1Y7", + "ilogic_loc": "ILOGIC_X1Y7", + "ologic_loc": "OLOGIC_X1Y7", + "idelay_loc": "IDELAY_X1Y7", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[649]", + "owire": "do_buf[649]", + "iwire": "di_buf[649]", + "twire": "t[649]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y8", + "site": "IOB_X1Y8", + "ilogic_loc": "ILOGIC_X1Y8", + "ologic_loc": "OLOGIC_X1Y8", + "idelay_loc": "IDELAY_X1Y8", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 16, + "SLEW": "\"FAST\"", + "pad_wire": "dio[650]", + "owire": "do_buf[650]", + "iwire": "di_buf[650]", + "twire": "t[650]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 5, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y8),", + "ODATA_RATE": "\"SDR\"", + "ODATA_WIDTH": 3, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y8),\n ", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y81", + "site": "IOB_X1Y77", + "ilogic_loc": "ILOGIC_X1Y77", + "ologic_loc": "OLOGIC_X1Y77", + "idelay_loc": "IDELAY_X1Y77", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[651]", + "owire": "do_buf[651]", + "iwire": "di_buf[651]", + "twire": "t[651]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y81", + "site": "IOB_X1Y78", + "ilogic_loc": "ILOGIC_X1Y78", + "ologic_loc": "OLOGIC_X1Y78", + "idelay_loc": "IDELAY_X1Y78", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 2, + "SLEW": "\"FAST\"", + "pad_wire": "dio[652]", + "owire": "do_buf[652]", + "iwire": "di_buf[652]", + "twire": "t[652]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y83", + "site": "IOB_X1Y79", + "ilogic_loc": "ILOGIC_X1Y79", + "ologic_loc": "OLOGIC_X1Y79", + "idelay_loc": "IDELAY_X1Y79", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[653]", + "owire": "do_buf[653]", + "iwire": "di_buf[653]", + "twire": "t[653]", + "use_iserdese2": 1, + "IOBDELAY": "\"IBUF\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y79),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y83", + "site": "IOB_X1Y80", + "ilogic_loc": "ILOGIC_X1Y80", + "ologic_loc": "OLOGIC_X1Y80", + "idelay_loc": "IDELAY_X1Y80", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[654]", + "owire": "do_buf[654]", + "iwire": "di_buf[654]", + "twire": "t[654]", + "use_iserdese2": 1, + "IOBDELAY": "\"NONE\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 2, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "direct", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": "", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y85", + "site": "IOB_X1Y81", + "ilogic_loc": "ILOGIC_X1Y81", + "ologic_loc": "OLOGIC_X1Y81", + "idelay_loc": "IDELAY_X1Y81", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[655]", + "owire": "do_buf[655]", + "iwire": "di_buf[655]", + "twire": "t[655]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 7, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y81),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y85", + "site": "IOB_X1Y82", + "ilogic_loc": "ILOGIC_X1Y82", + "ologic_loc": "OLOGIC_X1Y82", + "idelay_loc": "IDELAY_X1Y82", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[656]", + "owire": "do_buf[656]", + "iwire": "di_buf[656]", + "twire": "t[656]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"ASYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y87", + "site": "IOB_X1Y83", + "ilogic_loc": "ILOGIC_X1Y83", + "ologic_loc": "OLOGIC_X1Y83", + "idelay_loc": "IDELAY_X1Y83", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[657]", + "owire": "do_buf[657]", + "iwire": "di_buf[657]", + "twire": "t[657]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y83),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 4, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 4, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y83),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y87", + "site": "IOB_X1Y84", + "ilogic_loc": "ILOGIC_X1Y84", + "ologic_loc": "OLOGIC_X1Y84", + "idelay_loc": "IDELAY_X1Y84", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[658]", + "owire": "do_buf[658]", + "iwire": "di_buf[658]", + "twire": "t[658]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y89", + "site": "IOB_X1Y85", + "ilogic_loc": "ILOGIC_X1Y85", + "ologic_loc": "OLOGIC_X1Y85", + "idelay_loc": "IDELAY_X1Y85", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[659]", + "owire": "do_buf[659]", + "iwire": "di_buf[659]", + "twire": "t[659]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y85),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y89", + "site": "IOB_X1Y86", + "ilogic_loc": "ILOGIC_X1Y86", + "ologic_loc": "OLOGIC_X1Y86", + "idelay_loc": "IDELAY_X1Y86", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLUP\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[660]", + "owire": "do_buf[660]", + "iwire": "di_buf[660]", + "twire": "t[660]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y91", + "site": "IOB_X1Y87", + "ilogic_loc": "ILOGIC_X1Y87", + "ologic_loc": "OLOGIC_X1Y87", + "idelay_loc": "IDELAY_X1Y87", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 6, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[661]", + "owire": "do_buf[661]", + "iwire": "di_buf[661]", + "twire": "t[661]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y91", + "site": "IOB_X1Y88", + "ilogic_loc": "ILOGIC_X1Y88", + "ologic_loc": "OLOGIC_X1Y88", + "idelay_loc": "IDELAY_X1Y88", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 12, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[662]", + "owire": "do_buf[662]", + "iwire": "di_buf[662]", + "twire": "t[662]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 1, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 6, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"TRUE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y88),", + "ODATA_RATE": "\"DDR\"", + "ODATA_WIDTH": 6, + "OSERDES_MODE": "\"MASTER\"", + "TRISTATE_WIDTH": 1, + "ofb_connections": "\n .OFB(ofb_IOB_X1Y88),\n ", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y93", + "site": "IOB_X1Y89", + "ilogic_loc": "ILOGIC_X1Y89", + "ologic_loc": "OLOGIC_X1Y89", + "idelay_loc": "IDELAY_X1Y89", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 6, + "SLEW": "\"FAST\"", + "pad_wire": "dio[663]", + "owire": "do_buf[663]", + "iwire": "di_buf[663]", + "twire": "t[663]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y93", + "site": "IOB_X1Y90", + "ilogic_loc": "ILOGIC_X1Y90", + "ologic_loc": "OLOGIC_X1Y90", + "idelay_loc": "IDELAY_X1Y90", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[664]", + "owire": "do_buf[664]", + "iwire": "di_buf[664]", + "twire": "t[664]", + "use_iserdese2": 1, + "IOBDELAY": "\"BOTH\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 3, + "SERDES_MODE": "\"MASTER\"", + "mux_config": "idelay", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y90),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y95", + "site": "IOB_X1Y91", + "ilogic_loc": "ILOGIC_X1Y91", + "ologic_loc": "OLOGIC_X1Y91", + "idelay_loc": "IDELAY_X1Y91", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"NONE\"", + "DRIVE": 2, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[665]", + "owire": "do_buf[665]", + "iwire": "di_buf[665]", + "twire": "t[665]", + "use_iserdese2": 0, + "mux_config": "direct", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE\"" + }, + { + "tile": "RIOB18_X312Y95", + "site": "IOB_X1Y92", + "ilogic_loc": "ILOGIC_X1Y92", + "ologic_loc": "OLOGIC_X1Y92", + "idelay_loc": "IDELAY_X1Y92", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"PULLDOWN\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[666]", + "owire": "do_buf[666]", + "iwire": "di_buf[666]", + "twire": "t[666]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 1, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y92),", + "ofb_connections": "", + "DISABLE_CLOCKS": 0 + }, + { + "tile": "RIOB18_X312Y97", + "site": "IOB_X1Y93", + "ilogic_loc": "ILOGIC_X1Y93", + "ologic_loc": "OLOGIC_X1Y93", + "idelay_loc": "IDELAY_X1Y93", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 12, + "SLEW": "\"FAST\"", + "pad_wire": "dio[667]", + "owire": "do_buf[667]", + "iwire": "di_buf[667]", + "twire": "t[667]", + "use_iserdese2": 1, + "IOBDELAY": "\"IFD\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "NUM_CE": 2, + "IS_CLK_INVERTED": 0, + "IS_CLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_D_INVERTED": 1, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 8, + "SERDES_MODE": "\"SLAVE\"", + "mux_config": "direct", + "iddr_mux_config": "idelay", + "OFB_USED": "\"FALSE\"", + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "ddly_connection": ".DDLY(idelay_IOB_X1Y93),", + "ofb_connections": "", + "DISABLE_CLOCKS": 1 + }, + { + "tile": "RIOB18_X312Y97", + "site": "IOB_X1Y94", + "ilogic_loc": "ILOGIC_X1Y94", + "ologic_loc": "OLOGIC_X1Y94", + "idelay_loc": "IDELAY_X1Y94", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"SLOW\"", + "pad_wire": "dio[668]", + "owire": "do_buf[668]", + "iwire": "di_buf[668]", + "twire": "t[668]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "none" + }, + { + "tile": "RIOB18_X312Y99", + "site": "IOB_X1Y95", + "ilogic_loc": "ILOGIC_X1Y95", + "ologic_loc": "OLOGIC_X1Y95", + "idelay_loc": "IDELAY_X1Y95", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 4, + "SLEW": "\"FAST\"", + "pad_wire": "dio[669]", + "owire": "do_buf[669]", + "iwire": "di_buf[669]", + "twire": "t[669]", + "use_iserdese2": 0, + "mux_config": "idelay", + "iddr_mux_config": "direct", + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "SRTYPE": "\"SYNC\"", + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"" + }, + { + "tile": "RIOB18_X312Y99", + "site": "IOB_X1Y96", + "ilogic_loc": "ILOGIC_X1Y96", + "ologic_loc": "OLOGIC_X1Y96", + "idelay_loc": "IDELAY_X1Y96", + "IOSTANDARD": "\"LVCMOS18\"", + "PULLTYPE": "\"KEEPER\"", + "DRIVE": 8, + "SLEW": "\"FAST\"", + "pad_wire": "dio[670]", + "owire": "do_buf[670]", + "iwire": "di_buf[670]", + "twire": "t[670]", + "use_iserdese2": 0, + "mux_config": "none", + "iddr_mux_config": "none" + } +] \ No newline at end of file diff --git a/fuzzers/035-iob18-ilogic/tag_groups.txt b/fuzzers/035-iob18-ilogic/tag_groups.txt new file mode 100644 index 00000000..d7e54647 --- /dev/null +++ b/fuzzers/035-iob18-ilogic/tag_groups.txt @@ -0,0 +1,8 @@ +IOI.ILOGIC_Y0.IDELMUXE3.P0 IOI.ILOGIC_Y0.IDELMUXE3.P1 +IOI.ILOGIC_Y0.IFFDELMUXE3.P0 IOI.ILOGIC_Y0.IFFDELMUXE3.P1 +IOI.ILOGIC_Y0.IFF.SRTYPE.ASYNC IOI.ILOGIC_Y0.IFF.SRTYPE.SYNC +IOI.ILOGIC_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE IOI.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE IOI.ILOGIC_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED +IOI.ILOGIC_Y1.IDELMUXE3.P0 IOI.ILOGIC_Y1.IDELMUXE3.P1 +IOI.ILOGIC_Y1.IFFDELMUXE3.P0 IOI.ILOGIC_Y1.IFFDELMUXE3.P1 +IOI.ILOGIC_Y1.IFF.SRTYPE.ASYNC IOI.ILOGIC_Y1.IFF.SRTYPE.SYNC +IOI.ILOGIC_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE IOI.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE IOI.ILOGIC_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED diff --git a/fuzzers/035-iob18-ilogic/top.py b/fuzzers/035-iob18-ilogic/top.py new file mode 100644 index 00000000..f83b03b1 --- /dev/null +++ b/fuzzers/035-iob18-ilogic/top.py @@ -0,0 +1,517 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +# +# Copyright (C) 2017-2020 The Project X-Ray Authors. +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC +import json +import io +import os +import random +random.seed(int(os.getenv("SEED"), 16)) +from prjxray import util +from prjxray import lut_maker +from prjxray import verilog +from prjxray.db import Database + + +def gen_sites(): + ''' + IOB18S: main IOB of a diff pair + IOB18M: secondary IOB of a diff pair + + Virtex-7 "VX" parts are high-performance-bank only (IOB18 / IOI = LIOI, + RIOI and their TBYTESRC/TBYTETERM variants); there are no IOB33/HR sites, + so the kintex7 035-iob-ilogic fuzzer cannot run here. Cover BOTH the L- + and R-side IOB18 columns so LIOI and RIOI get real measurements rather + than a transplant. SING rows are excluded (their ILOGIC is fuzzed + separately and has a different frame window). + ''' + db = Database(util.get_db_root(), util.get_part()) + grid = db.grid() + for tile_name in sorted(grid.tiles()): + if "IOB18" not in tile_name or "SING" in tile_name: + continue + loc = grid.loc_of_tilename(tile_name) + gridinfo = grid.gridinfo_at_loc(loc) + + for site_name, site_type in gridinfo.sites.items(): + if site_type in ['IOB18S', 'IOB18M']: + yield tile_name, site_name + + +def write_params(params): + pinstr = 'tile,site,pin,iostandard,drive,slew\n' + for vals in params: + pinstr += ','.join(map(str, vals)) + '\n' + + open('params.csv', 'w').write(pinstr) + + +def use_iserdese2(p, luts, connects): + iobdelay = random.choice(( + 'NONE', + 'BOTH', + 'IBUF', + 'IFD', + )) + + p['IOBDELAY'] = verilog.quote(iobdelay) + p['INIT_Q1'] = random.randint(0, 1) + p['INIT_Q2'] = random.randint(0, 1) + p['INIT_Q3'] = random.randint(0, 1) + p['INIT_Q4'] = random.randint(0, 1) + + p['SRVAL_Q1'] = random.randint(0, 1) + p['SRVAL_Q2'] = random.randint(0, 1) + p['SRVAL_Q3'] = random.randint(0, 1) + p['SRVAL_Q4'] = random.randint(0, 1) + p['NUM_CE'] = random.randint(1, 2) + + p['IS_CLK_INVERTED'] = random.randint(0, 1) + p['IS_CLKB_INVERTED'] = random.randint(0, 1) + p['IS_OCLK_INVERTED'] = random.randint(0, 1) + p['IS_OCLKB_INVERTED'] = random.randint(0, 1) + p['IS_CLKDIV_INVERTED'] = random.randint(0, 1) + p['IS_D_INVERTED'] = random.randint(0, 1) + p['INTERFACE_TYPE'] = verilog.quote( + random.choice( + ( + 'MEMORY', + 'MEMORY_DDR3', + 'MEMORY_QDR', + 'NETWORKING', + 'OVERSAMPLE', + ))) + p['DATA_RATE'] = verilog.quote(random.choice(( + 'SDR', + 'DDR', + ))) + if verilog.unquote(p['DATA_RATE']) == 'SDR': + data_widths = [2, 3, 4, 5, 6, 7, 8] + else: + data_widths = [4, 6, 8] + + p['DATA_WIDTH'] = random.choice(data_widths) + p['SERDES_MODE'] = verilog.quote(random.choice(('MASTER', 'SLAVE'))) + + use_delay = iobdelay != 'NONE' + + if iobdelay == 'NONE': + p['mux_config'] = 'direct' + p['iddr_mux_config'] = 'direct' + elif iobdelay == 'BOTH': + p['mux_config'] = 'idelay' + p['iddr_mux_config'] = 'idelay' + elif iobdelay == 'IBUF': + p['mux_config'] = 'idelay' + p['iddr_mux_config'] = 'direct' + elif iobdelay == 'IFD': + p['mux_config'] = 'direct' + p['iddr_mux_config'] = 'idelay' + + p['OFB_USED'] = verilog.quote(random.choice(('TRUE', 'FALSE'))) + p['DYN_CLKDIV_INV_EN'] = verilog.quote(random.choice(('TRUE', 'FALSE'))) + p['DYN_CLK_INV_EN'] = verilog.quote(random.choice(('TRUE', 'FALSE'))) + + if use_delay: + print( + """ + wire idelay_{site}; + + (* KEEP, DONT_TOUCH, LOC = "{idelay_loc}" *) + IDELAYE2 #( + ) idelay_site_{site} ( + .IDATAIN({iwire}), + .DATAOUT(idelay_{site}) + );""".format(**p), + file=connects) + + p['ddly_connection'] = '.DDLY(idelay_{site}),'.format(**p) + else: + p['ddly_connection'] = '' + + if verilog.unquote(p['OFB_USED']) == 'TRUE': + p['ODATA_RATE'] = verilog.quote(random.choice(( + 'SDR', + 'DDR', + ))) + if verilog.unquote(p['ODATA_RATE']) == 'SDR': + data_widths = [2, 3, 4, 5, 6, 7, 8] + else: + data_widths = [4, 6, 8] + + p['ODATA_WIDTH'] = random.choice(data_widths) + p['OSERDES_MODE'] = verilog.quote(random.choice(('MASTER', 'SLAVE'))) + + if p['ODATA_WIDTH'] == 4 and verilog.unquote(p['ODATA_RATE']) == 'DDR': + p['TRISTATE_WIDTH'] = 4 + else: + p['TRISTATE_WIDTH'] = 1 + + print( + """ + wire tfb_{site}; + wire ofb_{site}; + + (* KEEP, DONT_TOUCH, LOC = "{ologic_loc}" *) + OSERDESE2 #( + .SERDES_MODE({OSERDES_MODE}), + .DATA_RATE_TQ({ODATA_RATE}), + .DATA_RATE_OQ({ODATA_RATE}), + .DATA_WIDTH({ODATA_WIDTH}), + .TRISTATE_WIDTH({TRISTATE_WIDTH}) + ) oserdese2_{site} ( + .CLK(0), + .CLKDIV(0), + .D1(0), + .TFB(tfb_{site}), + .OQ({owire}), + .TQ({twire}), + .OFB(ofb_{site}) + );""".format(**p), + file=connects) + + p['ofb_connections'] = """ + .OFB(ofb_{site}), + """.format(**p) + else: + p['ofb_connections'] = '' + + if random.randint(0, 1): + clknet = luts.get_next_output_net() + else: + clknet = random.choice(( + 'clk_BUFG1', + 'clk_BUFG2', + )) + + if random.randint(0, 1): + clkbnet = luts.get_next_output_net() + else: + clkbnet = random.choice(( + 'clk_BUFG1', + 'clk_BUFG2', + )) + + if random.randint(0, 1): + oclknet = luts.get_next_output_net() + else: + oclknet = random.choice(( + 'clk_BUFG1', + 'clk_BUFG2', + )) + + clkdiv = random.choice(('clk_BUFG3', 'clk_BUFG4')) + + p['DISABLE_CLOCKS'] = random.randint(0, 1) + if p['DISABLE_CLOCKS']: + clknet = '0' + clkbnet = '0' + oclknet = '0' + clkdiv = '0' + + print( + ''' + (* KEEP, DONT_TOUCH, LOC = "{ilogic_loc}" *) + ISERDESE2 #( + .SERDES_MODE({SERDES_MODE}), + .INIT_Q1({INIT_Q1}), + .INIT_Q2({INIT_Q2}), + .INIT_Q3({INIT_Q3}), + .INIT_Q4({INIT_Q4}), + .SRVAL_Q1({SRVAL_Q1}), + .SRVAL_Q2({SRVAL_Q2}), + .SRVAL_Q3({SRVAL_Q3}), + .SRVAL_Q4({SRVAL_Q4}), + .DYN_CLKDIV_INV_EN({DYN_CLKDIV_INV_EN}), + .DYN_CLK_INV_EN({DYN_CLK_INV_EN}), + .INTERFACE_TYPE({INTERFACE_TYPE}), + .IS_CLK_INVERTED({IS_CLK_INVERTED}), + .IS_CLKB_INVERTED({IS_CLKB_INVERTED}), + .IS_OCLK_INVERTED({IS_OCLK_INVERTED}), + .IS_OCLKB_INVERTED({IS_OCLKB_INVERTED}), + .IS_CLKDIV_INVERTED({IS_CLKDIV_INVERTED}), + .IS_D_INVERTED({IS_D_INVERTED}), + .OFB_USED({OFB_USED}), + .NUM_CE({NUM_CE}), + .DATA_RATE({DATA_RATE}), + .DATA_WIDTH({DATA_WIDTH}), + .IOBDELAY({IOBDELAY}) + ) iserdese2_{site} ( + {ddly_connection} + {ofb_connections} + .D({iwire}), + .CLK({clknet}), + .CLKB({clkbnet}), + .OCLK({oclknet}), + .O({onet}), + .Q1({q1net}), + .CLKDIV({clkdiv}) + );'''.format( + clkdiv=clkdiv, + clknet=clknet, + clkbnet=clkbnet, + oclknet=oclknet, + onet=luts.get_next_input_net(), + q1net=luts.get_next_input_net(), + shiftout1net=luts.get_next_input_net(), + shiftout2net=luts.get_next_input_net(), + **p), + file=connects) + + +def use_direct_and_iddr(p, luts, connects): + p['mux_config'] = random.choice(( + 'direct', + 'idelay', + 'none', + )) + + p['iddr_mux_config'] = random.choice(( + 'direct', + 'idelay', + 'none', + )) + + if p['iddr_mux_config'] != 'none': + p['INIT_Q1'] = random.randint(0, 1) + p['INIT_Q2'] = random.randint(0, 1) + p['IS_C_INVERTED'] = random.randint(0, 1) + p['IS_D_INVERTED'] = random.randint(0, 1) + p['SRTYPE'] = verilog.quote(random.choice(('SYNC', 'ASYNC'))) + p['DDR_CLK_EDGE'] = verilog.quote( + random.choice( + ( + 'OPPOSITE_EDGE', + 'SAME_EDGE', + 'SAME_EDGE_PIPELINED', + ))) + + print( + ''' + (* KEEP, DONT_TOUCH, LOC = "{ilogic_loc}" *) + IDDR #( + .IS_D_INVERTED({IS_D_INVERTED}), + .IS_C_INVERTED({IS_C_INVERTED}), + .INIT_Q1({INIT_Q1}), + .INIT_Q2({INIT_Q2}), + .SRTYPE({SRTYPE}), + .DDR_CLK_EDGE({DDR_CLK_EDGE}) + ) iddr_{site} ( + .C({cnet}), + .D(iddr_d_{site}), + .Q1({q1}), + .Q2({q2}) + ); + '''.format( + cnet=luts.get_next_output_net(), + q1=luts.get_next_input_net(), + q2=luts.get_next_input_net(), + **p), + file=connects) + + if p['iddr_mux_config'] == 'idelay' or p['mux_config'] == 'idelay' or p[ + 'iddr_mux_config'] == 'tristate_feedback': + print( + """ + wire idelay_{site}; + + (* KEEP, DONT_TOUCH, LOC = "{idelay_loc}" *) + IDELAYE2 #( + ) idelay_site_{site} ( + .IDATAIN({iwire}), + .DATAOUT(idelay_{site}) + );""".format(**p), + file=connects) + + print( + """ + assign {owire} = {onet}; + assign {twire} = {tnet}; + """.format( + onet=luts.get_next_output_net(), + tnet=luts.get_next_output_net(), + **p), + file=connects) + + if p['iddr_mux_config'] == 'direct': + print( + ''' + assign iddr_d_{site} = {iwire};'''.format(**p, ), + file=connects) + elif p['iddr_mux_config'] == 'idelay': + print( + ''' + assign iddr_d_{site} = idelay_{site};'''.format(**p, ), + file=connects) + elif p['iddr_mux_config'] == 'tristate_feedback': + print( + ''' + assign iddr_d_{site} = tfb_{site} ? ofb_{site} : idelay_{site};'''.format( + **p, ), + file=connects) + elif p['iddr_mux_config'] == 'none': + pass + else: + assert False, p['mux_config'] + + if p['mux_config'] == 'direct': + print( + ''' + assign {net} = {iwire};'''.format( + net=luts.get_next_input_net(), + **p, + ), + file=connects) + elif p['mux_config'] == 'idelay': + print( + ''' + assign {net} = idelay_{site};'''.format( + net=luts.get_next_input_net(), + **p, + ), + file=connects) + elif p['mux_config'] == 'none': + pass + else: + assert False, p['mux_config'] + + +def run(): + # IOSTANDARD does not affect the ILOGIC config bits being measured, so pin + # it to LVCMOS18 (valid on every HP bank at the default drive). LVCMOS12's + # default drive of 12 is illegal on HP banks (DRC BIVB-1), and mixing + # standards only adds bank-compatibility failure modes for no extra ILOGIC + # coverage. + iostandards = ['LVCMOS18'] + iostandard = random.choice(iostandards) + drives = [2, 4, 6, 8, 12, 16] + + slews = ['FAST', 'SLOW'] + pulls = ["NONE", "KEEPER", "PULLDOWN", "PULLUP"] + + luts = lut_maker.LutMaker() + + connects = io.StringIO() + + tile_params = [] + params = [] + for idx, (tile, site) in enumerate(gen_sites()): + if idx == 0: + continue + + p = {} + p['tile'] = tile + p['site'] = site + p['ilogic_loc'] = site.replace('IOB', 'ILOGIC') + p['ologic_loc'] = site.replace('IOB', 'OLOGIC') + p['idelay_loc'] = site.replace('IOB', 'IDELAY') + p['IOSTANDARD'] = verilog.quote(iostandard) + p['PULLTYPE'] = verilog.quote(random.choice(pulls)) + p['DRIVE'] = random.choice(drives) + p['SLEW'] = verilog.quote(random.choice(slews)) + + p['pad_wire'] = 'dio[{}]'.format(idx - 1) + p['owire'] = 'do_buf[{}]'.format(idx - 1) + p['iwire'] = 'di_buf[{}]'.format(idx - 1) + p['twire'] = 't[{}]'.format(idx - 1) + + params.append(p) + tile_params.append( + ( + tile, site, p['pad_wire'], iostandard, p['DRIVE'], + verilog.unquote(p['SLEW']) if p['SLEW'] else None, + verilog.unquote(p['PULLTYPE']))) + + write_params(tile_params) + + print( + ''' +`define N_DI {n_di} + +module top(input clk, inout wire [`N_DI-1:0] dio); + wire [`N_DI-1:0] di_buf; + wire [`N_DI-1:0] do_buf; + wire [`N_DI-1:0] t; + + wire clk_BUFG1; + wire clk_BUFG2; + wire clk_BUFG3; + wire clk_BUFG4; + + (* KEEP, DONT_TOUCH *) + BUFG bufg1( + .O(clk_BUFG1) + ); + (* KEEP, DONT_TOUCH *) + BUFG bufg2( + .O(clk_BUFG2) + ); + (* KEEP, DONT_TOUCH *) + BUFG bufg3( + .O(clk_BUFG3) + ); + (* KEEP, DONT_TOUCH *) + BUFG bufg4( + .O(clk_BUFG4) + ); + '''.format(n_di=idx)) + + # Always output a LUT6 to make placer happy. + print( + ''' + (* KEEP, DONT_TOUCH *) + LUT6 dummy_lut(); + ''') + + any_idelay = False + + for p in params: + print( + ''' + wire iddr_d_{site}; + + (* KEEP, DONT_TOUCH, LOC = "{site}" *) + IOBUF #( + .IOSTANDARD({IOSTANDARD}) + ) ibuf_{site} ( + .IO({pad_wire}), + .I({owire}), + .O({iwire}), + .T({twire}) + ); + '''.format(**p), + file=connects) + + p['use_iserdese2'] = random.randint(0, 1) + if p['use_iserdese2']: + use_iserdese2(p, luts, connects) + else: + use_direct_and_iddr(p, luts, connects) + + if p['iddr_mux_config'] == 'idelay' or p['mux_config'] == 'idelay': + any_idelay = True + + if any_idelay: + print(""" + (* KEEP, DONT_TOUCH *) + IDELAYCTRL();""") + + for l in luts.create_wires_and_luts(): + print(l) + + print(connects.getvalue()) + + print("endmodule") + + with open('params.jl', 'w') as f: + json.dump(params, f, indent=2) + + +if __name__ == '__main__': + run() diff --git a/fuzzers/035b-iob18-iserdes/Makefile b/fuzzers/035b-iob18-iserdes/Makefile new file mode 100644 index 00000000..e759587c --- /dev/null +++ b/fuzzers/035b-iob18-iserdes/Makefile @@ -0,0 +1,44 @@ +# Copyright (C) 2017-2020 The Project X-Ray Authors. +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC +# +# IOB18 (HP-bank) ISERDES fuzzer for Virtex-7. The kintex7 035b-iob-iserdes +# fuzzer targets IOB33/HR sites that do not exist on this part, so its RIOI +# ISERDES results were transplanted. This variant places ISERDESE2 on real +# IOB18 sites on BOTH the L and R columns and measures the ISERDES config bits +# directly, merging to lioi and rioi (segmaker emits the IOI. prefix, which +# mergedb rewrites per side). +N := 40 +include ../fuzzer.mk + +database: build/segbits_iob18_iserdes.db + +build/segbits_iob18_iserdes.rdb: $(SPECIMENS_OK) + ${XRAY_SEGMATCH} -c 20 -m 1 -M 1 -o build/segbits_iob18_iserdes.rdb2 $$(find -name segdata_*.txt) + # Keep only ISERDES-related solutions (the rest belong to 035-iob18-ilogic). + grep -e ".ISERDES." build/segbits_iob18_iserdes.rdb2 > $@ + grep -e ".IDDR.IN_USE." build/segbits_iob18_iserdes.rdb2 >> $@ || true + +build/segbits_iob18_iserdes.db: build/segbits_iob18_iserdes.rdb + ${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --groups tag_groups.txt --seg-fn-in $^ --seg-fn-out $@ + ${XRAY_MASKMERGE} build/mask_iob18_iserdes.db $$(find -name segdata_*.txt) + +pushdb: + ${XRAY_MERGEDB} lioi build/segbits_iob18_iserdes.db + ${XRAY_MERGEDB} lioi_tbytesrc build/segbits_iob18_iserdes.db + ${XRAY_MERGEDB} lioi_tbyteterm build/segbits_iob18_iserdes.db + ${XRAY_MERGEDB} rioi build/segbits_iob18_iserdes.db + ${XRAY_MERGEDB} rioi_tbytesrc build/segbits_iob18_iserdes.db + ${XRAY_MERGEDB} rioi_tbyteterm build/segbits_iob18_iserdes.db + ${XRAY_MERGEDB} mask_lioi build/mask_iob18_iserdes.db + ${XRAY_MERGEDB} mask_lioi_tbytesrc build/mask_iob18_iserdes.db + ${XRAY_MERGEDB} mask_lioi_tbyteterm build/mask_iob18_iserdes.db + ${XRAY_MERGEDB} mask_rioi build/mask_iob18_iserdes.db + ${XRAY_MERGEDB} mask_rioi_tbytesrc build/mask_iob18_iserdes.db + ${XRAY_MERGEDB} mask_rioi_tbyteterm build/mask_iob18_iserdes.db + +.PHONY: database pushdb diff --git a/fuzzers/035b-iob18-iserdes/bits.dbf b/fuzzers/035b-iob18-iserdes/bits.dbf new file mode 100644 index 00000000..e69de29b diff --git a/fuzzers/035b-iob18-iserdes/generate.py b/fuzzers/035b-iob18-iserdes/generate.py new file mode 100644 index 00000000..c6e5621b --- /dev/null +++ b/fuzzers/035b-iob18-iserdes/generate.py @@ -0,0 +1,284 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +# +# Copyright (C) 2017-2020 The Project X-Ray Authors. +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC +import json + +from prjxray.segmaker import Segmaker +from prjxray import util +from prjxray import verilog + +iface_types = [ + "NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", "MEMORY_QDR" +] + +data_rates = ["SDR", "DDR"] + +data_widths = { + "SDR": [2, 3, 4, 5, 6, 7, 8], + "DDR": [4, 6, 8, 10, 14], +} + + +def run(): + + segmk = Segmaker("design.bits") + + # Load tags + with open("params.json", "r") as fp: + data = json.load(fp) + + loc_to_tile_site_map = {} + + # Output tags + for param_list in data: + for params in param_list: + loc = verilog.unquote(params["SITE_LOC"]) + + get_xy = util.create_xy_fun('IOB_') + x, y = get_xy(loc.replace("ILOGIC", "IOB")) + + loc_to_tile_site_map[loc] = params["TILE_NAME"] + ".IOB_Y%d" % ( + y % 2) + + # Site not used at all + if not params["IS_USED"]: + + segmk.add_site_tag(loc, "ISERDES.SHIFTOUT_USED", 0) + + segmk.add_site_tag(loc, "IDDR_OR_ISERDES.IN_USE", 0) + segmk.add_site_tag(loc, "ISERDES.IN_USE", 0) + segmk.add_site_tag(loc, "IDDR.IN_USE", 0) + + segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0) + segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0) + + for i in iface_types: + if i == "NETWORKING": + for j in data_rates: + for k in data_widths[j]: + tag = "ISERDES.%s.%s.W%s" % (i, j, k) + segmk.add_site_tag(loc, tag, 0) + else: + segmk.add_site_tag(loc, "ISERDES.%s.DDR.W4" % i, 0) + + segmk.add_site_tag(loc, "ISERDES.NUM_CE.N1", 0) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.N2", 0) + + for i in range(1, 4 + 1): + segmk.add_site_tag(loc, "IFF.ZINIT_Q%d" % i, 0) + + for i in range(1, 4 + 1): + segmk.add_site_tag(loc, "IFF.ZSRVAL_Q%d" % i, 0) + + # segmk.add_site_tag(loc, "ISERDES.IS_CLKB_INVERTED", 0) + # segmk.add_site_tag(loc, "ISERDES.IS_CLK_INVERTED", 1) + + segmk.add_site_tag(loc, "ISERDES.DYN_CLKDIV_INV_EN", 0) + segmk.add_site_tag(loc, "ISERDES.DYN_CLK_INV_EN", 0) + + segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0) + segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1) + segmk.add_site_tag(loc, "IDELMUXE3.P0", 0) + segmk.add_site_tag(loc, "IDELMUXE3.P1", 1) + + segmk.add_site_tag(loc, "ISERDES.OFB_USED", 0) + + # Site used as ISERDESE2 + elif verilog.unquote(params["BEL_TYPE"]) == "ISERDESE2": + + segmk.add_site_tag(loc, "IDDR_OR_ISERDES.IN_USE", 1) + segmk.add_site_tag(loc, "ISERDES.IN_USE", 1) + + if "SHIFTOUT_USED" in params: + if params["CHAINED"]: + value = params["SHIFTOUT_USED"] + segmk.add_site_tag(loc, "ISERDES.SHIFTOUT_USED", value) + + if "SERDES_MODE" in params: + value = verilog.unquote(params["SERDES_MODE"]) + if value == "MASTER": + segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 1) + segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 0) + if value == "SLAVE": + segmk.add_site_tag(loc, "ISERDES.MODE.MASTER", 0) + segmk.add_site_tag(loc, "ISERDES.MODE.SLAVE", 1) + + iface_type = verilog.unquote(params["INTERFACE_TYPE"]) + data_rate = verilog.unquote(params["DATA_RATE"]) + data_width = int(params["DATA_WIDTH"]) + + for i in iface_types: + if i == "NETWORKING": + for j in data_rates: + for k in data_widths[j]: + tag = "ISERDES.%s.%s.W%s" % (i, j, k) + + if i == iface_type: + if j == data_rate: + if k == data_width: + segmk.add_site_tag(loc, tag, 1) + else: + if i == iface_type: + segmk.add_site_tag(loc, "ISERDES.%s.DDR.W4" % i, 1) + + if "NUM_CE" in params: + value = params["NUM_CE"] + if value == 1: + segmk.add_site_tag(loc, "ISERDES.NUM_CE.N1", 1) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.N2", 0) + if value == 2: + segmk.add_site_tag(loc, "ISERDES.NUM_CE.N1", 0) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.N2", 1) + + for i in range(1, 4 + 1): + if ("INIT_Q%d" % i) in params: + segmk.add_site_tag( + loc, "IFF.ZINIT_Q%d" % i, + not params["INIT_Q%d" % i]) + + for i in range(1, 4 + 1): + if ("SRVAL_Q%d" % i) in params: + segmk.add_site_tag( + loc, "IFF.ZSRVAL_Q%d" % i, + not params["SRVAL_Q%d" % i]) + + for inv in ["CLK", "CLKB", "OCLK", "OCLKB", "CLKDIV", + "CLKDIVP"]: + if "IS_{}_INVERTED".format(inv) in params: + segmk.add_site_tag( + loc, "ISERDES.INV_{}".format(inv), + params["IS_{}_INVERTED".format(inv)]) + segmk.add_site_tag( + loc, "ISERDES.ZINV_{}".format(inv), + not params["IS_{}_INVERTED".format(inv)]) + + if "DYN_CLKDIV_INV_EN" in params: + value = verilog.unquote(params["DYN_CLKDIV_INV_EN"]) + segmk.add_site_tag( + loc, "ISERDES.DYN_CLKDIV_INV_EN", int(value == "TRUE")) + if "DYN_CLK_INV_EN" in params: + value = verilog.unquote(params["DYN_CLK_INV_EN"]) + segmk.add_site_tag( + loc, "ISERDES.DYN_CLK_INV_EN", int(value == "TRUE")) + + # This parameter actually controls muxes used both in ILOGIC and + # ISERDES mode. + if "IOBDELAY" in params: + value = verilog.unquote(params["IOBDELAY"]) + if value == "NONE": + segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0) + segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1) + segmk.add_site_tag(loc, "IDELMUXE3.P0", 0) + segmk.add_site_tag(loc, "IDELMUXE3.P1", 1) + if value == "IBUF": + segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0) + segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1) + segmk.add_site_tag(loc, "IDELMUXE3.P0", 1) + segmk.add_site_tag(loc, "IDELMUXE3.P1", 0) + if value == "IFD": + segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 0) + segmk.add_site_tag(loc, "IDELMUXE3.P0", 0) + segmk.add_site_tag(loc, "IDELMUXE3.P1", 1) + if value == "BOTH": + segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 0) + segmk.add_site_tag(loc, "IDELMUXE3.P0", 1) + segmk.add_site_tag(loc, "IDELMUXE3.P1", 0) + + if "OFB_USED" in params: + value = verilog.unquote(params["OFB_USED"]) + segmk.add_site_tag( + loc, "ISERDES.OFB_USED", int(value == "TRUE")) + + # Site used as IDDR + elif verilog.unquote(params["BEL_TYPE"]) in ["IDDR", + "IDDR_NO_CLK"]: + segmk.add_site_tag(loc, "IDDR_OR_ISERDES.IN_USE", 1) + segmk.add_site_tag(loc, "IDDR.IN_USE", 1) + segmk.add_site_tag(loc, "ISERDES.IN_USE", 0) + + if "DDR_CLK_EDGE" in params: + value = verilog.unquote(params["DDR_CLK_EDGE"]) + segmk.add_site_tag( + loc, "IFF.DDR_CLK_EDGE.OPPOSITE_EDGE", + int(value == "OPPOSITE_EDGE")) + segmk.add_site_tag( + loc, "IFF.DDR_CLK_EDGE.SAME_EDGE", + int(value == "SAME_EDGE")) + segmk.add_site_tag( + loc, "IFF.DDR_CLK_EDGE.SAME_EDGE_PIPELINED", + int(value == "SAME_EDGE_PIPELINED")) + + if "SRTYPE" in params: + value = verilog.unquote(params["SRTYPE"]) + if value == "ASYNC": + segmk.add_site_tag(loc, "IFF.SRTYPE.ASYNC", 1) + segmk.add_site_tag(loc, "IFF.SRTYPE.SYNC", 0) + if value == "SYNC": + segmk.add_site_tag(loc, "IFF.SRTYPE.ASYNC", 0) + segmk.add_site_tag(loc, "IFF.SRTYPE.SYNC", 1) + + if "IDELMUX" in params: + if params["IDELMUX"] == 1: + segmk.add_site_tag(loc, "IDELMUXE3.P0", 1) + segmk.add_site_tag(loc, "IDELMUXE3.P1", 0) + else: + segmk.add_site_tag(loc, "IDELMUXE3.P0", 0) + segmk.add_site_tag(loc, "IDELMUXE3.P1", 1) + + if "IFFDELMUX" in params: + if params["IFFDELMUX"] == 1: + segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 1) + segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 0) + else: + segmk.add_site_tag(loc, "IFFDELMUXE3.P0", 0) + segmk.add_site_tag(loc, "IFFDELMUXE3.P1", 1) + + for inv in ["C", "D"]: + if "IS_{}_INVERTED".format(inv) in params: + segmk.add_site_tag( + loc, "INV_{}".format(inv), + params["IS_{}_INVERTED".format(inv)]) + segmk.add_site_tag( + loc, "ZINV_{}".format(inv), + not params["IS_{}_INVERTED".format(inv)]) + + segmk.add_site_tag(loc, "ISERDES.NUM_CE.N1", 1) + segmk.add_site_tag(loc, "ISERDES.NUM_CE.N2", 0) + + # Should not happen + else: + print("Unknown BEL_TYPE '{}'".format(params["BEL_TYPE"])) + exit(-1) + + # Write segments and tags for later check + def_tags = {t: 0 for d in segmk.site_tags.values() for t in d.keys()} + + with open("tags.json", "w") as fp: + tags = {} + for l, d in segmk.site_tags.items(): + d1 = dict(def_tags) + d1.update({k: int(v) for k, v in d.items()}) + tags[loc_to_tile_site_map[l]] = d1 + + json.dump(tags, fp, sort_keys=True, indent=1) + + def bitfilter(frame_idx, bit_idx): + if frame_idx < 26 or frame_idx > 29: + return False + return True + + segmk.compile(bitfilter=bitfilter) + segmk.write() + + +if __name__ == "__main__": + run() diff --git a/fuzzers/035b-iob18-iserdes/generate.tcl b/fuzzers/035b-iob18-iserdes/generate.tcl new file mode 100644 index 00000000..f0c151d3 --- /dev/null +++ b/fuzzers/035b-iob18-iserdes/generate.tcl @@ -0,0 +1,45 @@ +# Copyright (C) 2017-2022 The Project X-Ray Authors +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC +create_project -force -part $::env(XRAY_PART) design design +read_verilog top.v +synth_design -top top + +set_property CFGBVS GND [current_design] +set_property CONFIG_VOLTAGE 1.8 [current_design] +set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] +set_param tcl.collectionResultDisplayLimit 0 + +set_property IS_ENABLED 0 [get_drc_checks {NSTD-1}] +set_property IS_ENABLED 0 [get_drc_checks {UCIO-1}] +set_property IS_ENABLED 0 [get_drc_checks {REQP-79}] +set_property IS_ENABLED 0 [get_drc_checks {REQP-81}] +set_property IS_ENABLED 0 [get_drc_checks {REQP-84}] +set_property IS_ENABLED 0 [get_drc_checks {REQP-85}] +set_property IS_ENABLED 0 [get_drc_checks {REQP-87}] +set_property IS_ENABLED 0 [get_drc_checks {REQP-85}] +set_property IS_ENABLED 0 [get_drc_checks {AVAL-28}] +# ISERDES/ILOGIC fuzzer deliberately builds "invalid" clocking and D-inversion +# mux configs to observe their bits; suppress the DRCs that would block bitgen. +set_property IS_ENABLED 0 [get_drc_checks {REQP-105}] +set_property IS_ENABLED 0 [get_drc_checks {PDRC-26}] +set_property IS_ENABLED 0 [get_drc_checks {PDRC-158}] +set_property IS_ENABLED 0 [get_drc_checks {REQP-1580}] +set_property IS_ENABLED 0 [get_drc_checks {REQP-1581}] +set_property IS_ENABLED 0 [get_drc_checks {REQP-1582}] +# ISERDESE2-specific DRCs (CLK/CLKDIV topology) the iserdes fuzzer must bypass. +set_property IS_ENABLED 0 [get_drc_checks {NDRV-1}] +set_property IS_ENABLED 0 [get_drc_checks {REQP-98}] +set_property IS_ENABLED 0 [get_drc_checks {REQP-103}] +set_property IS_ENABLED 0 [get_drc_checks {REQP-109}] +set_property IS_ENABLED 0 [get_drc_checks {REQP-111}] + +place_design +route_design + +write_checkpoint -force design.dcp +write_bitstream -force design.bit diff --git a/fuzzers/035b-iob18-iserdes/params.json b/fuzzers/035b-iob18-iserdes/params.json new file mode 100644 index 00000000..b79b2a07 --- /dev/null +++ b/fuzzers/035b-iob18-iserdes/params.json @@ -0,0 +1,11906 @@ +[ + [ + { + "BEL_TYPE": "\"ISERDESE2\"", + "CHAINED": 0, + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "IDELAY_LOC": "\"IDELAY_X0Y2\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "IOBDELAY": "\"IFD\"", + "IS_CLKB_INVERTED": 1, + "IS_CLKDIVP_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_CLK_INVERTED": 1, + "IS_D_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_USED": 1, + "NUM_CE": 1, + "OFB_USED": "\"FALSE\"", + "SERDES_MODE": "\"SLAVE\"", + "SITE_LOC": "\"ILOGIC_X0Y2\"", + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "TILE_NAME": "LIOB18_X81Y2", + "USE_IDELAY": 0 + }, + { + "IDELAY_LOC": "\"IDELAY_X0Y1\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X0Y1\"", + "TILE_NAME": "LIOB18_X81Y2" + } + ], + [ + { + "BEL_TYPE": "\"ISERDESE2\"", + "CHAINED": 0, + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "IDELAY_LOC": "\"IDELAY_X0Y3\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "IOBDELAY": "\"BOTH\"", + "IS_CLKB_INVERTED": 0, + "IS_CLKDIVP_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_CLK_INVERTED": 0, + "IS_D_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_USED": 1, + "NUM_CE": 2, + "OFB_USED": "\"FALSE\"", + "SERDES_MODE": "\"MASTER\"", + "SITE_LOC": "\"ILOGIC_X0Y3\"", + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "TILE_NAME": "LIOB18_X81Y4", + "USE_IDELAY": 1 + }, + { + "IDELAY_LOC": "\"IDELAY_X0Y4\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X0Y4\"", + "TILE_NAME": "LIOB18_X81Y4" + } + ], + [ + { + "BEL_TYPE": "\"ISERDESE2\"", + "CHAINED": 0, + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "IDELAY_LOC": "\"IDELAY_X0Y6\"", + "INIT_Q1": 1, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "IOBDELAY": "\"BOTH\"", + "IS_CLKB_INVERTED": 1, + "IS_CLKDIVP_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_CLK_INVERTED": 0, + "IS_D_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_USED": 1, + "NUM_CE": 2, + "OFB_USED": "\"FALSE\"", + "SERDES_MODE": "\"SLAVE\"", + "SITE_LOC": "\"ILOGIC_X0Y6\"", + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "TILE_NAME": "LIOB18_X81Y6", + "USE_IDELAY": 0 + }, + { + "IDELAY_LOC": "\"IDELAY_X0Y5\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X0Y5\"", + "TILE_NAME": "LIOB18_X81Y6" + } + ], + [ + { + "BEL_TYPE": "\"IDDR\"", + "CE1USED": 0, + "CHAINED": 0, + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"", + "IDELAY_LOC": "\"IDELAY_X0Y8\"", + "IDELMUX": 1, + "IFFDELMUX": 1, + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "IS_USED": 1, + "SITE_LOC": "\"ILOGIC_X0Y8\"", + "SRTYPE": "\"ASYNC\"", + "SR_MODE": "\"NONE\"", + "TILE_NAME": "LIOB18_X81Y8", + "USE_IDELAY": 1 + }, + { + "IDELAY_LOC": "\"IDELAY_X0Y7\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X0Y7\"", + "TILE_NAME": "LIOB18_X81Y8" + } + ], + [ + { + "BEL_TYPE": "\"IDDR\"", + "CE1USED": 1, + "CHAINED": 0, + "DDR_CLK_EDGE": "\"SAME_EDGE\"", + "IDELAY_LOC": "\"IDELAY_X0Y9\"", + "IDELMUX": 0, + "IFFDELMUX": 1, + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "IS_USED": 1, + "SITE_LOC": "\"ILOGIC_X0Y9\"", + "SRTYPE": "\"SYNC\"", + "SR_MODE": "\"RST\"", + "TILE_NAME": "LIOB18_X81Y10", + "USE_IDELAY": 1 + }, + { + "IDELAY_LOC": "\"IDELAY_X0Y10\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X0Y10\"", + "TILE_NAME": "LIOB18_X81Y10" + } + ], + [ + { + "BEL_TYPE": "\"IDDR_NO_CLK\"", + "CE1USED": 1, + "CHAINED": 0, + "DDR_CLK_EDGE": "\"SAME_EDGE\"", + "IDELAY_LOC": "\"IDELAY_X0Y12\"", + "IDELMUX": 0, + "IFFDELMUX": 0, + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "IS_USED": 1, + "SITE_LOC": "\"ILOGIC_X0Y12\"", + "SRTYPE": "\"ASYNC\"", + "SR_MODE": "\"RST\"", + "TILE_NAME": "LIOB18_X81Y12", + "USE_IDELAY": 0 + }, + { + "IDELAY_LOC": "\"IDELAY_X0Y11\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X0Y11\"", + "TILE_NAME": "LIOB18_X81Y12" + } + ], + [ + { + "BEL_TYPE": "\"IDDR_NO_CLK\"", + "CE1USED": 0, + "CHAINED": 0, + "DDR_CLK_EDGE": "\"SAME_EDGE\"", + "IDELAY_LOC": "\"IDELAY_X0Y13\"", + "IDELMUX": 0, + "IFFDELMUX": 0, + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "IS_USED": 1, + "SITE_LOC": "\"ILOGIC_X0Y13\"", + "SRTYPE": "\"SYNC\"", + "SR_MODE": "\"SET\"", + "TILE_NAME": "LIOB18_X81Y14", + "USE_IDELAY": 0 + }, + { + "IDELAY_LOC": "\"IDELAY_X0Y14\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X0Y14\"", + "TILE_NAME": "LIOB18_X81Y14" + } + ], + [ + { + "BEL_TYPE": "\"IDDR\"", + "CE1USED": 1, + "CHAINED": 0, + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"", + "IDELAY_LOC": "\"IDELAY_X0Y15\"", + "IDELMUX": 0, + "IFFDELMUX": 1, + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "IS_USED": 1, + "SITE_LOC": "\"ILOGIC_X0Y15\"", + "SRTYPE": "\"SYNC\"", + "SR_MODE": "\"NONE\"", + "TILE_NAME": "LIOB18_X81Y16", + "USE_IDELAY": 1 + }, + { + "IDELAY_LOC": "\"IDELAY_X0Y16\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X0Y16\"", + "TILE_NAME": "LIOB18_X81Y16" + } + ], + [ + { + "BEL_TYPE": "\"ISERDESE2\"", + "CHAINED": 0, + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "IDELAY_LOC": "\"IDELAY_X0Y18\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "IOBDELAY": "\"IBUF\"", + "IS_CLKB_INVERTED": 0, + "IS_CLKDIVP_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_CLK_INVERTED": 0, + "IS_D_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_USED": 1, + "NUM_CE": 1, + "OFB_USED": "\"FALSE\"", + "SERDES_MODE": "\"MASTER\"", + "SITE_LOC": "\"ILOGIC_X0Y18\"", + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "TILE_NAME": "LIOB18_X81Y18", + "USE_IDELAY": 0 + }, + { + "IDELAY_LOC": "\"IDELAY_X0Y17\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X0Y17\"", + "TILE_NAME": "LIOB18_X81Y18" + } + ], + [ + { + "BEL_TYPE": "\"ISERDESE2\"", + "CHAINED": 0, + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "IDELAY_LOC": "\"IDELAY_X0Y20\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "IOBDELAY": "\"IBUF\"", + "IS_CLKB_INVERTED": 1, + "IS_CLKDIVP_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_CLK_INVERTED": 0, + "IS_D_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_USED": 1, + "NUM_CE": 2, + "OFB_USED": "\"FALSE\"", + "SERDES_MODE": "\"MASTER\"", + "SITE_LOC": "\"ILOGIC_X0Y20\"", + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "TILE_NAME": "LIOB18_X81Y20", + "USE_IDELAY": 1 + }, + { + "IDELAY_LOC": "\"IDELAY_X0Y19\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X0Y19\"", + "TILE_NAME": "LIOB18_X81Y20" + } + ], + [ + { + "BEL_TYPE": "\"ISERDESE2\"", + "CHAINED": 0, + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "IDELAY_LOC": "\"IDELAY_X0Y21\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "INTERFACE_TYPE": "\"MEMORY_QDR\"", + "IOBDELAY": "\"NONE\"", + "IS_CLKB_INVERTED": 1, + "IS_CLKDIVP_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_CLK_INVERTED": 1, + "IS_D_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 1, + "IS_USED": 1, + "NUM_CE": 2, + "OFB_USED": "\"FALSE\"", + "SERDES_MODE": "\"SLAVE\"", + "SITE_LOC": "\"ILOGIC_X0Y21\"", + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "TILE_NAME": "LIOB18_X81Y22", + "USE_IDELAY": 1 + }, + { + "IDELAY_LOC": "\"IDELAY_X0Y22\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X0Y22\"", + "TILE_NAME": "LIOB18_X81Y22" + } + ], + [ + { + "BEL_TYPE": "\"ISERDESE2\"", + "CHAINED": 0, + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "IDELAY_LOC": "\"IDELAY_X0Y23\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 1, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "IOBDELAY": "\"BOTH\"", + "IS_CLKB_INVERTED": 1, + "IS_CLKDIVP_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_CLK_INVERTED": 1, + "IS_D_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_USED": 1, + "NUM_CE": 1, + "OFB_USED": "\"FALSE\"", + "SERDES_MODE": "\"MASTER\"", + "SITE_LOC": "\"ILOGIC_X0Y23\"", + "SRVAL_Q1": 0, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "TILE_NAME": "LIOB18_X81Y24", + "USE_IDELAY": 0 + }, + { + "IDELAY_LOC": "\"IDELAY_X0Y24\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X0Y24\"", + "TILE_NAME": "LIOB18_X81Y24" + } + ], + [ + { + "BEL_TYPE": "\"ISERDESE2\"", + "CHAINED": 0, + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 8, + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "IDELAY_LOC": "\"IDELAY_X0Y26\"", + "INIT_Q1": 1, + "INIT_Q2": 1, + "INIT_Q3": 1, + "INIT_Q4": 0, + "INTERFACE_TYPE": "\"NETWORKING\"", + "IOBDELAY": "\"IFD\"", + "IS_CLKB_INVERTED": 0, + "IS_CLKDIVP_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_CLK_INVERTED": 1, + "IS_D_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_USED": 1, + "NUM_CE": 1, + "OFB_USED": "\"FALSE\"", + "SERDES_MODE": "\"MASTER\"", + "SITE_LOC": "\"ILOGIC_X0Y26\"", + "SRVAL_Q1": 1, + "SRVAL_Q2": 1, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "TILE_NAME": "LIOB18_X81Y27", + "USE_IDELAY": 1 + }, + { + "IDELAY_LOC": "\"IDELAY_X0Y25\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X0Y25\"", + "TILE_NAME": "LIOB18_X81Y27" + } + ], + [ + { + "BEL_TYPE": "\"IDDR\"", + "CE1USED": 1, + "CHAINED": 0, + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"", + "IDELAY_LOC": "\"IDELAY_X0Y28\"", + "IDELMUX": 1, + "IFFDELMUX": 1, + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "IS_USED": 1, + "SITE_LOC": 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"RIOB18_X312Y322", + "USE_IDELAY": 0 + }, + { + "IDELAY_LOC": "\"IDELAY_X1Y309\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X1Y309\"", + "TILE_NAME": "RIOB18_X312Y322" + } + ], + [ + { + "BEL_TYPE": "\"IDDR_NO_CLK\"", + "CE1USED": 1, + "CHAINED": 0, + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"", + "IDELAY_LOC": "\"IDELAY_X1Y311\"", + "IDELMUX": 0, + "IFFDELMUX": 0, + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "IS_USED": 1, + "SITE_LOC": "\"ILOGIC_X1Y311\"", + "SRTYPE": "\"SYNC\"", + "SR_MODE": "\"SET\"", + "TILE_NAME": "RIOB18_X312Y324", + "USE_IDELAY": 0 + }, + { + "IDELAY_LOC": "\"IDELAY_X1Y312\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X1Y312\"", + "TILE_NAME": "RIOB18_X312Y324" + } + ], + [ + { + "BEL_TYPE": "\"IDDR\"", + "CE1USED": 0, + "CHAINED": 0, + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"", + "IDELAY_LOC": "\"IDELAY_X1Y313\"", + "IDELMUX": 0, + "IFFDELMUX": 0, + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "IS_USED": 1, + "SITE_LOC": "\"ILOGIC_X1Y313\"", + "SRTYPE": "\"SYNC\"", + "SR_MODE": "\"NONE\"", + "TILE_NAME": "RIOB18_X312Y326", + "USE_IDELAY": 0 + }, + { + "IDELAY_LOC": "\"IDELAY_X1Y314\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X1Y314\"", + "TILE_NAME": "RIOB18_X312Y326" + } + ], + [ + { + "BEL_TYPE": "\"IDDR_NO_CLK\"", + "CE1USED": 0, + "CHAINED": 0, + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"", + "IDELAY_LOC": "\"IDELAY_X1Y316\"", + "IDELMUX": 1, + "IFFDELMUX": 1, + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "IS_USED": 1, + "SITE_LOC": "\"ILOGIC_X1Y316\"", + "SRTYPE": "\"SYNC\"", + "SR_MODE": "\"RST\"", + "TILE_NAME": "RIOB18_X312Y328", + "USE_IDELAY": 1 + }, + { + "IDELAY_LOC": "\"IDELAY_X1Y315\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X1Y315\"", + "TILE_NAME": "RIOB18_X312Y328" + } + ], + [ + { + "BEL_TYPE": "\"IDDR_NO_CLK\"", + "CE1USED": 0, + "CHAINED": 0, + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"", + "IDELAY_LOC": "\"IDELAY_X1Y318\"", + "IDELMUX": 1, + "IFFDELMUX": 1, + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "IS_USED": 1, + "SITE_LOC": "\"ILOGIC_X1Y318\"", + "SRTYPE": "\"ASYNC\"", + "SR_MODE": "\"NONE\"", + "TILE_NAME": "RIOB18_X312Y330", + "USE_IDELAY": 1 + }, + { + "IDELAY_LOC": "\"IDELAY_X1Y317\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X1Y317\"", + "TILE_NAME": "RIOB18_X312Y330" + } + ], + [ + { + "IDELAY_LOC": "\"IDELAY_X1Y320\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X1Y320\"", + "TILE_NAME": "RIOB18_X312Y332" + }, + { + "IDELAY_LOC": "\"IDELAY_X1Y319\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X1Y319\"", + "TILE_NAME": "RIOB18_X312Y332" + } + ], + [ + { + "BEL_TYPE": "\"IDDR\"", + "CE1USED": 1, + "CHAINED": 0, + "DDR_CLK_EDGE": "\"SAME_EDGE\"", + "IDELAY_LOC": "\"IDELAY_X1Y322\"", + "IDELMUX": 0, + "IFFDELMUX": 0, + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "IS_USED": 1, + "SITE_LOC": "\"ILOGIC_X1Y322\"", + "SRTYPE": "\"SYNC\"", + "SR_MODE": "\"NONE\"", + "TILE_NAME": "RIOB18_X312Y334", + "USE_IDELAY": 0 + }, + { + "IDELAY_LOC": "\"IDELAY_X1Y321\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X1Y321\"", + "TILE_NAME": "RIOB18_X312Y334" + } + ], + [ + { + "BEL_TYPE": "\"ISERDESE2\"", + "CHAINED": 0, + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 5, + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "IDELAY_LOC": "\"IDELAY_X1Y323\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 1, + "INIT_Q4": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "IOBDELAY": "\"IFD\"", + "IS_CLKB_INVERTED": 0, + "IS_CLKDIVP_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_CLK_INVERTED": 0, + "IS_D_INVERTED": 0, + "IS_OCLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_USED": 1, + "NUM_CE": 1, + "OFB_USED": "\"FALSE\"", + "SERDES_MODE": "\"SLAVE\"", + "SITE_LOC": "\"ILOGIC_X1Y323\"", + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 0, + "TILE_NAME": "RIOB18_X312Y336", + "USE_IDELAY": 0 + }, + { + "IDELAY_LOC": "\"IDELAY_X1Y324\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X1Y324\"", + "TILE_NAME": "RIOB18_X312Y336" + } + ], + [ + { + "BEL_TYPE": "\"ISERDESE2\"", + "CHAINED": 0, + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "IDELAY_LOC": "\"IDELAY_X1Y326\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "IOBDELAY": "\"IBUF\"", + "IS_CLKB_INVERTED": 0, + "IS_CLKDIVP_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_CLK_INVERTED": 0, + "IS_D_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_USED": 1, + "NUM_CE": 2, + "OFB_USED": "\"FALSE\"", + "SERDES_MODE": "\"SLAVE\"", + "SITE_LOC": "\"ILOGIC_X1Y326\"", + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "TILE_NAME": "RIOB18_X312Y339", + "USE_IDELAY": 0 + }, + { + "IDELAY_LOC": "\"IDELAY_X1Y325\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X1Y325\"", + "TILE_NAME": "RIOB18_X312Y339" + } + ], + [ + { + "BEL_TYPE": "\"ISERDESE2\"", + "CHAINED": 0, + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "IDELAY_LOC": "\"IDELAY_X1Y328\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "IOBDELAY": "\"NONE\"", + "IS_CLKB_INVERTED": 0, + "IS_CLKDIVP_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_CLK_INVERTED": 0, + "IS_D_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_USED": 1, + "NUM_CE": 2, + "OFB_USED": "\"TRUE\"", + "SERDES_MODE": "\"SLAVE\"", + "SITE_LOC": "\"ILOGIC_X1Y328\"", + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 0, + "TILE_NAME": "RIOB18_X312Y341", + "USE_IDELAY": 1 + }, + { + "IDELAY_LOC": "\"IDELAY_X1Y327\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X1Y327\"", + "TILE_NAME": "RIOB18_X312Y341" + } + ], + [ + { + "IDELAY_LOC": "\"IDELAY_X1Y330\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X1Y330\"", + "TILE_NAME": "RIOB18_X312Y343" + }, + { + "IDELAY_LOC": "\"IDELAY_X1Y329\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X1Y329\"", + "TILE_NAME": "RIOB18_X312Y343" + } + ], + [ + { + "BEL_TYPE": "\"IDDR\"", + "CE1USED": 1, + "CHAINED": 0, + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"", + "IDELAY_LOC": "\"IDELAY_X1Y331\"", + "IDELMUX": 0, + "IFFDELMUX": 0, + "INIT_Q1": 0, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 1, + "IS_USED": 1, + "SITE_LOC": "\"ILOGIC_X1Y331\"", + "SRTYPE": "\"SYNC\"", + "SR_MODE": "\"SET\"", + "TILE_NAME": "RIOB18_X312Y345", + "USE_IDELAY": 1 + }, + { + "IDELAY_LOC": "\"IDELAY_X1Y332\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X1Y332\"", + "TILE_NAME": "RIOB18_X312Y345" + } + ], + [ + { + "BEL_TYPE": "\"IDDR\"", + "CE1USED": 0, + "CHAINED": 0, + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"", + "IDELAY_LOC": "\"IDELAY_X1Y333\"", + "IDELMUX": 0, + "IFFDELMUX": 0, + "INIT_Q1": 0, + "INIT_Q2": 1, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "IS_USED": 1, + "SITE_LOC": "\"ILOGIC_X1Y333\"", + "SRTYPE": "\"SYNC\"", + "SR_MODE": "\"NONE\"", + "TILE_NAME": "RIOB18_X312Y347", + "USE_IDELAY": 0 + }, + { + "IDELAY_LOC": "\"IDELAY_X1Y334\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X1Y334\"", + "TILE_NAME": "RIOB18_X312Y347" + } + ], + [ + { + "BEL_TYPE": "\"ISERDESE2\"", + "CHAINED": 0, + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "IDELAY_LOC": "\"IDELAY_X1Y335\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "INTERFACE_TYPE": "\"MEMORY\"", + "IOBDELAY": "\"IBUF\"", + "IS_CLKB_INVERTED": 0, + "IS_CLKDIVP_INVERTED": 1, + "IS_CLKDIV_INVERTED": 0, + "IS_CLK_INVERTED": 1, + "IS_D_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 1, + "IS_USED": 1, + "NUM_CE": 2, + "OFB_USED": "\"FALSE\"", + "SERDES_MODE": "\"MASTER\"", + "SITE_LOC": "\"ILOGIC_X1Y335\"", + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "TILE_NAME": "RIOB18_X312Y349", + "USE_IDELAY": 0 + }, + { + "IDELAY_LOC": "\"IDELAY_X1Y336\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X1Y336\"", + "TILE_NAME": "RIOB18_X312Y349" + } + ], + [ + { + "BEL_TYPE": "\"ISERDESE2\"", + "CHAINED": 0, + "DATA_RATE": "\"DDR\"", + "DATA_WIDTH": 4, + "DYN_CLKDIV_INV_EN": "\"FALSE\"", + "DYN_CLK_INV_EN": "\"TRUE\"", + "IDELAY_LOC": "\"IDELAY_X1Y338\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 0, + "INTERFACE_TYPE": "\"OVERSAMPLE\"", + "IOBDELAY": "\"IBUF\"", + "IS_CLKB_INVERTED": 0, + "IS_CLKDIVP_INVERTED": 1, + "IS_CLKDIV_INVERTED": 1, + "IS_CLK_INVERTED": 1, + "IS_D_INVERTED": 0, + "IS_OCLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_USED": 1, + "NUM_CE": 2, + "OFB_USED": "\"FALSE\"", + "SERDES_MODE": "\"MASTER\"", + "SITE_LOC": "\"ILOGIC_X1Y338\"", + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 1, + "SRVAL_Q4": 1, + "TILE_NAME": "RIOB18_X312Y351", + "USE_IDELAY": 0 + }, + { + "IDELAY_LOC": "\"IDELAY_X1Y337\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X1Y337\"", + "TILE_NAME": "RIOB18_X312Y351" + } + ], + [ + { + "BEL_TYPE": "\"IDDR_NO_CLK\"", + "CE1USED": 0, + "CHAINED": 0, + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"", + "IDELAY_LOC": "\"IDELAY_X1Y340\"", + "IDELMUX": 1, + "IFFDELMUX": 1, + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 1, + "IS_USED": 1, + "SITE_LOC": "\"ILOGIC_X1Y340\"", + "SRTYPE": "\"ASYNC\"", + "SR_MODE": "\"SET\"", + "TILE_NAME": "RIOB18_X312Y353", + "USE_IDELAY": 1 + }, + { + "IDELAY_LOC": "\"IDELAY_X1Y339\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X1Y339\"", + "TILE_NAME": "RIOB18_X312Y353" + } + ], + [ + { + "BEL_TYPE": "\"ISERDESE2\"", + "CHAINED": 0, + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 4, + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "IDELAY_LOC": "\"IDELAY_X1Y341\"", + "INIT_Q1": 0, + "INIT_Q2": 1, + "INIT_Q3": 0, + "INIT_Q4": 0, + "INTERFACE_TYPE": "\"MEMORY_DDR3\"", + "IOBDELAY": "\"IFD\"", + "IS_CLKB_INVERTED": 1, + "IS_CLKDIVP_INVERTED": 0, + "IS_CLKDIV_INVERTED": 1, + "IS_CLK_INVERTED": 0, + "IS_D_INVERTED": 1, + "IS_OCLKB_INVERTED": 1, + "IS_OCLK_INVERTED": 0, + "IS_USED": 1, + "NUM_CE": 2, + "OFB_USED": "\"FALSE\"", + "SERDES_MODE": "\"MASTER\"", + "SITE_LOC": "\"ILOGIC_X1Y341\"", + "SRVAL_Q1": 0, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "TILE_NAME": "RIOB18_X312Y355", + "USE_IDELAY": 0 + }, + { + "IDELAY_LOC": "\"IDELAY_X1Y342\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X1Y342\"", + "TILE_NAME": "RIOB18_X312Y355" + } + ], + [ + { + "BEL_TYPE": "\"ISERDESE2\"", + "CHAINED": 0, + "DATA_RATE": "\"SDR\"", + "DATA_WIDTH": 2, + "DYN_CLKDIV_INV_EN": "\"TRUE\"", + "DYN_CLK_INV_EN": "\"FALSE\"", + "IDELAY_LOC": "\"IDELAY_X1Y344\"", + "INIT_Q1": 0, + "INIT_Q2": 0, + "INIT_Q3": 0, + "INIT_Q4": 1, + "INTERFACE_TYPE": "\"NETWORKING\"", + "IOBDELAY": "\"NONE\"", + "IS_CLKB_INVERTED": 0, + "IS_CLKDIVP_INVERTED": 0, + "IS_CLKDIV_INVERTED": 0, + "IS_CLK_INVERTED": 1, + "IS_D_INVERTED": 1, + "IS_OCLKB_INVERTED": 0, + "IS_OCLK_INVERTED": 0, + "IS_USED": 1, + "NUM_CE": 1, + "OFB_USED": "\"FALSE\"", + "SERDES_MODE": "\"MASTER\"", + "SITE_LOC": "\"ILOGIC_X1Y344\"", + "SRVAL_Q1": 1, + "SRVAL_Q2": 0, + "SRVAL_Q3": 0, + "SRVAL_Q4": 1, + "TILE_NAME": "RIOB18_X312Y357", + "USE_IDELAY": 0 + }, + { + "IDELAY_LOC": "\"IDELAY_X1Y343\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X1Y343\"", + "TILE_NAME": "RIOB18_X312Y357" + } + ], + [ + { + "BEL_TYPE": "\"IDDR_NO_CLK\"", + "CE1USED": 0, + "CHAINED": 0, + "DDR_CLK_EDGE": "\"SAME_EDGE_PIPELINED\"", + "IDELAY_LOC": "\"IDELAY_X1Y345\"", + "IDELMUX": 1, + "IFFDELMUX": 1, + "INIT_Q1": 1, + "INIT_Q2": 1, + "IS_C_INVERTED": 1, + "IS_D_INVERTED": 0, + "IS_USED": 1, + "SITE_LOC": "\"ILOGIC_X1Y345\"", + "SRTYPE": "\"SYNC\"", + "SR_MODE": "\"SET\"", + "TILE_NAME": "RIOB18_X312Y359", + "USE_IDELAY": 1 + }, + { + "IDELAY_LOC": "\"IDELAY_X1Y346\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X1Y346\"", + "TILE_NAME": "RIOB18_X312Y359" + } + ], + [ + { + "BEL_TYPE": "\"IDDR\"", + "CE1USED": 0, + "CHAINED": 0, + "DDR_CLK_EDGE": "\"OPPOSITE_EDGE\"", + "IDELAY_LOC": "\"IDELAY_X1Y347\"", + "IDELMUX": 0, + "IFFDELMUX": 1, + "INIT_Q1": 1, + "INIT_Q2": 0, + "IS_C_INVERTED": 0, + "IS_D_INVERTED": 0, + "IS_USED": 1, + "SITE_LOC": "\"ILOGIC_X1Y347\"", + "SRTYPE": "\"SYNC\"", + "SR_MODE": "\"SET\"", + "TILE_NAME": "RIOB18_X312Y361", + "USE_IDELAY": 1 + }, + { + "IDELAY_LOC": "\"IDELAY_X1Y348\"", + "IS_USED": 0, + "SITE_LOC": "\"ILOGIC_X1Y348\"", + "TILE_NAME": "RIOB18_X312Y361" + } + ] +] \ No newline at end of file diff --git a/fuzzers/035b-iob18-iserdes/tag_groups.txt b/fuzzers/035b-iob18-iserdes/tag_groups.txt new file mode 100644 index 00000000..79a46d2e --- /dev/null +++ b/fuzzers/035b-iob18-iserdes/tag_groups.txt @@ -0,0 +1,11 @@ +IOI.ILOGIC_Y0.ISERDES.MEMORY.DDR.W4 IOI.ILOGIC_Y0.ISERDES.MEMORY_DDR.W.DDR.W4 IOI.ILOGIC_Y0.ISERDES.MEMORY_QDR.DDR.W4 IOI.ILOGIC_Y0.ISERDES.NETWORKING.DDR.W10 IOI.ILOGIC_Y0.ISERDES.NETWORKING.DDR.W14 IOI.ILOGIC_Y0.ISERDES.NETWORKING.DDR.W4 IOI.ILOGIC_Y0.ISERDES.NETWORKING.DDR.W6 IOI.ILOGIC_Y0.ISERDES.NETWORKING.DDR.W8 IOI.ILOGIC_Y0.ISERDES.NETWORKING.SDR.W2 IOI.ILOGIC_Y0.ISERDES.NETWORKING.SDR.W3 IOI.ILOGIC_Y0.ISERDES.NETWORKING.SDR.W4 IOI.ILOGIC_Y0.ISERDES.NETWORKING.SDR.W5 IOI.ILOGIC_Y0.ISERDES.NETWORKING.SDR.W6 IOI.ILOGIC_Y0.ISERDES.NETWORKING.SDR.W7 IOI.ILOGIC_Y0.ISERDES.NETWORKING.SDR.W8 IOI.ILOGIC_Y0.ISERDES.OVERSAMPLE.DDR.W4 + +IOI.ILOGIC_Y0.ISERDES.MODE.MASTER IOI.ILOGIC_Y0.ISERDES.MODE.SLAVE + +IOI.ILOGIC_Y0.ISERDES.NUM_CE.N1 IOI.ILOGIC_Y0.ISERDES.NUM_CE.N2 + +IOI.ILOGIC_Y1.ISERDES.MEMORY.DDR.W4 IOI.ILOGIC_Y1.ISERDES.MEMORY_DDR.W.DDR.W4 IOI.ILOGIC_Y1.ISERDES.MEMORY_QDR.DDR.W4 IOI.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W10 IOI.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W14 IOI.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W4 IOI.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W6 IOI.ILOGIC_Y1.ISERDES.NETWORKING.DDR.W8 IOI.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W2 IOI.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W3 IOI.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W4 IOI.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W5 IOI.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W6 IOI.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W7 IOI.ILOGIC_Y1.ISERDES.NETWORKING.SDR.W8 IOI.ILOGIC_Y1.ISERDES.OVERSAMPLE.DDR.W4 + +IOI.ILOGIC_Y1.ISERDES.MODE.MASTER IOI.ILOGIC_Y1.ISERDES.MODE.SLAVE + +IOI.ILOGIC_Y1.ISERDES.NUM_CE.N1 IOI.ILOGIC_Y1.ISERDES.NUM_CE.N2 diff --git a/fuzzers/035b-iob18-iserdes/top.py b/fuzzers/035b-iob18-iserdes/top.py new file mode 100644 index 00000000..639421c5 --- /dev/null +++ b/fuzzers/035b-iob18-iserdes/top.py @@ -0,0 +1,496 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +# +# Copyright (C) 2017-2020 The Project X-Ray Authors. +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC +import os, random +random.seed(int(os.getenv("SEED"), 16)) + +import json + +from prjxray import util +from prjxray import verilog +from prjxray.db import Database + +# ============================================================================= + + +def gen_sites(): + db = Database(util.get_db_root(), util.get_part()) + grid = db.grid() + + tile_list = [] + for tile_name in sorted(grid.tiles()): + if "IOB18" not in tile_name or "SING" in tile_name: + continue + tile_list.append(tile_name) + + get_xy = util.create_xy_fun('[LR]IOB18_') + tile_list.sort(key=get_xy) + + for iob_tile_name in tile_list: + iob_gridinfo = grid.gridinfo_at_loc( + grid.loc_of_tilename(iob_tile_name)) + + iob33s = [k for k, v in iob_gridinfo.sites.items() if v == "IOB18S"][0] + iob33m = [k for k, v in iob_gridinfo.sites.items() if v == "IOB18M"][0] + + top_sites = { + "IOB": iob33m, + "ILOGIC": iob33m.replace("IOB", "ILOGIC"), + "IDELAY": iob33m.replace("IOB", "IDELAY"), + } + + bot_sites = { + "IOB": iob33s, + "ILOGIC": iob33s.replace("IOB", "ILOGIC"), + "IDELAY": iob33s.replace("IOB", "IDELAY"), + } + + yield iob_tile_name, top_sites, bot_sites + + +def gen_iserdes(loc): + + # Site params + params = { + "SITE_LOC": verilog.quote(loc), + "USE_IDELAY": random.randint(0, 1), + "BEL_TYPE": verilog.quote("ISERDESE2"), + "INIT_Q1": random.randint(0, 1), + "INIT_Q2": random.randint(0, 1), + "INIT_Q3": random.randint(0, 1), + "INIT_Q4": random.randint(0, 1), + "SRVAL_Q1": random.randint(0, 1), + "SRVAL_Q2": random.randint(0, 1), + "SRVAL_Q3": random.randint(0, 1), + "SRVAL_Q4": random.randint(0, 1), + "NUM_CE": random.randint(1, 2), + + # The following one shows negative correlation (0 - not inverted) + "IS_D_INVERTED": random.randint(0, 1), + + # No bits were found for parameters below + "IS_OCLKB_INVERTED": random.randint(0, 1), + "IS_OCLK_INVERTED": random.randint(0, 1), + "IS_CLKDIVP_INVERTED": random.randint(0, 1), + "IS_CLKDIV_INVERTED": random.randint(0, 1), + "IS_CLKB_INVERTED": random.randint(0, 1), + "IS_CLK_INVERTED": random.randint(0, 1), + "DYN_CLKDIV_INV_EN": verilog.quote(random.choice(["TRUE", "FALSE"])), + "DYN_CLK_INV_EN": verilog.quote(random.choice(["TRUE", "FALSE"])), + "IOBDELAY": verilog.quote( + random.choice(["NONE", "IBUF", "IFD", "BOTH"])), + "OFB_USED": verilog.quote( + random.choice(["TRUE"] + ["FALSE"] * 9)), # Force more FALSEs + } + + iface_type = random.choice( + ["NETWORKING", "OVERSAMPLE", "MEMORY", "MEMORY_DDR3", "MEMORY_QDR"]) + data_rate = random.choice(["SDR", "DDR"]) + serdes_mode = random.choice(["MASTER", "SLAVE"]) + + params["INTERFACE_TYPE"] = verilog.quote(iface_type) + params["DATA_RATE"] = verilog.quote(data_rate) + params["SERDES_MODE"] = verilog.quote(serdes_mode) + + # Networking mode + if iface_type == "NETWORKING": + data_widths = { + "SDR": [2, 3, 4, 5, 6, 7, 8], + "DDR": [4, 6, 8, 10, 14], + } + params["DATA_WIDTH"] = random.choice(data_widths[data_rate]) + + # Others + else: + params["DATA_WIDTH"] = 4 + + if verilog.unquote(params["OFB_USED"]) == "TRUE": + params["IOBDELAY"] = verilog.quote("NONE") + + return params + + +def gen_iddr(loc): + + # Site params + params = { + "SITE_LOC": + verilog.quote(loc), + "USE_IDELAY": + random.randint(0, 1), + "BEL_TYPE": + verilog.quote(random.choice(["IDDR", "IDDR_NO_CLK"])), + "INIT_Q1": + random.randint(0, 1), + "INIT_Q2": + random.randint(0, 1), + "SRTYPE": + verilog.quote(random.choice(["ASYNC", "SYNC"])), + "DDR_CLK_EDGE": + verilog.quote( + random.choice( + ["OPPOSITE_EDGE", "SAME_EDGE", "SAME_EDGE_PIPELINED"])), + "CE1USED": + random.randint(0, 1), + "SR_MODE": + verilog.quote(random.choice(["NONE", "SET", "RST"])), + "IS_C_INVERTED": + random.randint(0, 1), + "IS_D_INVERTED": + random.randint(0, 1), + } + + if params["USE_IDELAY"]: + params["IDELMUX"] = random.randint(0, 1) + params["IFFDELMUX"] = random.randint(0, 1) + else: + params["IDELMUX"] = 0 + params["IFFDELMUX"] = 0 + + return params + + +def run(): + + # Get all [LR]IOI3 tiles + tiles = list(gen_sites()) + + # Header + print("// Tile count: %d" % len(tiles)) + print("// Seed: '%s'" % os.getenv("SEED")) + print( + ''' +module top ( + (* CLOCK_BUFFER_TYPE = "NONE" *) + input wire clk1, + (* CLOCK_BUFFER_TYPE = "NONE" *) + input wire clk2, + input wire ce, + input wire rst, + input wire [{N}:0] di, + output wire [{N}:0] do +); + +wire [{N}:0] di_buf; +wire [{N}:0] do_buf; + +// IDELAYCTRL +(* KEEP, DONT_TOUCH *) +IDELAYCTRL idelayctrl(); + '''.format(**{"N": len(tiles) - 1})) + + # LOCes IOBs + data = [] + for i, sites in enumerate(tiles): + tile_name = sites[0] + + # Use site + if random.randint(0, 19) > 0: # Use more often + + # Top sites + if random.randint(0, 1): + this_sites = sites[1] + other_sites = sites[2] + # Bottom sites + else: + this_sites = sites[2] + other_sites = sites[1] + + # Generate cell + bel_types = ["IDDR", "ISERDESE2"] + bel_type = bel_types[int( + random.randint(0, 2) > 0)] # ISERDES more often + if bel_type == "ISERDESE2": + params = gen_iserdes(this_sites["ILOGIC"]) + if bel_type == "IDDR": + params = gen_iddr(this_sites["ILOGIC"]) + + params["IDELAY_LOC"] = verilog.quote(this_sites["IDELAY"]) + params["IS_USED"] = 1 + + # Instantiate the cell + print('') + print('// This : ' + " ".join(this_sites.values())) + print('// Other: ' + " ".join(other_sites.values())) + print('(* LOC="%s", KEEP, DONT_TOUCH *)' % this_sites["IOB"]) + print('IBUF ibuf_%03d (.I(di[%3d]), .O(di_buf[%3d]));' % (i, i, i)) + print('(* LOC="%s", KEEP, DONT_TOUCH *)' % other_sites["IOB"]) + print('OBUF obuf_%03d (.I(do_buf[%3d]), .O(do[%3d]));' % (i, i, i)) + + clk1_conn = random.choice(["clk1", ""]) + + param_str = ",".join(".%s(%s)" % (k, v) for k, v in params.items()) + print( + 'ilogic_single #(%s) ilogic_%03d (.clk1(%s), .clk2(clk2), .ce(ce), .rst(rst), .I(di_buf[%3d]), .O(do_buf[%3d]));' + % (param_str, i, clk1_conn, i, i)) + + params["CHAINED"] = 0 + params["TILE_NAME"] = tile_name + + # Params for the second site + other_params = { + "TILE_NAME": tile_name, + "SITE_LOC": verilog.quote(other_sites["ILOGIC"]), + "IDELAY_LOC": verilog.quote(other_sites["IDELAY"]), + "IS_USED": 0, + } + + # Append to data list + data.append([params, other_params]) + + # Don't use sites + else: + + params_list = [ + { + "TILE_NAME": tile_name, + "SITE_LOC": verilog.quote(sites[1]["ILOGIC"]), + "IDELAY_LOC": verilog.quote(sites[1]["IDELAY"]), + "IS_USED": 0, + }, + { + "TILE_NAME": tile_name, + "SITE_LOC": verilog.quote(sites[2]["ILOGIC"]), + "IDELAY_LOC": verilog.quote(sites[2]["IDELAY"]), + "IS_USED": 0, + } + ] + + data.append(params_list) + + # Store params + with open("params.json", "w") as fp: + json.dump(data, fp, sort_keys=True, indent=1) + + print( + ''' +endmodule + +(* KEEP, DONT_TOUCH *) +module ilogic_single( + input wire clk1, + input wire clk2, + input wire ce, + input wire rst, + input wire I, + output wire O, + input wire [1:0] shiftin, + output wire [1:0] shiftout +); + +parameter SITE_LOC = ""; +parameter IS_USED = 1; +parameter BEL_TYPE = "ISERDESE2"; +parameter IDELAY_LOC = ""; +parameter USE_IDELAY = 0; +parameter IDELMUX = 0; +parameter IFFDELMUX = 0; +parameter INTERFACE_TYPE = "NETWORKING"; +parameter DATA_RATE = "DDR"; +parameter DATA_WIDTH = 4; +parameter SERDES_MODE = "MASTER"; +parameter NUM_CE = 2; +parameter INIT_Q1 = 0; +parameter INIT_Q2 = 0; +parameter INIT_Q3 = 0; +parameter INIT_Q4 = 0; +parameter SRVAL_Q1 = 0; +parameter SRVAL_Q2 = 0; +parameter SRVAL_Q3 = 0; +parameter SRVAL_Q4 = 0; +parameter IS_D_INVERTED = 0; +parameter IS_OCLK_INVERTED = 0; +parameter IS_OCLKB_INVERTED = 0; +parameter IS_CLK_INVERTED = 0; +parameter IS_CLKB_INVERTED = 0; +parameter IS_CLKDIV_INVERTED = 0; +parameter IS_CLKDIVP_INVERTED = 0; +parameter DYN_CLKDIV_INV_EN = "FALSE"; +parameter DYN_CLK_INV_EN = "FALSE"; +parameter IOBDELAY = "NONE"; +parameter OFB_USED = "FALSE"; +parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; +parameter SRTYPE = "ASYNC"; +parameter CE1USED = 0; +parameter SR_MODE = "NONE"; +parameter IS_C_INVERTED = 0; + +wire [8:0] x; +wire ddly; + +(* KEEP, DONT_TOUCH *) +generate if (IS_USED && USE_IDELAY) begin + + // IDELAY + (* LOC=IDELAY_LOC, KEEP, DONT_TOUCH *) + IDELAYE2 idelay + ( + .C(clk), + .REGRST(), + .LD(), + .CE(), + .INC(), + .CINVCTRL(), + .CNTVALUEIN(), + .IDATAIN(I), + .DATAIN(), + .LDPIPEEN(), + .DATAOUT(ddly), + .CNTVALUEOUT() + ); + +end else begin + + assign ddly = 0; + +end endgenerate + +(* KEEP, DONT_TOUCH *) +generate if (IS_USED && BEL_TYPE == "ISERDESE2") begin + + // ISERDES + (* LOC=SITE_LOC, KEEP, DONT_TOUCH *) + ISERDESE2 # + ( + .INTERFACE_TYPE(INTERFACE_TYPE), + .DATA_RATE(DATA_RATE), + .DATA_WIDTH(DATA_WIDTH), + .SERDES_MODE(SERDES_MODE), + .NUM_CE(NUM_CE), + .IS_D_INVERTED(IS_D_INVERTED), + .IS_OCLK_INVERTED(IS_OCLK_INVERTED), + .IS_OCLKB_INVERTED(IS_OCLKB_INVERTED), + .IS_CLK_INVERTED(IS_CLK_INVERTED), + .IS_CLKB_INVERTED(IS_CLKB_INVERTED), + .IS_CLKDIV_INVERTED(IS_CLKDIV_INVERTED), + .IS_CLKDIVP_INVERTED(IS_CLKDIVP_INVERTED), + .INIT_Q1(INIT_Q1), + .INIT_Q2(INIT_Q2), + .INIT_Q3(INIT_Q3), + .INIT_Q4(INIT_Q4), + .SRVAL_Q1(SRVAL_Q1), + .SRVAL_Q2(SRVAL_Q2), + .SRVAL_Q3(SRVAL_Q3), + .SRVAL_Q4(SRVAL_Q4), + .DYN_CLKDIV_INV_EN(DYN_CLKDIV_INV_EN), + .DYN_CLK_INV_EN(DYN_CLK_INV_EN), + .IOBDELAY(IOBDELAY), + .OFB_USED(OFB_USED) + ) + isedres + ( + .D(I), + .DDLY(), + .OFB(), + //.TFB(), + .CE1(), + .CE2(), + .DYNCLKSEL(), + .CLK(clk1), + .CLKB(clk2), + .OCLK(), + .OCLKB(), + .DYNCLKDIVSEL(), + .CLKDIV(), + .CLKDIVP(), + .RST(), + .BITSLIP(), + .O(x[8]), + .Q1(x[0]), + .Q2(x[1]), + .Q3(x[2]), + .Q4(x[3]), + .Q5(x[4]), + .Q6(x[5]), + .Q7(x[6]), + .Q8(x[7]), + .SHIFTIN1(shiftin[0]), + .SHIFTIN2(shiftin[1]), + .SHIFTOUT1(shiftout[0]), + .SHIFTOUT2(shiftout[1]) + ); + +end else if (IS_USED && BEL_TYPE == "IDDR") begin + + // IDDR + (* LOC=SITE_LOC, KEEP, DONT_TOUCH *) + IDDR # + ( + .IS_C_INVERTED(IS_C_INVERTED), + .IS_D_INVERTED(IS_D_INVERTED), + .DDR_CLK_EDGE(DDR_CLK_EDGE), + .INIT_Q1(INIT_Q1), + .INIT_Q2(INIT_Q2), + .SRTYPE(SRTYPE) + ) + iddr + ( + .C(clk1), + .CE( (CE1USED) ? ce : 1'hx ), + .D( (IFFDELMUX) ? ddly : I ), + .S( (SR_MODE == "SET") ? rst : 1'd0 ), + .R( (SR_MODE == "RST") ? rst : 1'd0 ), + .Q1(x[0]), + .Q2(x[1]) + ); + + assign x[8] = (IDELMUX) ? ddly : I; + assign x[7:2] = 0; + +end else if (IS_USED && BEL_TYPE == "IDDR_NO_CLK") begin + + // IDDR + (* LOC=SITE_LOC, KEEP, DONT_TOUCH *) + IDDR # + ( + .IS_C_INVERTED(IS_C_INVERTED), + .IS_D_INVERTED(IS_D_INVERTED), + .DDR_CLK_EDGE(DDR_CLK_EDGE), + .INIT_Q1(INIT_Q1), + .INIT_Q2(INIT_Q2), + .SRTYPE(SRTYPE) + ) + iddr + ( + .C(), + .CE( (CE1USED) ? ce : 1'hx ), + .D( (IFFDELMUX) ? ddly : I ), + .S( (SR_MODE == "SET") ? rst : 1'd0 ), + .R( (SR_MODE == "RST") ? rst : 1'd0 ), + .Q1(x[0]), + .Q2(x[1]) + ); + + assign x[8] = (IDELMUX) ? ddly : I; + assign x[7:2] = 0; + +end else begin + + assign x[0] = I; + assign x[1] = I; + assign x[2] = I; + assign x[3] = I; + assign x[4] = I; + assign x[5] = I; + assign x[6] = I; + assign x[7] = I; + assign x[8] = I; + +end endgenerate + +// Output +assign O = |x; + +endmodule + + ''') + + +run() diff --git a/fuzzers/045a-hclk-cmt-ck-in/Makefile b/fuzzers/045a-hclk-cmt-ck-in/Makefile new file mode 100644 index 00000000..c5577a4f --- /dev/null +++ b/fuzzers/045a-hclk-cmt-ck-in/Makefile @@ -0,0 +1,66 @@ +# Copyright (C) 2017-2020 The Project X-Ray Authors. +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC +# +# 045a — fill the CK_IN[1..13] gap in segbits_hclk_cmt[_l].db. +# +# Mirrors 045-hclk-cmt-pips/Makefile but iterates over the 21 unsolved +# CK_IN PIPs in targets.csv (rather than sweeping all PIPs). Re-uses +# 045's cmt_regions.csv (build/ symlink), bits.dbf, and segmatch+mergedb +# downstream chain. +export FUZDIR=$(shell pwd) +PARENT_FUZDIR=$(FUZDIR)/../045-hclk-cmt-pips +PIP_TYPE?=hclk_cmt +PIPLIST_TCL=$(PARENT_FUZDIR)/hclk_cmt_pip_list.tcl +TODO_RE=".*HCLK_CMT.*CK_IN.*" +EXCLUDE_RE="(^.*LEAF)|(^.*BUFMR)|(^.*PHSR)|(^.*CLK_PLL7)|(^.*CLK_MMCM13)" +MAKETODO_FLAGS=--sides ",l" --pip-type ${PIP_TYPE} --seg-type ${PIP_TYPE} --re $(TODO_RE) --exclude-re $(EXCLUDE_RE) + +# One specimen per target PIP in targets.csv (21 rows + header). N a few +# above 21 to give segmatch slack for failed-route specimens. +N = 24 +FOUR_BIT_PIPS="FREQ_REF" +SPECIMENS_DEPS=build/cmt_regions.csv +A_PIPLIST=hclk_cmt.txt + +include ../pip_loop.mk + +.PRECIOUS: build/%.rdb + +build/%.rdb: $(SPECIMENS_OK) + $(XRAY_SEGMATCH) -c 4 -o $@.4 $(shell find build -name $(subst segbits,segdata,$(patsubst %.rdb,%.txt,$(notdir $@)))) + $(XRAY_SEGMATCH) -c 2 -o $@.2 $(shell find build -name $(subst segbits,segdata,$(patsubst %.rdb,%.txt,$(notdir $@)))) + grep ${FOUR_BIT_PIPS} $@.4 > $@ || true + grep -v ${FOUR_BIT_PIPS} $@.2 >> $@ || true + +build/%.db: build/%.rdb + ${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \ + --seg-fn-in $< \ + --seg-fn-out $@ + cp $< build/$(ITER)/$(notdir $<) + ${XRAY_MASKMERGE} $(subst segbits,mask,$@) \ + $(shell find build -name $(subst segbits,segdata,$(patsubst %.db,%.txt,$(notdir $@)))) + +database: build/segbits_hclk_cmt.db build/segbits_hclk_cmt_l.db + cp ${XRAY_DATABASE_DIR}/${XRAY_DATABASE}/segbits_hclk_cmt*.db build/database/${XRAY_DATABASE} || true + XRAY_DATABASE_DIR=${FUZDIR}/build/database ${XRAY_MERGEDB} hclk_cmt build/segbits_hclk_cmt.db + XRAY_DATABASE_DIR=${FUZDIR}/build/database ${XRAY_MERGEDB} hclk_cmt_l build/segbits_hclk_cmt_l.db + +# cmt_regions.csv: symlink to 045's existing one so we don't re-run Vivado +# to regenerate it. If the symlink is missing, fall back to running +# 045's output_cmt.tcl. +build/cmt_regions.csv: + mkdir -p build + test -e $@ || ln -sf $(PARENT_FUZDIR)/build/cmt_regions.csv $@ + +pushdb: database + ${XRAY_MERGEDB} hclk_cmt build/database/${XRAY_DATABASE}/segbits_hclk_cmt.db + ${XRAY_MERGEDB} mask_hclk_cmt build/mask_hclk_cmt.db + ${XRAY_MERGEDB} hclk_cmt_l build/database/${XRAY_DATABASE}/segbits_hclk_cmt_l.db + ${XRAY_MERGEDB} mask_hclk_cmt_l build/mask_hclk_cmt_l.db + +.PHONY: database pushdb diff --git a/fuzzers/045a-hclk-cmt-ck-in/README.md b/fuzzers/045a-hclk-cmt-ck-in/README.md new file mode 100644 index 00000000..b435a972 --- /dev/null +++ b/fuzzers/045a-hclk-cmt-ck-in/README.md @@ -0,0 +1,191 @@ +# 045a — HCLK\_CMT CK\_IN\* segbits + +Fills the gap left by `045-hclk-cmt-pips`, which leaves 21 PIPs through the +`HCLK_CMT_CK_IN[1..13]` inputs unsolved (see +`fuzzers/045-hclk-cmt-pips/build/todo.txt`). These are needed to translate +`HCLK_CMT*.MUX_CLK_n.CK_INm` features that nextpnr-xilinx emits when routing +a `IBUFDS_GTE2 → BUFG → fabric` clock (e.g. the VC707 `SGMIICLK_Q0` path). + +The 21 unsolved entries split as: + +| tile_type | unsolved PIPs | +|-------------|---------------| +| HCLK_CMT | 3 (MUX_CLK_{7,8,10} ← CK_IN{9,4,6}) | +| HCLK_CMT_L | 18 (CK_IN{1,2,3,5,7,8,9,10,11,12,13} → various MMCM/PLL/MUX_CLK_*) | + +## Why the parent 045 fuzzer misses them + +`045-hclk-cmt-pips` uses random CMT clock-source assignments and relies on +Vivado's placer/router to spread routes across PIPs. For the CK_IN paths +Vivado almost always picks the same physical wire regardless of seed — +either because the CK_IN input is fed from a non-modeled source (a CCIO +that isn't in the design pool) or because the routing engine prefers a +single "shortest path" through the mux fabric. Without explicit +constraints the `(MUX_CLK_n, CK_INm)` cell of the routing matrix never +flips, so `segmatch` can't isolate its bits. + +## Approach used here + +For each of the 21 PIPs we generate a *forced-route* specimen: + +1. `top.py` instantiates a CMT loadload (MMCM/PLL or BUFR sink) plus a + clock-capable source (CCIO pad). +2. `generate.tcl` issues explicit `USER_CLOCK_ROOT`, `LOC`, and + `route_design -mode quick -nets ` to pin the clock through the + exact `HCLK_CMT*.MUX_CLK_n.HCLK_CMT_CK_INm` PIP we want to learn. + We confirmed this works on this part by reproducing the same trick in + `~/div2_sgmii_loc_build/` (LOC SLICE_X0Y0 + LOC BUFGCTRL_X0Y0 forced + the clock onto `HCLK_CMT_X88Y26` and set bit `27_181`). +3. The standard prjxray `segmaker` / `segmatch` chain extracts the + set/clear bit pattern for each PIP. + +## State as of this session + +End-to-end runnable scaffold: + +- `targets.csv` — the 21 PIPs (3 HCLK_CMT + 18 HCLK_CMT_L), generated from + `045-hclk-cmt-pips/build/todo.txt`. +- `top.py` — delegates to 045's `top.py` so we share its MMCM/PLL/BUFR + loadload pool. Verified to emit ~3240 lines of Verilog given a SEED. +- `generate.tcl` — implements `pick_target_for_specimen` (round-robin + on SPECIMEN env) and `force_ck_in_route` (walks placed nets, finds one + in the target tile_type, builds a two-leg `find_routing_path` and pins + it with `FIXED_ROUTE`). Parses cleanly through Vivado. +- `Makefile` — N=24 (21 targets + 3 redundant retries on the first three + rows). Uses standard pip_loop.mk. +- `build/cmt_regions.csv` — symlinked from 045's prior build so we share + its CMT site→region mapping. + +## How to run + +``` +cd fuzzers/045a-hclk-cmt-ck-in +source ../../settings/virtex7.sh # set XRAY_PART etc. +make +``` + +Output: `build/segbits_hclk_cmt.db` + `build/segbits_hclk_cmt_l.db` +which then merge into `database/virtex7/segbits_hclk_cmt[_l].db` via +`pushdb`-equivalent step (see 045's Makefile chain). + +## What the first specimen run taught us + +Ran `make N=1 build/1/specimen_001/OK` against target row 0 +(`HCLK_CMT.HCLK_CMT_MUX_CLK_10.HCLK_CMT_CK_IN6`). + +- top.py / generate.tcl chain runs end-to-end through Vivado: + synth → place → route_design → force_ck_in_route → route_design + → write_bitstream → bit2fasm. ~10 min wall-clock per specimen. +- `force_ck_in_route` scanned 16 nets, found 9 candidates touching + some `HCLK_CMT` tile, tried 3, and bailed: every candidate failed + the `find_routing_path` driver→src leg. Diagnostic line: + `045a: candidate cin1_MMCME2_ADV_X0Y3 via HCLK_CMT_X88Y182 — driver can't reach src`. +- The Vivado design.bit + design.fasm are produced, but with no + target PIP used. Consequence: `int_generate.py` asserts + `"Didn't generate any segments"` because nothing in design.txt + intersects todo.txt. + +## Why simple `find_routing_path` isn't enough + +Each `HCLK_CMT_CK_INm` input is fed from a specific clock backbone +segment determined by *physical placement* (which BUFGCTRL site, +which BUFR site, which HCLK leaf). 045's random MMCM/PLL/BUFR +placement happens to never land in a topology where the existing +clock drivers can be re-routed to CK_IN6 — which is exactly why +those 21 PIPs survived 100 random specimens in 045 to begin with. + +`find_routing_path` faithfully reports "no reachable wires" because +the driver site_pin really can't get to CK_IN6 of the chosen +HCLK_CMT tile without first being moved. + +## The pivot the next session needs + +Make `force_ck_in_route` *choose the design topology* per specimen, +not just react to whatever random placement landed: + +1. **LOC-based force per target.** We already proved on + `~/div2_sgmii_loc_build/` that + `set_property LOC BUFGCTRL_X0Y0 [get_cells sysclk_bufg]` + + `set_property USER_CLOCK_ROOT X0Y0 [get_nets clk]` reliably + moves the clock onto a specific `HCLK_CMT_X88Y26` and lights up + one bit (`27_181`). For each target row in `targets.csv` we + need a small table of `(tile_type instance, expected_BUFG_site, + expected_BUFR_site)` triples; the proc applies those LOC + constraints before `place_design`, not after route. +2. **Drop the post-hoc find_routing_path.** Once Vivado places the + design under the LOC, the natural route will hit the target + PIP — no FIXED_ROUTE injection needed. Verify with + `get_pips -of_objects [get_nets clk]` and only commit specimens + where the target PIP shows up. +3. **Skip-not-fail in int_generate.** For specimens that did + ultimately use the target PIP, write `segdata_*.txt`; for those + that didn't, write an empty `segdata_*.txt` + `tag` line marking + the negative. Avoid the `AssertionError` and let segmatch + benefit from negative evidence. + +## Pre-pivot smoke test of the chain + +End-to-end pipeline works *modulo* the topology issue: ~10 min per +specimen, parses cleanly, emits bit + fasm + txt. Only the segmaker +step asserts on empty output. + +## Probe result (`/tmp/ckin_probe/` on 2026-05-30) + +Built a minimal `IBUF → BUFR (LOC X0Y2) → MMCM (LOC X0Y0)` design in +Vivado, dumped every PIP used in HCLK_CMT* tiles plus every PIP whose +name contains `CK_IN`. + +Result: **zero HCLK_CMT PIPs used**, and the only `CK_IN` PIP in the +whole design was +`CLK_HROW_BOT_R.CLK_HROW_CK_IN_L0->>CLK_HROW_BOT_R_CK_BUFG_CASCO0` +(BUFG-cascade input, *not* an HCLK_CMT input). + +Interpretation: Vivado's BUFR→MMCM routing flows entirely through the +CLK_HROW / BUFG-ring network and bypasses the HCLK_CMT entirely. +Combined with 045's history of 100 random specimens *never* hitting +the 21 unsolved CK_IN PIPs, the most likely explanation is that +**Vivado deliberately doesn't use `HCLK_CMT_CK_IN*` PIPs** for any +standard topology — they exist in silicon but the timing/closure +model avoids them. + +That changes the conclusion for the open-flow problem. If Vivado +doesn't set bits for those PIPs and *still* produces a bitstream +that works on hardware, the `IBUFDS_GTE2.IN_USE` / `CK_IN8` lines +nextpnr-xilinx emits are mostly decorative — and our PPIP no-op +patch (silence fasm2frames, emit no bits) is **the correct fix**. + +The open-flow VC707 counter's stuck-LED issue is therefore unlikely +to be about missing CK_IN segbits. More plausible culprits: + +1. **FF clear-bits** — counter125's FFs initialise via FDRE/FDSE + `ZINI/ZRST` segbits. If the open-flow bitstream programs those + wrong (e.g. wrong `INIT` value, or `FFSYNC` flipped), the counter + starts at `0b10001000` (= LEDs 3 + 7 on, all others off, which is + exactly what we observed) and stays there. +2. **`rst` input routing** — nextpnr placed rst at `IOB_X0Y124`; + check the LIOB18 IBUF + INT-routing FASM lines against Vivado. +3. **OBUF / DRIVE / SLEW** for the LED IOBs — but those would only + affect brightness, not the bit pattern. + +Picking up this thread should start at `~/counter125_build/top.fasm` +vs `top_vivado.fasm` for the **CLBLL/CLBLM SLICE FF and rst-input +IOB lines**, not the HCLK_CMT block. + +## 045a status + +The scaffold is preserved as-is (Makefile, top.py, generate.tcl, +targets.csv) because it might still be valuable as a **negative-result +record** — the 21 PIPs in `targets.csv` are essentially "PIPs the +silicon supports but Vivado refuses to use". A future generation that +needs to fuzz these would do so by *building the routing manually* +with `route_via` from a clean starting design, not by hoping random +placements happen to use them. + +## Files + +| file | role | +|---------------|------| +| `Makefile` | drives N specimens through the common segmatch chain | +| `targets.csv` | the 21 (tile_type, dst, src) tuples to fuzz | +| `top.py` | per-specimen Verilog generator (placeholder, see TODO) | +| `generate.tcl`| per-specimen Vivado driver: LOC-force the target PIP (TODO) | diff --git a/fuzzers/045a-hclk-cmt-ck-in/bits.dbf b/fuzzers/045a-hclk-cmt-ck-in/bits.dbf new file mode 100644 index 00000000..e69de29b diff --git a/fuzzers/045a-hclk-cmt-ck-in/generate.tcl b/fuzzers/045a-hclk-cmt-ck-in/generate.tcl new file mode 100644 index 00000000..1c49cd2a --- /dev/null +++ b/fuzzers/045a-hclk-cmt-ck-in/generate.tcl @@ -0,0 +1,150 @@ +# Copyright (C) 2017-2020 The Project X-Ray Authors +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC +# +# 045a — CK_IN-targeted segbits for HCLK_CMT[_L]. +# +# Picks one (tile_type, dst, src) target from targets.csv per specimen +# (round-robin on SPECIMEN env var), then forces a clock net through the +# CK_IN PIP using FIXED_ROUTE. Mirrors the proven pattern in 045's +# route_todo (loop through nets, find one in the right tile type, set +# FIXED_ROUTE via find_routing_path). Standard segmaker chain takes it +# from there. +source "$::env(XRAY_DIR)/utils/utils.tcl" + +proc load_targets {} { + set fp [open "$::env(FUZDIR)/targets.csv" r] + gets $fp _header + set rows [list] + for {gets $fp line} {$line != ""} {gets $fp line} { + lappend rows [split $line ","] + } + close $fp + return $rows +} + +proc pick_target_for_specimen {} { + # Extract specimen number from cwd (e.g. .../specimen_007 -> 7) since + # prjxray's top_generate chain doesn't export SPECIMEN as an env var. + set cwd [pwd] + set tail [file tail $cwd] + set n 0 + if {![regexp {specimen_(\d+)} $tail _m num]} { + puts "045a: WARN — could not parse specimen number from cwd $cwd; defaulting to 1" + set num 1 + } + set n [expr {$num - 1}] + set rows [load_targets] + set row [lindex $rows [expr {$n % [llength $rows]}]] + puts "045a: specimen=$tail target_row=$n -> $row" + return $row +} + +# Try to force a net through the target PIP using FIXED_ROUTE. +# +# Approach: gather candidate (net, tile) pairs FIRST without touching +# routing, score them cheaply (does the driver site_pin even share a +# clock backbone with the target tile?), and only unroute + FIXED_ROUTE +# the most promising candidate. If nothing plausible exists in this +# specimen's random placement, give up immediately — leaving the design +# routed as-is — instead of repeatedly unrouting nets and crashing into +# unreachable wires. +proc force_ck_in_route {target_tile_type target_dst target_src} { + puts "045a: forcing route through $target_tile_type.$target_dst.$target_src" + + # Collect candidates without mutating the design. + set candidates [list] + set max_scan 16 ;# bail-out — never scan more than 16 nets / specimen + set scanned 0 + foreach net [get_nets] { + if {$scanned >= $max_scan} { break } + incr scanned + set hits [get_wires -of_objects $net -filter "TILE_NAME =~ *HCLK_CMT*"] + if {[llength $hits] == 0} { continue } + foreach hit $hits { + set tile [lindex [split $hit /] 0] + if {[get_property TILE_TYPE [get_tiles $tile]] != $target_tile_type} { continue } + set src_wire [get_wires "$tile/$target_src"] + set dst_wire [get_wires "$tile/$target_dst"] + if {[llength $src_wire] == 0 || [llength $dst_wire] == 0} { continue } + lappend candidates [list $net $tile $src_wire $dst_wire] + break ;# one candidate tile per net is enough + } + } + puts "045a: scanned $scanned nets, found [llength $candidates] candidate (net,tile) pairs" + if {[llength $candidates] == 0} { + puts "045a: no candidate net touches a $target_tile_type tile with $target_src and $target_dst reachable — skipping this specimen" + return 0 + } + + # Try at most 3 candidates. For each, do ONE find_routing_path check + # *before* unrouting; only mutate the net if both legs exist. + set try_limit 3 + set tried 0 + foreach cand $candidates { + if {$tried >= $try_limit} { break } + incr tried + lassign $cand net tile src_wire dst_wire + set src_node [get_nodes -of_objects $src_wire] + set dst_node [get_nodes -of_objects $dst_wire] + if {[llength $src_node] == 0 || [llength $dst_node] == 0} { continue } + set origin_pin [get_site_pins -filter {DIRECTION == OUT} -of_objects $net] + if {[llength $origin_pin] == 0} { continue } + set origin_node [get_nodes -of_objects $origin_pin] + + # Cheap reachability probe BEFORE we destroy any existing routing. + set leg1 [find_routing_path -to $src_node -from $origin_node] + if {[llength $leg1] == 0} { + puts "045a: candidate $net via $tile — driver can't reach src; skipping" + continue + } + set leg2 [find_routing_path -to $dst_node -from $src_node] + if {[llength $leg2] == 0} { + puts "045a: candidate $net via $tile — src can't reach dst; skipping" + continue + } + + # Both legs check out — commit. + route_design -unroute -nets $net + set_property FIXED_ROUTE [concat $leg1 $leg2] $net + puts "045a: forced $tile/$target_src -> $tile/$target_dst on net $net (candidate $tried)" + return 1 + } + + puts "045a: tried $tried candidates, none routable for $target_tile_type.$target_dst.$target_src — leaving design unchanged for this specimen" + return 0 +} + +proc run {} { + create_project -force -part $::env(XRAY_PART) design design + read_verilog top.v + synth_design -top top + + set_property CFGBVS VCCO [current_design] + set_property CONFIG_VOLTAGE 3.3 [current_design] + set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] + foreach drc {PDRC-29 PDRC-38 REQP-13 REQP-123 REQP-161 REQP-1575 + REQP-1684 REQP-1712 AVAL-50 AVAL-78 AVAL-81} { + set_property IS_ENABLED 0 [get_drc_checks $drc] + } + set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets] + + place_design -directive Quick + route_design -directive Quick + + set target [pick_target_for_specimen] + lassign $target tile_type dst src + force_ck_in_route $tile_type $dst $src + + route_design -directive Quick -preserve + + write_checkpoint -force design.dcp + write_bitstream -force design.bit + write_pip_txtdata design.txt +} + +run diff --git a/fuzzers/045a-hclk-cmt-ck-in/targets.csv b/fuzzers/045a-hclk-cmt-ck-in/targets.csv new file mode 100644 index 00000000..925fb9e9 --- /dev/null +++ b/fuzzers/045a-hclk-cmt-ck-in/targets.csv @@ -0,0 +1,22 @@ +tile_type,dst,src +HCLK_CMT,HCLK_CMT_MUX_CLK_10,HCLK_CMT_CK_IN6 +HCLK_CMT,HCLK_CMT_MUX_CLK_7,HCLK_CMT_CK_IN9 +HCLK_CMT,HCLK_CMT_MUX_CLK_8,HCLK_CMT_CK_IN4 +HCLK_CMT_L,HCLK_CMT_CK_IN10,HCLK_CMT_CCIO0 +HCLK_CMT_L,HCLK_CMT_CK_IN11,HCLK_CMT_MUX_CLK_MMCM11 +HCLK_CMT_L,HCLK_CMT_CK_IN11,HCLK_CMT_MUX_CLK_PLL5 +HCLK_CMT_L,HCLK_CMT_CK_IN12,HCLK_CMT_MUX_CLK_MMCM6 +HCLK_CMT_L,HCLK_CMT_CK_IN12,HCLK_CMT_MUX_CLK_PLL4 +HCLK_CMT_L,HCLK_CMT_CK_IN13,HCLK_CMT_CK_BUFHCLK0 +HCLK_CMT_L,HCLK_CMT_CK_IN13,HCLK_CMT_MUX_CLK_PLL3 +HCLK_CMT_L,HCLK_CMT_CK_IN1,HCLK_CMT_MUX_CLK_MMCM1 +HCLK_CMT_L,HCLK_CMT_CK_IN2,HCLK_CMT_MUX_CLK_6 +HCLK_CMT_L,HCLK_CMT_CK_IN2,HCLK_CMT_MUX_CLK_7 +HCLK_CMT_L,HCLK_CMT_CK_IN2,HCLK_CMT_MUX_CLK_MMCM4 +HCLK_CMT_L,HCLK_CMT_CK_IN3,HCLK_CMT_MUX_CLK_5 +HCLK_CMT_L,HCLK_CMT_CK_IN5,HCLK_CMT_MUX_CLK_PLL1 +HCLK_CMT_L,HCLK_CMT_CK_IN7,HCLK_CMT_MUX_CLK_9 +HCLK_CMT_L,HCLK_CMT_CK_IN8,HCLK_CMT_CK_BUFHCLK1 +HCLK_CMT_L,HCLK_CMT_CK_IN8,HCLK_CMT_CK_BUFHCLK6 +HCLK_CMT_L,HCLK_CMT_CK_IN8,HCLK_CMT_MUX_CLK_PLL5 +HCLK_CMT_L,HCLK_CMT_CK_IN9,HCLK_CMT_CK_BUFHCLK9 diff --git a/fuzzers/045a-hclk-cmt-ck-in/top.py b/fuzzers/045a-hclk-cmt-ck-in/top.py new file mode 100644 index 00000000..ebb6efa6 --- /dev/null +++ b/fuzzers/045a-hclk-cmt-ck-in/top.py @@ -0,0 +1,40 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +# +# Copyright (C) 2017-2020 The Project X-Ray Authors. +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC +""" 045a — same MMCM/PLL/BUFR loadload design as 045, just driven with a +different SEED. The per-specimen target PIP selection happens in +generate.tcl, which reads targets.csv and picks based on the SPECIMEN +env var. + +We delegate to 045's top.py to avoid duplicating ~600 lines of CMT +loadload synthesis. 045's top.py reads +$FUZDIR/build/cmt_regions.csv at module level, so we temporarily +override FUZDIR for the duration of the import. +""" +import os +import sys +import runpy + +# Make 045's helpers importable. +PARENT = os.path.join(os.path.dirname(os.path.abspath(__file__)), + '..', '045-hclk-cmt-pips') +sys.path.insert(0, PARENT) + +# 045's top.py expects FUZDIR pointing at *its own* fuzzer dir so it can +# read build/cmt_regions.csv. Save the caller's value and restore after. +caller_fuzdir = os.environ.get('FUZDIR') +os.environ['FUZDIR'] = PARENT +try: + runpy.run_path(os.path.join(PARENT, 'top.py'), run_name='__main__') +finally: + if caller_fuzdir is None: + os.environ.pop('FUZDIR', None) + else: + os.environ['FUZDIR'] = caller_fuzdir diff --git a/utils/strip_transplant.py b/utils/strip_transplant.py new file mode 100644 index 00000000..98b7b58d --- /dev/null +++ b/utils/strip_transplant.py @@ -0,0 +1,109 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +# +# Copyright (C) 2017-2020 The Project X-Ray Authors. +# +# Use of this source code is governed by a ISC-style +# license that can be found in the LICENSE file or at +# https://opensource.org/licenses/ISC +# +# SPDX-License-Identifier: ISC +""" +Remove segbits whose recorded provenance is a transplant (a fuzzer that +cannot run on this part, or a foreign-database copy) so the slot can be +re-filled by a real measurement. + +For a given (e.g. rioi) it edits, in lock-step: + segbits_.db (TAG bit bit ...) + segbits_.origin_info.db (TAG origin: bit bit ...) +A tag is dropped iff its origin_info origin EXACTLY equals one of the +--origins values. Tags whose origin is a comma-joined chain (i.e. a +transplant later partly overwritten by a real fuzzer) are kept and +reported, since the chain needs the real re-fuzz merged first. + +Use --apply to write; default is a dry run. +""" +import argparse +import os +import sys + + +def load_origins(fn): + """tag -> origin (from a *.origin_info.db).""" + origins = {} + if not os.path.exists(fn): + return origins + for line in open(fn): + parts = line.split() + if len(parts) < 2: + continue + tag = parts[0] + # The origin token may sit right after the tag (most fuzzers) or at + # the end of the line (hand-edited entries); search all fields. + origin = None + for p in parts[1:]: + if p.startswith('origin:'): + origin = p[len('origin:'):] + break + origins[tag] = origin + return origins + + +def strip_file(fn, drop_tags): + """Rewrite fn keeping only lines whose first field is not in drop_tags. + Returns (kept, removed).""" + kept, removed = [], [] + for line in open(fn): + tag = line.split(' ', 1)[0].strip() if line.strip() else None + if tag in drop_tags: + removed.append(line.rstrip('\n')) + elif line.strip(): + kept.append(line.rstrip('\n')) + return kept, removed + + +def main(): + ap = argparse.ArgumentParser(description=__doc__) + ap.add_argument('--db-root', required=True) + ap.add_argument('--db-type', required=True, help='e.g. rioi, lioi_tbytesrc') + ap.add_argument( + '--origins', required=True, nargs='+', + help='origin strings to drop (exact match), e.g. 035-iob-ilogic') + ap.add_argument('--apply', action='store_true', help='write changes') + args = ap.parse_args() + + seg = os.path.join(args.db_root, 'segbits_%s.db' % args.db_type) + org = os.path.join(args.db_root, 'segbits_%s.origin_info.db' % args.db_type) + if not os.path.exists(org): + print(' %s: no origin_info db, skipping' % args.db_type) + return 0 + + origins = load_origins(org) + bad = set(args.origins) + drop = {t for t, o in origins.items() if o in bad} + chained = { + t: o + for t, o in origins.items() + if o and ',' in o and any(b in o.split(',') for b in bad) + } + + print('[%s] drop %d tags with origin in %s' % (args.db_type, len(drop), sorted(bad))) + if chained: + print(' NOTE %d chained-origin tags kept (need real re-fuzz merged ' + 'first): %s' % (len(chained), sorted(chained)[:4])) + + for fn in (seg, org): + if not os.path.exists(fn): + continue + kept, removed = strip_file(fn, drop) + print(' %s: %d kept, %d removed' % (os.path.basename(fn), len(kept), len(removed))) + if args.apply: + with open(fn, 'w') as f: + f.write('\n'.join(sorted(kept)) + ('\n' if kept else '')) + if not args.apply: + print(' (dry run; pass --apply to write)') + return 0 + + +if __name__ == '__main__': + sys.exit(main())