From 5396046644b6bbe5a5ae8e82f358957a88c773b0 Mon Sep 17 00:00:00 2001 From: John McMaster Date: Wed, 31 Oct 2018 10:45:50 -0700 Subject: [PATCH] bram minitest: split into fuzzer config, data Signed-off-by: John McMaster --- .../101-bram-config/minitest}/.gitignore | 0 .../101-bram-config/minitest}/Makefile | 21 +- .../101-bram-config/minitest}/README.md | 0 .../101-bram-config/minitest}/diff.mk | 0 .../101-bram-config/minitest}/env.sh | 0 .../101-bram-config/minitest}/runme.sh | 0 .../101-bram-config/minitest}/runme.tcl | 0 .../101-bram-config/minitest}/top.v | 128 ----- fuzzers/102-bram-data/minitest/.gitignore | 1 + fuzzers/102-bram-data/minitest/Makefile | 29 + fuzzers/102-bram-data/minitest/diff.mk | 11 + fuzzers/102-bram-data/minitest/runme.sh | 18 + fuzzers/102-bram-data/minitest/runme.tcl | 31 ++ fuzzers/102-bram-data/minitest/top.v | 508 ++++++++++++++++++ 14 files changed, 602 insertions(+), 145 deletions(-) rename {minitests/bram => fuzzers/101-bram-config/minitest}/.gitignore (100%) rename {minitests/bram => fuzzers/101-bram-config/minitest}/Makefile (50%) rename {minitests/bram => fuzzers/101-bram-config/minitest}/README.md (100%) rename {minitests/bram => fuzzers/101-bram-config/minitest}/diff.mk (100%) rename {minitests/bram => fuzzers/101-bram-config/minitest}/env.sh (100%) rename {minitests/bram => fuzzers/101-bram-config/minitest}/runme.sh (100%) rename {minitests/bram => fuzzers/101-bram-config/minitest}/runme.tcl (100%) rename {minitests/bram => fuzzers/101-bram-config/minitest}/top.v (73%) create mode 100644 fuzzers/102-bram-data/minitest/.gitignore create mode 100644 fuzzers/102-bram-data/minitest/Makefile create mode 100644 fuzzers/102-bram-data/minitest/diff.mk create mode 100644 fuzzers/102-bram-data/minitest/runme.sh create mode 100644 fuzzers/102-bram-data/minitest/runme.tcl create mode 100644 fuzzers/102-bram-data/minitest/top.v diff --git a/minitests/bram/.gitignore b/fuzzers/101-bram-config/minitest/.gitignore similarity index 100% rename from minitests/bram/.gitignore rename to fuzzers/101-bram-config/minitest/.gitignore diff --git a/minitests/bram/Makefile b/fuzzers/101-bram-config/minitest/Makefile similarity index 50% rename from minitests/bram/Makefile rename to fuzzers/101-bram-config/minitest/Makefile index f0f385fa..83cf4a70 100644 --- a/minitests/bram/Makefile +++ b/fuzzers/101-bram-config/minitest/Makefile @@ -1,4 +1,7 @@ -all: build/env build/roi_bramd_bit01.diff build/roi_bramd_bits01.diff build/roi_bramds_bit01.diff build/roi_bramis_bit01.diff +# WARNING: probably don't do more than -j 2 +# diff.mk can overlap in a few cases + +all: build/env build/roi_brami_bit01.diff build/roi_bramis_bit01.diff build/roi_bram18_width.diff build/roi_bram18_write_mode.diff build/roi_bram18_ram_mode.diff clean: rm -rf build @@ -7,22 +10,6 @@ clean: build/env: test "$(XRAY_PART)" = "xc7a50tfgg484-1" -# Toggle one bit to locate where first BRAM data is (BRAM18) -build/roi_bram18d_bit01.diff: - $(MAKE) -f diff.mk OUT_DIFF=build/roi_bram18d_bit01.diff PRJL=roi_bram18d_bit0 PRJR=roi_bram18d_bit1 - -# Toggle one bit to locate where first BRAM data is (BRAM36) -build/roi_bram36d_bit01.diff: - $(MAKE) -f diff.mk OUT_DIFF=build/roi_bram36d_bit01.diff PRJL=roi_bram36d_bit0 PRJR=roi_bram36d_bit1 - -# Toggle all bits in a single BRAM data section -build/roi_bramd_bits01.diff: - $(MAKE) -f diff.mk OUT_DIFF=build/roi_bramd_bits01.diff PRJL=roi_bramd_bits0 PRJR=roi_bramd_bits1 - -# Toggle one bit in each BRAM data section -build/roi_bramds_bit01.diff: - $(MAKE) -f diff.mk OUT_DIFF=build/roi_bramds_bit01.diff PRJL=roi_bramds_bit0 PRJR=roi_bramds_bit1 - # Toggle one bit in BRAM config section build/roi_brami_bit01.diff: $(MAKE) -f diff.mk OUT_DIFF=build/roi_brami_bit01.diff PRJL=roi_brami_bit0 PRJR=roi_brami_bit1 diff --git a/minitests/bram/README.md b/fuzzers/101-bram-config/minitest/README.md similarity index 100% rename from minitests/bram/README.md rename to fuzzers/101-bram-config/minitest/README.md diff --git a/minitests/bram/diff.mk b/fuzzers/101-bram-config/minitest/diff.mk similarity index 100% rename from minitests/bram/diff.mk rename to fuzzers/101-bram-config/minitest/diff.mk diff --git a/minitests/bram/env.sh b/fuzzers/101-bram-config/minitest/env.sh similarity index 100% rename from minitests/bram/env.sh rename to fuzzers/101-bram-config/minitest/env.sh diff --git a/minitests/bram/runme.sh b/fuzzers/101-bram-config/minitest/runme.sh similarity index 100% rename from minitests/bram/runme.sh rename to fuzzers/101-bram-config/minitest/runme.sh diff --git a/minitests/bram/runme.tcl b/fuzzers/101-bram-config/minitest/runme.tcl similarity index 100% rename from minitests/bram/runme.tcl rename to fuzzers/101-bram-config/minitest/runme.tcl diff --git a/minitests/bram/top.v b/fuzzers/101-bram-config/minitest/top.v similarity index 73% rename from minitests/bram/top.v rename to fuzzers/101-bram-config/minitest/top.v index d481b77e..48bfe895 100644 --- a/minitests/bram/top.v +++ b/fuzzers/101-bram-config/minitest/top.v @@ -31,119 +31,6 @@ module top(input clk, stb, di, output do); ); endmodule -/****************************************************************************** -******************************************************************************* -DATA ROI -******************************************************************************* -******************************************************************************/ - -/****************************************************************************** -Toggle a single data bit to locate a single instance (BRAM36) -******************************************************************************/ - -module roi_bram36d_bit0(input clk, input [255:0] din, output [255:0] dout); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0(1'b0), .INIT({256{1'b0}})) - r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); -endmodule - -module roi_bram36d_bit1(input clk, input [255:0] din, output [255:0] dout); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0(1'b1), .INIT({256{1'b0}})) - r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); -endmodule - -/****************************************************************************** -Toggle a single data bit to locate a single instance (BRAM18) -******************************************************************************/ - -module roi_bram18d_bit0(input clk, input [255:0] din, output [255:0] dout); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y20"), .INIT0(1'b0), .INIT({256{1'b0}})) - r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); -endmodule - -module roi_bram18d_bit1(input clk, input [255:0] din, output [255:0] dout); - ram_RAMB18E1 #(.LOC("RAMB18_X0Y20"), .INIT0(1'b1), .INIT({256{1'b0}})) - r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); -endmodule - -/****************************************************************************** -Toggle all bits to show the size of the data section -******************************************************************************/ - -module roi_bramd_bits0(input clk, input [255:0] din, output [255:0] dout); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0({256{1'b0}}), .INIT({256{1'b0}})) - r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); -endmodule - -module roi_bramd_bits1(input clk, input [255:0] din, output [255:0] dout); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0({256{1'b1}}), .INIT({256{1'b1}})) - r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); -endmodule - -/****************************************************************************** -Toggle one bit per BRAM in the ROI to show pitch between entries -******************************************************************************/ - -module roi_bramds_bit0(input clk, input [255:0] din, output [255:0] dout); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0(1'b0), .INIT({256{1'b0}})) - r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y21"), .INIT0(1'b0), .INIT({256{1'b0}})) - r1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8])); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y22"), .INIT0(1'b0), .INIT({256{1'b0}})) - r2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y23"), .INIT0(1'b0), .INIT({256{1'b0}})) - r3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8])); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y24"), .INIT0(1'b0), .INIT({256{1'b0}})) - r4(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8])); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y25"), .INIT0(1'b0), .INIT({256{1'b0}})) - r5(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8])); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y26"), .INIT0(1'b0), .INIT({256{1'b0}})) - r6(.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8])); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y27"), .INIT0(1'b0), .INIT({256{1'b0}})) - r7(.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8])); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y28"), .INIT0(1'b0), .INIT({256{1'b0}})) - r8(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8])); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y29"), .INIT0(1'b0), .INIT({256{1'b0}})) - r9(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8])); -endmodule - -module roi_bramds_bit1(input clk, input [255:0] din, output [255:0] dout); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0(1'b1), .INIT({256{1'b0}})) - r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y21"), .INIT0(1'b1), .INIT({256{1'b0}})) - r1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8])); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y22"), .INIT0(1'b1), .INIT({256{1'b0}})) - r2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y23"), .INIT0(1'b1), .INIT({256{1'b0}})) - r3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8])); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y24"), .INIT0(1'b1), .INIT({256{1'b0}})) - r4(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8])); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y25"), .INIT0(1'b1), .INIT({256{1'b0}})) - r5(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8])); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y26"), .INIT0(1'b1), .INIT({256{1'b0}})) - r6(.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8])); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y27"), .INIT0(1'b1), .INIT({256{1'b0}})) - r7(.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8])); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y28"), .INIT0(1'b1), .INIT({256{1'b0}})) - r8(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8])); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y29"), .INIT0(1'b1), .INIT({256{1'b0}})) - r9(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8])); -endmodule - -/****************************************************************************** -Set all data bits -******************************************************************************/ - -module roi_bram36_0s(input clk, input [255:0] din, output [255:0] dout); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0({256{1'b0}}), .INIT({256{1'b0}})) - r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); -endmodule - -module roi_bram36_1s(input clk, input [255:0] din, output [255:0] dout); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0({256{1'b1}}), .INIT({256{1'b1}})) - r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); -endmodule - - /****************************************************************************** ******************************************************************************* CONFIG ROI @@ -231,21 +118,6 @@ module roi_invalid(input clk, input [255:0] din, output [255:0] dout); r2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); endmodule -//HCK test -//XXX: what specifically was this testing? -module roi_hck(input clk, input [255:0] din, output [255:0] dout); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y24"), .INIT({256{1'b1}})) - r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y25"), .INIT({256{1'b1}})) - r1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8])); - //HCK - ram_RAMB36E1 #(.LOC("RAMB36_X0Y26"), .INIT({256{1'b1}})) - r2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); - ram_RAMB36E1 #(.LOC("RAMB36_X0Y27"), .INIT({256{1'b1}})) - r3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8])); - -endmodule - /****************************************************************************** READ_WIDTH ******************************************************************************/ diff --git a/fuzzers/102-bram-data/minitest/.gitignore b/fuzzers/102-bram-data/minitest/.gitignore new file mode 100644 index 00000000..378eac25 --- /dev/null +++ b/fuzzers/102-bram-data/minitest/.gitignore @@ -0,0 +1 @@ +build diff --git a/fuzzers/102-bram-data/minitest/Makefile b/fuzzers/102-bram-data/minitest/Makefile new file mode 100644 index 00000000..0d09d460 --- /dev/null +++ b/fuzzers/102-bram-data/minitest/Makefile @@ -0,0 +1,29 @@ +# WARNING: probably don't do more than -j 2 +# diff.mk can overlap in a few cases + +all: build/env build/roi_bram18d_bit01.diff build/roi_bram36d_bit01.diff build/roi_bramd_bits01.diff build/roi_bramds_bit01.diff + +clean: + rm -rf build + +# hard coded LOCs in .v +build/env: + test "$(XRAY_PART)" = "xc7a50tfgg484-1" + +# Toggle one bit to locate where first BRAM data is (BRAM18) +build/roi_bram18d_bit01.diff: + $(MAKE) -f diff.mk OUT_DIFF=build/roi_bram18d_bit01.diff PRJL=roi_bram18d_bit0 PRJR=roi_bram18d_bit1 + +# Toggle one bit to locate where first BRAM data is (BRAM36) +build/roi_bram36d_bit01.diff: + $(MAKE) -f diff.mk OUT_DIFF=build/roi_bram36d_bit01.diff PRJL=roi_bram36d_bit0 PRJR=roi_bram36d_bit1 + +# Toggle all bits in a single BRAM data section +build/roi_bramd_bits01.diff: + $(MAKE) -f diff.mk OUT_DIFF=build/roi_bramd_bits01.diff PRJL=roi_bramd_bits0 PRJR=roi_bramd_bits1 + +# Toggle one bit in each BRAM data section +build/roi_bramds_bit01.diff: + $(MAKE) -f diff.mk OUT_DIFF=build/roi_bramds_bit01.diff PRJL=roi_bramds_bit0 PRJR=roi_bramds_bit1 + + diff --git a/fuzzers/102-bram-data/minitest/diff.mk b/fuzzers/102-bram-data/minitest/diff.mk new file mode 100644 index 00000000..b2c2ff60 --- /dev/null +++ b/fuzzers/102-bram-data/minitest/diff.mk @@ -0,0 +1,11 @@ +all: $(OUT_DIFF) + +$(OUT_DIFF): build/$(PRJL)/design.bits build/$(PRJR)/design.bits + diff build/$(PRJL)/design.bits build/$(PRJR)/design.bits >$(OUT_DIFF) || true + +build/$(PRJL)/design.bits: + PROJECT=$(PRJL) bash runme.sh + +build/$(PRJR)/design.bits: + PROJECT=$(PRJR) bash runme.sh + diff --git a/fuzzers/102-bram-data/minitest/runme.sh b/fuzzers/102-bram-data/minitest/runme.sh new file mode 100644 index 00000000..9390d5ff --- /dev/null +++ b/fuzzers/102-bram-data/minitest/runme.sh @@ -0,0 +1,18 @@ +#!/bin/bash + +set -ex + +: "${PROJECT:?Need to set PROJECT non-empty}" + +# Create build dir +export SRC_DIR=$PWD +BUILD_DIR=build/$PROJECT +mkdir -p $BUILD_DIR +cd $BUILD_DIR + +export TOP_V=$SRC_DIR/top.v + +vivado -mode batch -source $SRC_DIR/runme.tcl +${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit +test -z "$(fgrep CRITICAL vivado.log)" + diff --git a/fuzzers/102-bram-data/minitest/runme.tcl b/fuzzers/102-bram-data/minitest/runme.tcl new file mode 100644 index 00000000..6aa1f9eb --- /dev/null +++ b/fuzzers/102-bram-data/minitest/runme.tcl @@ -0,0 +1,31 @@ +create_project -force -part $::env(XRAY_PART) design design +#read_verilog $::env(SRC_DIR)/$::env(PROJECT).v +read_verilog $::env(TOP_V) +synth_design -top top -flatten_hierarchy none -verilog_define ROI=$::env(PROJECT) + +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] + +create_pblock roi +set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi] +add_cells_to_pblock [get_pblocks roi] [get_cells roi] +resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" + +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] + +place_design +route_design + +write_checkpoint -force design.dcp + +# set_property BITSTREAM.GENERAL.DEBUGBITSTREAM Yes [current_design] +# BRAM SDP WEA check, to make test slightly easier to write +set_property IS_ENABLED 0 [get_drc_checks {REQP-1931}] +write_bitstream -force design.bit + diff --git a/fuzzers/102-bram-data/minitest/top.v b/fuzzers/102-bram-data/minitest/top.v new file mode 100644 index 00000000..f577e6d7 --- /dev/null +++ b/fuzzers/102-bram-data/minitest/top.v @@ -0,0 +1,508 @@ +`ifndef ROI +ERROR: must set ROI +`endif + +module top(input clk, stb, di, output do); + localparam integer DIN_N = 256; + localparam integer DOUT_N = 256; + + reg [DIN_N-1:0] din; + wire [DOUT_N-1:0] dout; + + reg [DIN_N-1:0] din_shr; + reg [DOUT_N-1:0] dout_shr; + + always @(posedge clk) begin + din_shr <= {din_shr, di}; + dout_shr <= {dout_shr, din_shr[DIN_N-1]}; + if (stb) begin + din <= din_shr; + dout_shr <= dout; + end + end + + assign do = dout_shr[DOUT_N-1]; + + `ROI + roi ( + .clk(clk), + .din(din), + .dout(dout) + ); +endmodule + +/****************************************************************************** +******************************************************************************* +DATA ROI +******************************************************************************* +******************************************************************************/ + +/****************************************************************************** +Toggle a single data bit to locate a single instance (BRAM36) +******************************************************************************/ + +module roi_bram36d_bit0(input clk, input [255:0] din, output [255:0] dout); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0(1'b0), .INIT({256{1'b0}})) + r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); +endmodule + +module roi_bram36d_bit1(input clk, input [255:0] din, output [255:0] dout); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0(1'b1), .INIT({256{1'b0}})) + r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); +endmodule + +/****************************************************************************** +Toggle a single data bit to locate a single instance (BRAM18) +******************************************************************************/ + +module roi_bram18d_bit0(input clk, input [255:0] din, output [255:0] dout); + ram_RAMB18E1 #(.LOC("RAMB18_X0Y20"), .INIT0(1'b0), .INIT({256{1'b0}})) + r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); +endmodule + +module roi_bram18d_bit1(input clk, input [255:0] din, output [255:0] dout); + ram_RAMB18E1 #(.LOC("RAMB18_X0Y20"), .INIT0(1'b1), .INIT({256{1'b0}})) + r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); +endmodule + +/****************************************************************************** +Toggle all bits to show the size of the data section +******************************************************************************/ + +module roi_bramd_bits0(input clk, input [255:0] din, output [255:0] dout); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0({256{1'b0}}), .INIT({256{1'b0}})) + r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); +endmodule + +module roi_bramd_bits1(input clk, input [255:0] din, output [255:0] dout); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0({256{1'b1}}), .INIT({256{1'b1}})) + r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); +endmodule + +/****************************************************************************** +Toggle one bit per BRAM in the ROI to show pitch between entries +******************************************************************************/ + +module roi_bramds_bit0(input clk, input [255:0] din, output [255:0] dout); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0(1'b0), .INIT({256{1'b0}})) + r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y21"), .INIT0(1'b0), .INIT({256{1'b0}})) + r1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y22"), .INIT0(1'b0), .INIT({256{1'b0}})) + r2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y23"), .INIT0(1'b0), .INIT({256{1'b0}})) + r3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y24"), .INIT0(1'b0), .INIT({256{1'b0}})) + r4(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y25"), .INIT0(1'b0), .INIT({256{1'b0}})) + r5(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y26"), .INIT0(1'b0), .INIT({256{1'b0}})) + r6(.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y27"), .INIT0(1'b0), .INIT({256{1'b0}})) + r7(.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y28"), .INIT0(1'b0), .INIT({256{1'b0}})) + r8(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y29"), .INIT0(1'b0), .INIT({256{1'b0}})) + r9(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8])); +endmodule + +module roi_bramds_bit1(input clk, input [255:0] din, output [255:0] dout); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0(1'b1), .INIT({256{1'b0}})) + r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y21"), .INIT0(1'b1), .INIT({256{1'b0}})) + r1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y22"), .INIT0(1'b1), .INIT({256{1'b0}})) + r2(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y23"), .INIT0(1'b1), .INIT({256{1'b0}})) + r3(.clk(clk), .din(din[ 24 +: 8]), .dout(dout[ 24 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y24"), .INIT0(1'b1), .INIT({256{1'b0}})) + r4(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y25"), .INIT0(1'b1), .INIT({256{1'b0}})) + r5(.clk(clk), .din(din[ 40 +: 8]), .dout(dout[ 40 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y26"), .INIT0(1'b1), .INIT({256{1'b0}})) + r6(.clk(clk), .din(din[ 48 +: 8]), .dout(dout[ 48 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y27"), .INIT0(1'b1), .INIT({256{1'b0}})) + r7(.clk(clk), .din(din[ 56 +: 8]), .dout(dout[ 56 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y28"), .INIT0(1'b1), .INIT({256{1'b0}})) + r8(.clk(clk), .din(din[ 64 +: 8]), .dout(dout[ 64 +: 8])); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y29"), .INIT0(1'b1), .INIT({256{1'b0}})) + r9(.clk(clk), .din(din[ 72 +: 8]), .dout(dout[ 72 +: 8])); +endmodule + +/****************************************************************************** +Set all data bits +******************************************************************************/ + +module roi_bram36_0s(input clk, input [255:0] din, output [255:0] dout); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0({256{1'b0}}), .INIT({256{1'b0}})) + r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); +endmodule + +module roi_bram36_1s(input clk, input [255:0] din, output [255:0] dout); + ram_RAMB36E1 #(.LOC("RAMB36_X0Y20"), .INIT0({256{1'b1}}), .INIT({256{1'b1}})) + r0(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); +endmodule + + +/****************************************************************************** +******************************************************************************* +Library +******************************************************************************* +******************************************************************************/ + + +/* +Site RAMB18_X0Y42 +Pushed it outside the pblock +lets extend pblock + +for i in xrange(0x08): print '.INITP_%02X(INIT),' % i +for i in xrange(0x40): print '.INIT_%02X(INIT),' % i +*/ +module ram_RAMB18E1 (input clk, input [7:0] din, output [7:0] dout); + parameter LOC = ""; + + parameter INIT0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + parameter IS_CLKARDCLK_INVERTED = 1'b0; + parameter IS_CLKBWRCLK_INVERTED = 1'b0; + parameter IS_ENARDEN_INVERTED = 1'b0; + parameter IS_ENBWREN_INVERTED = 1'b0; + parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0; + parameter IS_RSTRAMB_INVERTED = 1'b0; + parameter IS_RSTREGARSTREG_INVERTED = 1'b0; + parameter IS_RSTREGB_INVERTED = 1'b0; + parameter RAM_MODE = "TDP"; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + + parameter DOA_REG = 1'b0; + parameter DOB_REG = 1'b0; + parameter SRVAL_A = 18'b0; + parameter SRVAL_B = 18'b0; + parameter INIT_A = 18'b0; + parameter INIT_B = 18'b0; + + parameter READ_WIDTH_A = 0; + parameter READ_WIDTH_B = 0; + parameter WRITE_WIDTH_A = 0; + parameter WRITE_WIDTH_B = 0; + + (* LOC=LOC *) + RAMB18E1 #( + .INITP_00(INIT), + .INITP_01(INIT), + .INITP_02(INIT), + .INITP_03(INIT), + .INITP_04(INIT), + .INITP_05(INIT), + .INITP_06(INIT), + .INITP_07(INIT), + + .INIT_00(INIT0), + .INIT_01(INIT), + .INIT_02(INIT), + .INIT_03(INIT), + .INIT_04(INIT), + .INIT_05(INIT), + .INIT_06(INIT), + .INIT_07(INIT), + .INIT_08(INIT), + .INIT_09(INIT), + .INIT_0A(INIT), + .INIT_0B(INIT), + .INIT_0C(INIT), + .INIT_0D(INIT), + .INIT_0E(INIT), + .INIT_0F(INIT), + .INIT_10(INIT), + .INIT_11(INIT), + .INIT_12(INIT), + .INIT_13(INIT), + .INIT_14(INIT), + .INIT_15(INIT), + .INIT_16(INIT), + .INIT_17(INIT), + .INIT_18(INIT), + .INIT_19(INIT), + .INIT_1A(INIT), + .INIT_1B(INIT), + .INIT_1C(INIT), + .INIT_1D(INIT), + .INIT_1E(INIT), + .INIT_1F(INIT), + .INIT_20(INIT), + .INIT_21(INIT), + .INIT_22(INIT), + .INIT_23(INIT), + .INIT_24(INIT), + .INIT_25(INIT), + .INIT_26(INIT), + .INIT_27(INIT), + .INIT_28(INIT), + .INIT_29(INIT), + .INIT_2A(INIT), + .INIT_2B(INIT), + .INIT_2C(INIT), + .INIT_2D(INIT), + .INIT_2E(INIT), + .INIT_2F(INIT), + .INIT_30(INIT), + .INIT_31(INIT), + .INIT_32(INIT), + .INIT_33(INIT), + .INIT_34(INIT), + .INIT_35(INIT), + .INIT_36(INIT), + .INIT_37(INIT), + .INIT_38(INIT), + .INIT_39(INIT), + .INIT_3A(INIT), + .INIT_3B(INIT), + .INIT_3C(INIT), + .INIT_3D(INIT), + .INIT_3E(INIT), + .INIT_3F(INIT), + + .IS_CLKARDCLK_INVERTED(IS_CLKARDCLK_INVERTED), + .IS_CLKBWRCLK_INVERTED(IS_CLKBWRCLK_INVERTED), + .IS_ENARDEN_INVERTED(IS_ENARDEN_INVERTED), + .IS_ENBWREN_INVERTED(IS_ENBWREN_INVERTED), + .IS_RSTRAMARSTRAM_INVERTED(IS_RSTRAMARSTRAM_INVERTED), + .IS_RSTRAMB_INVERTED(IS_RSTRAMB_INVERTED), + .IS_RSTREGARSTREG_INVERTED(IS_RSTREGARSTREG_INVERTED), + .IS_RSTREGB_INVERTED(IS_RSTREGB_INVERTED), + .RAM_MODE(RAM_MODE), + .WRITE_MODE_A(WRITE_MODE_A), + .WRITE_MODE_B(WRITE_MODE_B), + + .DOA_REG(DOA_REG), + .DOB_REG(DOB_REG), + .SRVAL_A(SRVAL_A), + .SRVAL_B(SRVAL_B), + .INIT_A(INIT_A), + .INIT_B(INIT_B), + + .READ_WIDTH_A(READ_WIDTH_A), + .READ_WIDTH_B(READ_WIDTH_B), + .WRITE_WIDTH_A(WRITE_WIDTH_A), + .WRITE_WIDTH_B(WRITE_WIDTH_B) + ) ram ( + .CLKARDCLK(din[0]), + .CLKBWRCLK(din[1]), + .ENARDEN(din[2]), + .ENBWREN(din[3]), + .REGCEAREGCE(din[4]), + .REGCEB(din[5]), + .RSTRAMARSTRAM(din[6]), + .RSTRAMB(din[7]), + .RSTREGARSTREG(din[0]), + .RSTREGB(din[1]), + .ADDRARDADDR(din[2]), + .ADDRBWRADDR(din[3]), + .DIADI(din[4]), + .DIBDI(din[5]), + .DIPADIP(din[6]), + .DIPBDIP(din[7]), + .WEA(din[0]), + .WEBWE(din[1]), + .DOADO(dout[0]), + .DOBDO(dout[1]), + .DOPADOP(dout[2]), + .DOPBDOP(dout[3])); + +endmodule + +module ram_RAMB36E1 (input clk, input [7:0] din, output [7:0] dout); + parameter LOC = ""; + parameter INIT0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter IS_ENARDEN_INVERTED = 1'b0; + + (* LOC=LOC *) + RAMB36E1 #( + .INITP_00(INIT), + .INITP_01(INIT), + .INITP_02(INIT), + .INITP_03(INIT), + .INITP_04(INIT), + .INITP_05(INIT), + .INITP_06(INIT), + .INITP_07(INIT), + .INITP_08(INIT), + .INITP_09(INIT), + .INITP_0A(INIT), + .INITP_0B(INIT), + .INITP_0C(INIT), + .INITP_0D(INIT), + .INITP_0E(INIT), + .INITP_0F(INIT), + + .INIT_00(INIT0), + .INIT_01(INIT), + .INIT_02(INIT), + .INIT_03(INIT), + .INIT_04(INIT), + .INIT_05(INIT), + .INIT_06(INIT), + .INIT_07(INIT), + .INIT_08(INIT), + .INIT_09(INIT), + .INIT_0A(INIT), + .INIT_0B(INIT), + .INIT_0C(INIT), + .INIT_0D(INIT), + .INIT_0E(INIT), + .INIT_0F(INIT), + .INIT_10(INIT), + .INIT_11(INIT), + .INIT_12(INIT), + .INIT_13(INIT), + .INIT_14(INIT), + .INIT_15(INIT), + .INIT_16(INIT), + .INIT_17(INIT), + .INIT_18(INIT), + .INIT_19(INIT), + .INIT_1A(INIT), + .INIT_1B(INIT), + .INIT_1C(INIT), + .INIT_1D(INIT), + .INIT_1E(INIT), + .INIT_1F(INIT), + .INIT_20(INIT), + .INIT_21(INIT), + .INIT_22(INIT), + .INIT_23(INIT), + .INIT_24(INIT), + .INIT_25(INIT), + .INIT_26(INIT), + .INIT_27(INIT), + .INIT_28(INIT), + .INIT_29(INIT), + .INIT_2A(INIT), + .INIT_2B(INIT), + .INIT_2C(INIT), + .INIT_2D(INIT), + .INIT_2E(INIT), + .INIT_2F(INIT), + .INIT_30(INIT), + .INIT_31(INIT), + .INIT_32(INIT), + .INIT_33(INIT), + .INIT_34(INIT), + .INIT_35(INIT), + .INIT_36(INIT), + .INIT_37(INIT), + .INIT_38(INIT), + .INIT_39(INIT), + .INIT_3A(INIT), + .INIT_3B(INIT), + .INIT_3C(INIT), + .INIT_3D(INIT), + .INIT_3E(INIT), + .INIT_3F(INIT), + + .INIT_40(INIT), + .INIT_41(INIT), + .INIT_42(INIT), + .INIT_43(INIT), + .INIT_44(INIT), + .INIT_45(INIT), + .INIT_46(INIT), + .INIT_47(INIT), + .INIT_48(INIT), + .INIT_49(INIT), + .INIT_4A(INIT), + .INIT_4B(INIT), + .INIT_4C(INIT), + .INIT_4D(INIT), + .INIT_4E(INIT), + .INIT_4F(INIT), + .INIT_50(INIT), + .INIT_51(INIT), + .INIT_52(INIT), + .INIT_53(INIT), + .INIT_54(INIT), + .INIT_55(INIT), + .INIT_56(INIT), + .INIT_57(INIT), + .INIT_58(INIT), + .INIT_59(INIT), + .INIT_5A(INIT), + .INIT_5B(INIT), + .INIT_5C(INIT), + .INIT_5D(INIT), + .INIT_5E(INIT), + .INIT_5F(INIT), + .INIT_60(INIT), + .INIT_61(INIT), + .INIT_62(INIT), + .INIT_63(INIT), + .INIT_64(INIT), + .INIT_65(INIT), + .INIT_66(INIT), + .INIT_67(INIT), + .INIT_68(INIT), + .INIT_69(INIT), + .INIT_6A(INIT), + .INIT_6B(INIT), + .INIT_6C(INIT), + .INIT_6D(INIT), + .INIT_6E(INIT), + .INIT_6F(INIT), + .INIT_70(INIT), + .INIT_71(INIT), + .INIT_72(INIT), + .INIT_73(INIT), + .INIT_74(INIT), + .INIT_75(INIT), + .INIT_76(INIT), + .INIT_77(INIT), + .INIT_78(INIT), + .INIT_79(INIT), + .INIT_7A(INIT), + .INIT_7B(INIT), + .INIT_7C(INIT), + .INIT_7D(INIT), + .INIT_7E(INIT), + .INIT_7F(INIT), + + .IS_CLKARDCLK_INVERTED(1'b0), + .IS_CLKBWRCLK_INVERTED(1'b0), + .IS_ENARDEN_INVERTED(IS_ENARDEN_INVERTED), + .IS_ENBWREN_INVERTED(1'b0), + .IS_RSTRAMARSTRAM_INVERTED(1'b0), + .IS_RSTRAMB_INVERTED(1'b0), + .IS_RSTREGARSTREG_INVERTED(1'b0), + .IS_RSTREGB_INVERTED(1'b0), + .RAM_MODE("TDP"), + .WRITE_MODE_A("WRITE_FIRST"), + .WRITE_MODE_B("WRITE_FIRST"), + .SIM_DEVICE("VIRTEX6") + ) ram ( + .CLKARDCLK(din[0]), + .CLKBWRCLK(din[1]), + .ENARDEN(din[2]), + .ENBWREN(din[3]), + .REGCEAREGCE(din[4]), + .REGCEB(din[5]), + .RSTRAMARSTRAM(din[6]), + .RSTRAMB(din[7]), + .RSTREGARSTREG(din[0]), + .RSTREGB(din[1]), + .ADDRARDADDR(din[2]), + .ADDRBWRADDR(din[3]), + .DIADI(din[4]), + .DIBDI(din[5]), + .DIPADIP(din[6]), + .DIPBDIP(din[7]), + .WEA(din[0]), + .WEBWE(din[1]), + .DOADO(dout[0]), + .DOBDO(dout[1]), + .DOPADOP(dout[2]), + .DOPBDOP(dout[3])); +endmodule +