From 53002168fd7cfb6852466bddbf9298badbb0048f Mon Sep 17 00:00:00 2001 From: John McMaster Date: Wed, 6 Dec 2017 15:15:00 -0800 Subject: [PATCH] rom minitest Signed-off-by: John McMaster Signed-off-by: Tim 'mithro' Ansell --- minitests/rom/.gitignore | 8 +++ minitests/rom/Makefile | 27 ++++++++++ minitests/rom/README.txt | 4 ++ minitests/rom/runme.sh | 7 +++ minitests/rom/runme.tcl | 26 +++++++++ minitests/rom/top.v | 111 +++++++++++++++++++++++++++++++++++++++ 6 files changed, 183 insertions(+) create mode 100644 minitests/rom/.gitignore create mode 100644 minitests/rom/Makefile create mode 100644 minitests/rom/README.txt create mode 100755 minitests/rom/runme.sh create mode 100644 minitests/rom/runme.tcl create mode 100644 minitests/rom/top.v diff --git a/minitests/rom/.gitignore b/minitests/rom/.gitignore new file mode 100644 index 00000000..82a01aa0 --- /dev/null +++ b/minitests/rom/.gitignore @@ -0,0 +1,8 @@ +/.Xil +/design/ +/design.bit +/design.bits +/design.dcp +/usage_statistics_webtalk.* +/vivado* +/design.txt diff --git a/minitests/rom/Makefile b/minitests/rom/Makefile new file mode 100644 index 00000000..7e47a0e0 --- /dev/null +++ b/minitests/rom/Makefile @@ -0,0 +1,27 @@ +N := 3 +SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N))) +SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS)) + +all: + bash runme.sh + test -z $(fgrep CRITICAL vivado.log) + ${XRAY_SEGPRINT} -z -D design.bits >design.txt + +database: $(SPECIMENS_OK) + ${XRAY_SEGMATCH} -o seg_clblx.segbits $(addsuffix /segdata_clbl[lm]_[lr].txt,$(SPECIMENS)) + +pushdb: + ${XRAY_MERGEDDB} clbll_l seg_clblx.segbits + ${XRAY_MERGEDDB} clbll_r seg_clblx.segbits + ${XRAY_MERGEDDB} clblm_l seg_clblx.segbits + ${XRAY_MERGEDDB} clblm_r seg_clblx.segbits + +$(SPECIMENS_OK): + bash generate.sh $(subst /OK,,$@) + touch $@ + +clean: + rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit design.txt .Xil + +.PHONY: database pushdb clean + diff --git a/minitests/rom/README.txt b/minitests/rom/README.txt new file mode 100644 index 00000000..07f50a5f --- /dev/null +++ b/minitests/rom/README.txt @@ -0,0 +1,4 @@ +Test to verify that all the ROM* primitives are just regular LUTs and not BRAMs with init values + +Result: +Confirmed: floorplan shows as LUTs and no unknown bits observed diff --git a/minitests/rom/runme.sh b/minitests/rom/runme.sh new file mode 100755 index 00000000..536f2346 --- /dev/null +++ b/minitests/rom/runme.sh @@ -0,0 +1,7 @@ +#!/bin/bash + +set -ex +# rm -f vivado*.log vivado*.jou +vivado -mode batch -source runme.tcl +${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit +#${XRAY_SEGPRINT} design.bits SLICE_X16Y100 SLICE_X16Y101 SLICE_X16Y102 SLICE_X16Y103 diff --git a/minitests/rom/runme.tcl b/minitests/rom/runme.tcl new file mode 100644 index 00000000..86162f92 --- /dev/null +++ b/minitests/rom/runme.tcl @@ -0,0 +1,26 @@ +create_project -force -part $::env(XRAY_PART) design design +read_verilog top.v +synth_design -top top + +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] + +create_pblock roi +set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi] +add_cells_to_pblock [get_pblocks roi] [get_cells roi] +resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" + +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] + +place_design +route_design + +write_checkpoint -force design.dcp +write_bitstream -force design.bit + diff --git a/minitests/rom/top.v b/minitests/rom/top.v new file mode 100644 index 00000000..8fb127ad --- /dev/null +++ b/minitests/rom/top.v @@ -0,0 +1,111 @@ +/* +ROM128X1: 128-Deep by 1-Wide ROM +ROM256X1: 256-Deep by 1-Wide ROM +ROM32X1: 32-Deep by 1-Wide ROM +ROM64X1: 64-Deep by 1-Wide ROM +*/ + +module top(input clk, stb, di, output do); + localparam integer DIN_N = 256; + localparam integer DOUT_N = 256; + + reg [DIN_N-1:0] din; + wire [DOUT_N-1:0] dout; + + reg [DIN_N-1:0] din_shr; + reg [DOUT_N-1:0] dout_shr; + + always @(posedge clk) begin + din_shr <= {din_shr, di}; + dout_shr <= {dout_shr, din_shr[DIN_N-1]}; + if (stb) begin + din <= din_shr; + dout_shr <= dout; + end + end + + assign do = dout_shr[DOUT_N-1]; + + roi roi ( + .clk(clk), + .din(din), + .dout(dout) + ); +endmodule + +module roi(input clk, input [255:0] din, output [255:0] dout); + rom_ROM128X1 #(.LOC("XXX")) + rom_ROM128X1(.clk(clk), .din(din[ 0 +: 8]), .dout(dout[ 0 +: 8])); + rom_ROM256X1 #(.LOC("XXX")) + rom_ROM256X1(.clk(clk), .din(din[ 8 +: 8]), .dout(dout[ 8 +: 8])); + rom_ROM32X1 #(.LOC("XXX")) + rom_ROM32X1(.clk(clk), .din(din[ 16 +: 8]), .dout(dout[ 16 +: 8])); + rom_ROM64X1 #(.LOC("XXX")) + rom_ROM64X1(.clk(clk), .din(din[ 32 +: 8]), .dout(dout[ 32 +: 8])); +endmodule + +//****************************************************************************** +//BOUTMUX tests + +/* +Cell as SLICEM D6LUT + C6LUT + F7BMUX +*/ +module rom_ROM128X1 (input clk, input [7:0] din, output [7:0] dout); + parameter LOC="SLICE_FIXME"; + + //ROM128X1 #(.LOC(LOC), .N(N)) + ROM128X1 #(.INIT(128'b0)) + rom( + .O(dout[0]), + .A0(din[0]), + .A1(din[1]), + .A2(din[2]), + .A3(din[3]), + .A4(din[4]), + .A5(din[5]), + .A6(din[6])); +endmodule + +module rom_ROM256X1 (input clk, input [7:0] din, output [7:0] dout); + parameter LOC="SLICE_FIXME"; + + ROM256X1 #(.INIT(256'b0)) + rom( + .O(dout[0]), + .A0(din[0]), + .A1(din[1]), + .A2(din[2]), + .A3(din[3]), + .A4(din[4]), + .A5(din[5]), + .A6(din[6]), + .A7(din[7])); +endmodule + +module rom_ROM32X1 (input clk, input [7:0] din, output [7:0] dout); + parameter LOC="SLICE_FIXME"; + + ROM32X1 #(.INIT(32'b0)) + rom( + .O(dout[0]), + .A0(din[0]), + .A1(din[1]), + .A2(din[2]), + .A3(din[3]), + .A4(din[4])); +endmodule + +module rom_ROM64X1 (input clk, input [7:0] din, output [7:0] dout); + parameter LOC="SLICE_FIXME"; + + ROM64X1 #(.INIT(64'b0)) + rom( + .O(dout[0]), + .A0(din[0]), + .A1(din[1]), + .A2(din[2]), + .A3(din[3]), + .A4(din[4]), + .A5(din[5])); +endmodule +