From 52bae5e02fbd68e4b2b9eedcf5efcf773f899f76 Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Tue, 30 Oct 2018 09:14:34 -0700
Subject: [PATCH] Add wires used for ROI ports.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 minitests/roi_harness/Makefile              | 13 ++++++-
 minitests/roi_harness/create_design_json.py | 43 +++++++++++++++++++++
 minitests/roi_harness/runme.sh              |  2 +-
 minitests/roi_harness/runme.tcl             |  8 ++++
 prjxray/tile_segbits.py                     |  5 +++
 5 files changed, 68 insertions(+), 3 deletions(-)

diff --git a/minitests/roi_harness/Makefile b/minitests/roi_harness/Makefile
index 9c03896b..ff7d2fdc 100644
--- a/minitests/roi_harness/Makefile
+++ b/minitests/roi_harness/Makefile
@@ -1,16 +1,25 @@
 BUILD_DIR=build
+HARNESS_DIR ?= harness
 export BUILD_DIR
 
 XRAY_PINCFG ?= BASYS3-SWBUT
 export XRAY_PINCFG
 
+HARNESS_FILES=$(BUILD_DIR)/design.bit $(BUILD_DIR)/design.txt $(BUILD_DIR)/design.json $(BUILD_DIR)/design.dcp
+
 # official demo configuration
-all:
+all: $(HARNESS_FILES)
+
+$(HARNESS_FILES): runme.sh runme.tcl
 	./runme.sh
 
+copy: $(HARNESS_FILES)
+	mkdir -p $(HARNESS_DIR)
+	cp $(HARNESS_FILES) $(HARNESS_DIR)
+
 clean:
 	rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit design.txt .Xil
 	rm -rf $(BUILD_DIR) *~
 
-.PHONY: all clean
+.PHONY: all clean copy
 
diff --git a/minitests/roi_harness/create_design_json.py b/minitests/roi_harness/create_design_json.py
index a6717dad..653f2d50 100644
--- a/minitests/roi_harness/create_design_json.py
+++ b/minitests/roi_harness/create_design_json.py
@@ -2,14 +2,27 @@ import json
 import csv
 import argparse
 import sys
+from prjxray.db import Database
+from prjxray.roi import Roi
+from prjxray.util import get_db_root
 
 
+def set_port_wires(ports, name, pin, wires_outside_roi):
+    for port in ports:
+        if name == port['name']:
+            port['wires_outside_roi'] = wires_outside_roi
+            assert port['pin'] == pin
+            return
+
+    assert False, name
+
 def main():
     parser = argparse.ArgumentParser(
         description=
         "Creates design.json from output of ROI generation tcl script.")
     parser.add_argument('--design_txt', required=True)
     parser.add_argument('--design_info_txt', required=True)
+    parser.add_argument('--pad_wires', required=True)
 
     args = parser.parse_args()
 
@@ -26,6 +39,36 @@ def main():
 
             j['info'][name] = int(value)
 
+    db = Database(get_db_root())
+    grid = db.grid()
+
+    roi = Roi(
+            db=db,
+            x1=j['info']['GRID_X_MIN'],
+            y1=j['info']['GRID_Y_MIN'],
+            x2=j['info']['GRID_X_MAX'],
+            y2=j['info']['GRID_Y_MAX'],
+            )
+
+    with open(args.pad_wires) as f:
+        for l in f:
+            parts = l.strip().split(' ')
+            name = parts[0]
+            pin = parts[1]
+            wires = parts[2:]
+
+            wires_outside_roi = []
+
+            for wire in wires:
+                tile = wire.split('/')[0]
+
+                loc = grid.loc_of_tilename(tile)
+
+                if not roi.tile_in_roi(loc):
+                    wires_outside_roi.append(wire)
+
+            set_port_wires(j['ports'], name, pin, wires_outside_roi)
+
     json.dump(j, sys.stdout, indent=2, sort_keys=True)
 
 
diff --git a/minitests/roi_harness/runme.sh b/minitests/roi_harness/runme.sh
index 592a7cb0..e6034ccc 100755
--- a/minitests/roi_harness/runme.sh
+++ b/minitests/roi_harness/runme.sh
@@ -59,7 +59,7 @@ ${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit
 ${XRAY_SEGPRINT} -zd design.bits >design.segp
 ${XRAY_DIR}/utils/bits2fasm.py --verbose design.bits > design.fasm
 ${XRAY_DIR}/utils/fasm2frames.py design.fasm design.frm
-python3 ../create_design_json.py --design_info_txt design_info.txt --design_txt design.txt > design.json
+python3 ../create_design_json.py --design_info_txt design_info.txt --design_txt design.txt --pad_wires design_pad_wires.txt > design.json
 
 # Hack to get around weird clock error related to clk net not found
 # Remove following lines:
diff --git a/minitests/roi_harness/runme.tcl b/minitests/roi_harness/runme.tcl
index 6cf49534..ba5784a9 100644
--- a/minitests/roi_harness/runme.tcl
+++ b/minitests/roi_harness/runme.tcl
@@ -380,6 +380,7 @@ close $fp
 
 # XXX: maybe add IOB?
 set fp [open "design.txt" w]
+set fp_wires [open "design_pad_wires.txt" w]
 puts $fp "name node pin wire"
 # Manual routing
 if {$fixed_xdc eq ""} {
@@ -415,6 +416,9 @@ if {$fixed_xdc eq ""} {
         set pin "$net2pin($net)"
         set wire [node2wire $node]
         puts $fp "$net $node $pin $wire"
+
+        set wires [get_wires -of_objects [get_nets "din_IBUF[$i]"]]
+        puts $fp_wires "$net $pin $wires"
     }
 
     puts "Routing ROI outputs"
@@ -449,9 +453,13 @@ if {$fixed_xdc eq ""} {
         set pin "$net2pin($net)"
         set wire [node2wire $node]
         puts $fp "$net $node $pin $wire"
+
+        set wires [get_wires -of_objects [get_nets "roi/dout[$i]"]]
+        puts $fp_wires "$net $pin $wires"
     }
 }
 close $fp
+close $fp_wires
 
 puts "routing design"
 route_design
diff --git a/prjxray/tile_segbits.py b/prjxray/tile_segbits.py
index b8737b7f..392026b3 100644
--- a/prjxray/tile_segbits.py
+++ b/prjxray/tile_segbits.py
@@ -140,3 +140,8 @@ class TileSegbits(object):
         else:
             for bit in self.segbits[self.feature_addresses[feature][address]]:
                 yield bit
+
+    def frames(self, bits):
+        """ Iterate over frames this tile uses for a given bit location. """
+        for bit in self.segbits.values():
+            yield bits.base_address + bit.word_column