From 51dc4cad9505d1dba38a443a789c82580cf525c8 Mon Sep 17 00:00:00 2001 From: John McMaster Date: Fri, 10 Nov 2017 15:56:42 -0800 Subject: [PATCH] LUT5 vs LUT6 test Signed-off-by: John McMaster Signed-off-by: Tim 'mithro' Ansell --- fuzzers/012-lut5/.gitignore | 2 + fuzzers/012-lut5/Makefile | 21 +++++++ fuzzers/012-lut5/generate.py | 35 +++++++++++ fuzzers/012-lut5/generate.sh | 12 ++++ fuzzers/012-lut5/generate.tcl | 88 ++++++++++++++++++++++++++ fuzzers/012-lut5/top.v | 112 ++++++++++++++++++++++++++++++++++ 6 files changed, 270 insertions(+) create mode 100644 fuzzers/012-lut5/.gitignore create mode 100644 fuzzers/012-lut5/Makefile create mode 100644 fuzzers/012-lut5/generate.py create mode 100644 fuzzers/012-lut5/generate.sh create mode 100644 fuzzers/012-lut5/generate.tcl create mode 100644 fuzzers/012-lut5/top.v diff --git a/fuzzers/012-lut5/.gitignore b/fuzzers/012-lut5/.gitignore new file mode 100644 index 00000000..96a8fae1 --- /dev/null +++ b/fuzzers/012-lut5/.gitignore @@ -0,0 +1,2 @@ +/specimen_[0-9][0-9][0-9]/ +/tilegrid.json diff --git a/fuzzers/012-lut5/Makefile b/fuzzers/012-lut5/Makefile new file mode 100644 index 00000000..90c19eeb --- /dev/null +++ b/fuzzers/012-lut5/Makefile @@ -0,0 +1,21 @@ + +N := 1 +SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N))) +SPECIMENS_OK := $(addsuffix /OK,$(SPECIMENS)) + +database: $(SPECIMENS_OK) + #cp specimen_001/tilegrid.json tilegrid.json + true + +pushdb: + cp tilegrid.json ../../database/$(XRAY_DATABASE)/tilegrid.json + +$(SPECIMENS_OK): + bash generate.sh $(subst /OK,,$@) + touch $@ + +clean: + rm -rf specimen_[0-9][0-9][0-9]/ tilegrid.json vivado*.log vivado*.jou + +.PHONY: database pushdb clean + diff --git a/fuzzers/012-lut5/generate.py b/fuzzers/012-lut5/generate.py new file mode 100644 index 00000000..ec3b7c8d --- /dev/null +++ b/fuzzers/012-lut5/generate.py @@ -0,0 +1,35 @@ +#!/usr/bin/env python3 + +import sys, re + +sys.path.append("../../../utils/") +from segmaker import segmaker + +segmk = segmaker("design.bits") + +print("Loading tags from design.txt") +with open("design.txt", "r") as f: + for line in f: + ''' + puts $fp "$type $tile $grid_x $grid_y $lut $lut_type" + CLBLM_L CLBLM_L_X10Y112 30 39 SLICE_X13Y112/B5LUT LUT5 + CLBLM_L CLBLM_L_X10Y112 30 39 SLICE_X13Y112/A6LUT LUT6 + CLBLM_L CLBLM_L_X10Y112 30 39 SLICE_X12Y112/C6LUT LUT_OR_MEM6 + ''' + line = line.split() + tile_type = line[0] + tile_name = line[1] + grid_x = line[2] + grid_y = line[3] + site_lut_name = line[4] + site, lut_name = site_lut_name.split('/') + lut_type = line[5] + + if lut_type in ('LUT5', 'LUT6'): + which = lut_name[0] + segmk.addtag(site, "%s.LUT5" % which, lut_type == 'LUT5') + #segmk.addtag(site, "%s.LUT6" % which, lut_type == 'LUT6') + +segmk.compile() +segmk.write() + diff --git a/fuzzers/012-lut5/generate.sh b/fuzzers/012-lut5/generate.sh new file mode 100644 index 00000000..a509e83b --- /dev/null +++ b/fuzzers/012-lut5/generate.sh @@ -0,0 +1,12 @@ +#!/bin/bash + +. ../../utils/genheader.sh + +echo '`define SEED 32'"'h$(echo $1 | md5sum | cut -c1-8)" > setseed.vh + +vivado -mode batch -source ../generate.tcl + +for x in design*.bit; do + ../../../tools/bitread -F $XRAY_ROI_FRAMES -o ${x}s -zy $x +done + diff --git a/fuzzers/012-lut5/generate.tcl b/fuzzers/012-lut5/generate.tcl new file mode 100644 index 00000000..fdfafcfd --- /dev/null +++ b/fuzzers/012-lut5/generate.tcl @@ -0,0 +1,88 @@ +create_project -force -part $::env(XRAY_PART) design design + +read_verilog ../top.v +synth_design -top top + +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do] +set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb] + +create_pblock roi +add_cells_to_pblock [get_pblocks roi] [get_cells roi] +resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" + +set_property CFGBVS VCCO [current_design] +set_property CONFIG_VOLTAGE 3.3 [current_design] +set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] + +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] + +place_design +route_design + +write_checkpoint -force design.dcp +write_bitstream -force design.bit + + + + + +# Get all 6LUT and 5LUT in pblock +# A6LUT, B6LUT, A5LUT, etc +set luts [get_bels -of_objects [get_sites -of_objects [get_pblocks roi]] -filter {TYPE =~ LUT*} */*LUT] + + + +set grid_min_x -1 +set grid_max_x -1 +set grid_min_y -1 +set grid_max_y -1 + +foreach lut $luts { + set tile [get_tile -of_objects $lut] + set grid_x [get_property GRID_POINT_X $tile] + set grid_y [get_property GRID_POINT_Y $tile] + + if [expr $grid_min_x < 0 || $grid_x < $grid_min_x] {set grid_min_x $grid_x} + if [expr $grid_max_x < 0 || $grid_x > $grid_max_x] {set grid_max_x $grid_x} + + if [expr $grid_min_y < 0 || $grid_y < $grid_min_y] {set grid_min_y $grid_y} + if [expr $grid_max_y < 0 || $grid_y > $grid_max_y] {set grid_max_y $grid_y} +} + +# set tiles [get_tiles -filter "GRID_POINT_X >= $grid_min_x && GRID_POINT_X <= $grid_max_x && GRID_POINT_Y >= $grid_min_y && GRID_POINT_Y <= $grid_max_y"] +# set fp [open "tiles.txt" w] +# foreach tile $tiles { +# set type [get_property TYPE $tile] +# set grid_x [get_property GRID_POINT_X $tile] +# set grid_y [get_property GRID_POINT_Y $tile] +# set sites [get_sites -quiet -of_objects $tile] +# set typed_sites {} +# +# if [llength $sites] { +# set site_types [get_property SITE_TYPE $sites] +# foreach t $site_types s $sites { +# lappend typed_sites $t $s +# } +# } +# +# puts $fp "$type $tile $grid_x $grid_y $typed_sites" +# } +# close $fp + + +set fp [open "design.txt" w] +foreach lut $luts { + set tile [get_tile -of_objects $lut] + set grid_x [get_property GRID_POINT_X $tile] + set grid_y [get_property GRID_POINT_Y $tile] + set type [get_property TYPE $tile] + set lut_type [get_property TYPE $lut] + + if [get_property IS_USED $lut] { + puts $fp "$type $tile $grid_x $grid_y $lut $lut_type" + } +} +close $fp + diff --git a/fuzzers/012-lut5/top.v b/fuzzers/012-lut5/top.v new file mode 100644 index 00000000..d73ba5d4 --- /dev/null +++ b/fuzzers/012-lut5/top.v @@ -0,0 +1,112 @@ +`include "setseed.vh" + +`define N 1000 + +module top(input clk, stb, di, output do); + localparam integer DIN_N = 6; + localparam integer DOUT_N = `N; + + reg [DIN_N-1:0] din; + wire [DOUT_N-1:0] dout; + + reg [DIN_N-1:0] din_shr; + reg [DOUT_N-1:0] dout_shr; + + always @(posedge clk) begin + din_shr <= {din_shr, di}; + dout_shr <= {dout_shr, din_shr[DIN_N-1]}; + if (stb) begin + din <= din_shr; + dout_shr <= dout; + end + end + + assign do = dout_shr[DOUT_N-1]; + + roi roi ( + .clk(clk), + .din(din), + .dout(dout) + ); +endmodule + +module roi(input clk, input [5:0] din, output [`N-1:0] dout); + function [31:0] xorshift32(input [31:0] v); + begin + xorshift32 = v; + xorshift32 = xorshift32 ^ (xorshift32 << 13); + xorshift32 = xorshift32 ^ (xorshift32 >> 17); + xorshift32 = xorshift32 ^ (xorshift32 << 5); + end + endfunction + + function [31:0] hash32(input [31:0] v); + begin + hash32 = v ^ `SEED; + hash32 = xorshift32(hash32); + hash32 = xorshift32(hash32); + hash32 = xorshift32(hash32); + hash32 = xorshift32(hash32); + end + endfunction + + function [63:0] hash64(input [31:0] v); + begin + hash64[63:32] = hash32(v); + hash64[31: 0] = hash32(~v); + end + endfunction + + genvar i; + generate + for (i = 0; i < `N; i = i+1) begin:is + /* + wire o5; + wire o6; + assign dout[i] = o5 & o6; + LUT5 #( + .INIT(32'h8000_0001 + (i << 16) + 1'b1) + ) lut5 ( + .I0(din[0]), + .I1(din[f1]), + .I2(din[2]), + .I3(din[3]), + .I4(din[4]), + .O(o5) + ); + */ + + wire o6; + wire o2_5; + wire o2_6; + //Randomly take out 1/4 iterations + wire [3:0] hash = hash32(i); + wire opt_out = |hash; + assign dout[i] = o6 & o2_5 & o2_6 & opt_out; + + LUT6 #( + .INIT(64'h8000_0000_0000_0001 + (i << 16)) + ) lut6 ( + .I0(din[0]), + .I1(din[1]), + .I2(din[2]), + .I3(din[3]), + .I4(din[4]), + .I5(din[5]), + .O(o6) + ); + LUT6_2 #( + .INIT(64'h8000_0000_0000_0001 + (i << 8)) + ) lut62 ( + .I0(din[0]), + .I1(din[1]), + .I2(din[2]), + .I3(din[3]), + .I4(din[4]), + .I5(din[5]), + .O5(o2_5), + .O6(o2_6) + ); + end + endgenerate +endmodule