From 4f459cfde3bff8b1908fe6dc231ec71987e15e57 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Thu, 13 Jun 2019 16:39:49 +0200 Subject: [PATCH] Ran format-tcl Signed-off-by: Maciej Kurc --- minitests/litex/src.vivado/top.tcl | 2 +- minitests/litex/src.yosys/top.tcl | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/minitests/litex/src.vivado/top.tcl b/minitests/litex/src.vivado/top.tcl index 2e1eac64..19c7bc05 100644 --- a/minitests/litex/src.vivado/top.tcl +++ b/minitests/litex/src.vivado/top.tcl @@ -22,6 +22,6 @@ report_drc -file top_drc.rpt report_timing_summary -datasheet -max_paths 10 -file top_timing.rpt report_power -file top_power.rpt set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] -write_bitstream -force top.bit +write_bitstream -force top.bit write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit "up 0x0 top.bit" -file top.bin quit diff --git a/minitests/litex/src.yosys/top.tcl b/minitests/litex/src.yosys/top.tcl index 1512797c..e4220653 100644 --- a/minitests/litex/src.yosys/top.tcl +++ b/minitests/litex/src.yosys/top.tcl @@ -21,6 +21,6 @@ report_drc -file top_drc.rpt report_timing_summary -datasheet -max_paths 10 -file top_timing.rpt report_power -file top_power.rpt set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] -write_bitstream -force top.bit +write_bitstream -force top.bit write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit "up 0x0 top.bit" -file top.bin quit