diff --git a/minitests/litex/src.vivado/top.tcl b/minitests/litex/src.vivado/top.tcl
index 2e1eac64..19c7bc05 100644
--- a/minitests/litex/src.vivado/top.tcl
+++ b/minitests/litex/src.vivado/top.tcl
@@ -22,6 +22,6 @@ report_drc -file top_drc.rpt
 report_timing_summary -datasheet -max_paths 10 -file top_timing.rpt
 report_power -file top_power.rpt
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
-write_bitstream -force top.bit 
+write_bitstream -force top.bit
 write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit "up 0x0 top.bit" -file top.bin
 quit
diff --git a/minitests/litex/src.yosys/top.tcl b/minitests/litex/src.yosys/top.tcl
index 1512797c..e4220653 100644
--- a/minitests/litex/src.yosys/top.tcl
+++ b/minitests/litex/src.yosys/top.tcl
@@ -21,6 +21,6 @@ report_drc -file top_drc.rpt
 report_timing_summary -datasheet -max_paths 10 -file top_timing.rpt
 report_power -file top_power.rpt
 set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
-write_bitstream -force top.bit 
+write_bitstream -force top.bit
 write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit "up 0x0 top.bit" -file top.bin
 quit