From 3e851a6256a4b51b67aa4e4f716a74d160e08dd6 Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Thu, 21 Mar 2019 13:41:36 -0700
Subject: [PATCH] Reduce number of active GCLKs in final iterations.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 fuzzers/041-clk-hrow-pips/top.py | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/fuzzers/041-clk-hrow-pips/top.py b/fuzzers/041-clk-hrow-pips/top.py
index 5ac8692d..da45a805 100644
--- a/fuzzers/041-clk-hrow-pips/top.py
+++ b/fuzzers/041-clk-hrow-pips/top.py
@@ -436,7 +436,14 @@ module top();
         wire_name = 'gclk_{}'.format(site)
         gclks.append(wire_name)
 
-        if not mmcm_pll_only:
+
+        include_source = True
+        if mmcm_pll_only:
+            include_source = False
+        elif only_gclk_left(todos):
+            include_source = need_gclk_connection(todos, site)
+
+        if include_source:
             clock_sources.add_clock_source(wire_name, 'ANY')
 
         print("""