diff --git a/docs/architecture/glossary.rst b/docs/architecture/glossary.rst
index 24b8839f..a4e5bdbc 100644
--- a/docs/architecture/glossary.rst
+++ b/docs/architecture/glossary.rst
@@ -25,13 +25,13 @@ Glossary
 
     * Basic BEL - A logic unit which does things.
     * Routing BEL - A unit which is statically configured at routing time.
-     
+
 
   Bitstream
     Binary data that is directly loaded into an :term:`FPGA` to perform
     configuration. Contains configuration :term:`frames <frame>` as well as
     programming sequences and other commands required to load and activate same.
-    
+
   Block RAM
     Block RAM is inbuilt, configurable memory on an :term:`FPGA`, able to store
     more data than the :term:`flip flops <ff>`. The block RAM can function as
@@ -42,7 +42,7 @@ Glossary
   CFA
     A carry or fast adder (CFA) is a logic element on the :term:`FPGA` that
     performs fast arithmetic operations.
-    
+
   Clock
     A clock is a square-wave timing signal (50% on, 50% off) generated by an
     external oscillator and passed into the :term:`FPGA`. The clock frequency
@@ -62,7 +62,7 @@ Glossary
     part of a :term:`horizontal clock row` to one side of the global
     :term:`clock spine`. The term also often refers to the
     :term:`tiles <tile>` that are associated with these clocks.
-    
+
   Clock region
     Portion of a device including up to 12 :term:`clock domains <clock domain>`.
     A clock region is situated to the left or right of the global clock spine,
@@ -90,7 +90,7 @@ Glossary
   Fabric sub region
   FSR
     Another name for :term:`clock region`.
-    
+
   Flip flop
   FF
     A flip flop (FF) is a logic element on the :term:`FPGA` that stores state.
@@ -117,7 +117,7 @@ Glossary
     For example, in a logic column with 50 tiles, the first tile is configured
     with the first two words in each frame, the next tile with the next two
     words, and so on.
-    
+
   Frame base address
     The first configuration frame address for a :term:`column`. A frame base
     address has always the 7 LSB bits cleared.
@@ -135,7 +135,7 @@ Glossary
     You use a hardware definition language (HDL) to describe the behavior of an
     electronic circuit. Popular HDLs include Verilog (inspired by C) and VHDL
     (inspired by Ada).
-    
+
   Horizontal clock row
   HROW
     Portion of a device including 12 horizontal :term:`clocks <clock>` and the
@@ -171,7 +171,7 @@ Glossary
   Place and route
     Place and route (PnR) is the process of taking logic and placing it into
     hardware logic elements on the :term:`FPGA`, and then routing the signals
-    between the placed elements. 
+    between the placed elements.
 
   Region of interest
   ROI
@@ -222,4 +222,4 @@ Glossary
 
   Word
     32 bits stored in big-endian order. Fundamental unit of :term:`bitstream`
-    format. 
+    format.