diff --git a/docs/dev_database/common/index.rst b/docs/dev_database/common/index.rst index 221c253d..939999e8 100644 --- a/docs/dev_database/common/index.rst +++ b/docs/dev_database/common/index.rst @@ -2,11 +2,11 @@ Common database files ===================== -This section contains a description of :term:`database ` files +This section contains a description of :term:`database ` files that are common for all Xilinx series 7 chip architectures. .. toctree:: - :maxdepth: 2 + :maxdepth: 1 segbits site_type diff --git a/docs/dev_database/common/mask.rst b/docs/dev_database/common/mask.rst index 47743fc5..92a74540 100644 --- a/docs/dev_database/common/mask.rst +++ b/docs/dev_database/common/mask.rst @@ -2,9 +2,9 @@ mask files ========== -The *mask files* are generated for every FPGA :term:`tile ` type. +The *mask files* are generated for every FPGA :term:`tile ` type. They store the information which bits in the bitstream can configure the given -:term:`tile ` type. +:term:`tile ` type. Naming convention ----------------- @@ -14,13 +14,13 @@ The naming scheme for the mask files is the following:: mask_.db Note that auxiliary ``mask_.origin_info.db`` files -provide additional information about the :term:`fuzzer `, -which produced the :term:`database ` file. This file is optional. +provide additional information about the :term:`fuzzer `, +which produced the :term:`database ` file. This file is optional. -Every :term:`tile ` is configured at least by one of three configurational +Every :term:`tile ` is configured at least by one of three configurational buses mentioned in the :doc:`Configuration Section <../../architecture/configuration>`. The default bus is called ``CLB_IO_CLK``. -If the :term:`tile ` can also be configured by another bus, it has an additional ``mask_..db`` +If the :term:`tile ` can also be configured by another bus, it has an additional ``mask_..db`` related to that bus. For example: @@ -33,12 +33,12 @@ File format ----------- The file consists of records that describe the configuration bits for -the particular :term:`tile ` type. Each entry inside the file is of the form:: +the particular :term:`tile ` type. Each entry inside the file is of the form:: bit _ -This means that the :term:`tile ` can be configured by a bit located in the -:term:`frame ` at the address `` + ``, +This means that the :term:`tile ` can be configured by a bit located in the +:term:`frame ` at the address `` + ``, at position `` + ``. Information about ```` and ```` can be taken from part specific ``tilegrid.json`` file. @@ -46,7 +46,7 @@ Example ------- Below there is a part of artix7 ``mask_clbll_l.db`` file describing a FPGA *CLBLL* -:term:`tile `:: +:term:`tile `:: <...> bit 00_61 @@ -57,8 +57,8 @@ Below there is a part of artix7 ``mask_clbll_l.db`` file describing a FPGA *CLBL bit 01_02 <...> -The line ``bit 01_02`` means that the *CLBL_LL* :term:`tile ` can be -configured by the bit located in the :term:`frame ` at the address +The line ``bit 01_02`` means that the *CLBL_LL* :term:`tile ` can be +configured by the bit located in the :term:`frame ` at the address `` + 0x01``, at position `` + 0x2``. The ``tilegrid.json`` is a file specific to a given chip package. @@ -85,14 +85,14 @@ For *xc7a35tcpg236-1* we can find an exemplary *CLBLL_L* entry:: }, The ```` can be found as a argument of the *"baseaddr"* key -and for *CLBLL_L_X2Y0* :term:`tile ` it is equal to ``0x00400100``. The ```` +and for *CLBLL_L_X2Y0* :term:`tile ` it is equal to ``0x00400100``. The ```` on the other hand is an argument of the *"offset"* key. Here it is equal to 0. Finally, we are able to compute the bit location associated with the ``bit 01_02`` entry. The configuration bit for this record can be found in the following -:term:`frame ` address:: +:term:`frame ` address:: 0x00400100 + 0x01 = 0x00400101 @@ -100,5 +100,5 @@ Located at the bit position:: 0x0 + 0x2 = 0x2 -More about the configuration process and the meaning of the :term:`frame ` +More about the configuration process and the meaning of the :term:`frame ` can be found in the :doc:`Configuration Section <../../architecture/configuration>`. diff --git a/docs/dev_database/common/ppips.rst b/docs/dev_database/common/ppips.rst index 4d51d929..567f9fd0 100644 --- a/docs/dev_database/common/ppips.rst +++ b/docs/dev_database/common/ppips.rst @@ -2,13 +2,18 @@ ppips files =========== -The *ppips files* are generated for every FPGA :term:`tile ` type. +The *ppips files* are generated for every FPGA :term:`tile ` type. They store the information about the pseudo-PIPs, inside the tile. -Programable Interconnect Point (:term:`PIP `) is a connection inside the -:term:`tile ` that can be enabled or disabled. Pseudo PIPs appear as standard -:term:`PIPs ` in the Vivado tool, but they do not have actual configuration -bit pattern (they are not configurable). +Programable Interconnect Point (:term:`PIP `) is a connection inside the +:term:`tile ` that can be enabled or disabled. Pseudo PIPs appear as standard +:term:`PIPs ` in the Vivado tool, but they do not have actual configuration +bit pattern in segbits files (they are not configurable). + +The *ppips files* contains the information which `PIPs ` do not have +configuration bits, which allows the tools to not generat error in that situation. +On the other hand this information is used to indicate that the connection +between wires is always on. Naming convention ----------------- diff --git a/docs/dev_database/common/segbits.rst b/docs/dev_database/common/segbits.rst index 8037868c..e8380da0 100644 --- a/docs/dev_database/common/segbits.rst +++ b/docs/dev_database/common/segbits.rst @@ -2,12 +2,16 @@ segbits files ============= -The *segbits files* are generated for every FPGA :term:`tile ` type. +The *segbits files* are generated for every FPGA :term:`tile ` type. They store the information about the combinations of bits in the bitstream -that are responsible for enabling different features inside the :term:`tile `. +that are responsible for enabling different features inside the :term:`tile `. The features can be related to enabling some part of the primitive, setting some initial state of the block, configuring pin pull-up on output pins, etc. +Besides the features provided in this file that can be enabled, +the FPGA chip also has the default configuration. Due to that sometimes there +is no need for affecting the default configuration. + Naming convention ----------------- @@ -16,17 +20,17 @@ The naming scheme for the segbits files is the following:: segbits_.db Note that auxiliary ``segbits_.origin_info.db`` files -provide additional information about the :term:`fuzzer `, which produced the -:term:`database ` file. This file is optional. +provide additional information about the :term:`fuzzer `, which produced the +:term:`database ` file. This file is optional. -Every :term:`tile ` is configured at least by one of three configurational buses +Every :term:`tile ` is configured at least by one of three configurational buses mentioned in the :doc:`Configuration Section <../../architecture/configuration>`. -The default bus is called ``CLB_IO_CLK``. If the :term:`tile ` can also be configured +The default bus is called ``CLB_IO_CLK``. If the :term:`tile ` can also be configured by another bus, it has additional ``segbits_..db`` related to that bus. -Exemplary files: +Example files: - ``segbits_dsp_r.db`` - ``segbits_bram_l.db`` (configured with default ``CLB_IO_CLK`` bus) @@ -59,9 +63,9 @@ Feature naming conventions PIPs ^^^^ -The ```` names for interconnect :term:`PIPs ` are stored in the +The ```` names for interconnect :term:`PIPs ` are stored in the ``segbits_int_l.db`` and ``segbits_int_r.db`` database files. The features that -enable interconnect :term:`PIPs ` have the following syntax:: +enable interconnect :term:`PIPs ` have the following syntax:: ... @@ -84,7 +88,7 @@ Example ------- Below there is a part of the ``segbits_liob33_l.db`` file for the *artix7* -architecture. The file describes the *CLBLL* :term:`tile `:: +architecture. The file describes the *CLBLL* :term:`tile `:: <...> LIOB33.IOB_Y0.IBUFDISABLE.I 38_82 @@ -109,7 +113,7 @@ bit ``!38_92`` and setting bits ``38_94`` and ``39_93``. Generally, the ```` name is linked with its functionality. For example, ``LIOB33.IOB_Y0.PULLTYPE.PULLUP`` means that in the LIOB33 -:term:`tile `, +:term:`tile `, in IOB_Y0 site the *pull type* will be set to *PULLUP*. This simply means that all pins belonging to this particular IOB will be configured with pull-up. diff --git a/docs/dev_database/common/site_type.rst b/docs/dev_database/common/site_type.rst index 103c3120..7604b369 100644 --- a/docs/dev_database/common/site_type.rst +++ b/docs/dev_database/common/site_type.rst @@ -3,13 +3,13 @@ site_type files =============== The *site_type files* are generated for every FPGA -:term:`site ` type. They store the information about the pins and -:term:`PIPs ` of the :term:`site `. +:term:`site ` type. They store the information about the pins and +:term:`PIPs ` of the :term:`site `. Naming convention ----------------- -The naming scheme for the :term:`site ` type files is the following:: +The naming scheme for the :term:`site ` type files is the following:: site_type_.json @@ -22,7 +22,7 @@ Example files: File format ----------- -The :term:`site ` type files are JSON files with the following scheme:: +The :term:`site ` type files are JSON files with the following scheme:: { "site_pins": { @@ -42,15 +42,15 @@ The :term:`site ` type files are JSON files with the following scheme:: where: - - ** - specifies the :term:`site ` pin name - - ** - specifies the :term:`site ` :term:`pip ` name + - ** - specifies the :term:`site ` pin name + - ** - specifies the :term:`site ` :term:`pip ` name - ** - is a direction of a pin (either **IN** or **OUT**) - - ** - specifies the :term:`site ` type + - ** - specifies the :term:`site ` type -The ``"site_pins"`` section describes the input pins of a :term:`site ` -and its directions. The ``"site_pips"`` describes the :term:`PIPs ` -inside the :term:`site ` and which wires they can connect. +The ``"site_pins"`` section describes the input pins of a :term:`site ` +and its directions. The ``"site_pips"`` describes the :term:`PIPs ` +inside the :term:`site ` and which wires they can connect. Example ------- @@ -117,6 +117,6 @@ architecture:: "type": "SLICEL" } -Compare the description with the `Xilinx documentation`_ of that :term:`site `. +Compare the description with the `Xilinx documentation`_ of that :term:`site `. .. _Xilinx documentation: https://www.xilinx.com/support/documentation/user_guides/ug474_7Series_CLB.pdf#page=20 diff --git a/docs/dev_database/common/tile_type.rst b/docs/dev_database/common/tile_type.rst index c609501f..e904a455 100644 --- a/docs/dev_database/common/tile_type.rst +++ b/docs/dev_database/common/tile_type.rst @@ -2,9 +2,9 @@ tile_type files =============== -The *tile_type files* are generated for every FPGA :term:`tile ` -type. They store the information about the :term:`tile ` configuration, -its :term:`PIPs `, :term:`sites `, wires and their properties. +The *tile_type files* are generated for every FPGA :term:`tile ` +type. They store the information about the :term:`tile ` configuration, +its :term:`PIPs `, :term:`sites `, wires and their properties. Naming convention ----------------- @@ -22,7 +22,7 @@ Example files: File format ----------- -The :term:`tile ` type files are JSON files with the following shape:: +The :term:`tile ` type files are JSON files with the following shape:: { "pips": { @@ -30,10 +30,10 @@ The :term:`tile ` type files are JSON files with the following shape:: "can_invert":' "", "dst_to_src": { "delay": [ - "", - "", - "", - "" + "", + "", + "", + "" ], "in_cap": "", "res": "" @@ -44,10 +44,10 @@ The :term:`tile ` type files are JSON files with the following shape:: "is_pseudo": "0", "src_to_dst": { "delay": [ - "", - "", - "", - "" + "", + "", + "", + "" ], "in_cap": "", "res": "" @@ -63,10 +63,10 @@ The :term:`tile ` type files are JSON files with the following shape:: "": { "cap": "", "delay": [ - "", - "", - "", - "" + "", + "", + "", + "" ], "wire": "" }, @@ -85,28 +85,34 @@ The :term:`tile ` type files are JSON files with the following shape:: "pips" section ^^^^^^^^^^^^^^ -The "pips" section describes all :term:`PIPs ` in the :term:`tile `. -Every :term:`PIP ` has its name - ``""`` and may be +The "pips" section describes all :term:`PIPs ` in the :term:`tile `. +Every :term:`PIP ` has its name - ``""`` and may be characterized by the following attributes: - ``can_invert`` - takes a value which can be either **1** or **0**. - It defines whether the :term:`PIP ` has an inverter on it's output or not. + It defines whether the :term:`PIP ` has an inverter on it's output or not. - ``dst_to_src`` - information about the connection in the direction from destination to source. It describes the following properties of the connection: - - ``delay`` - four-element list, which contain information about the delays. - - ``in_cap`` - the input capacitance of the :term:`PIP ` - - ``res`` - the resistance of the :term:`PIP `. + - ``delay`` - a four-element list, which contain information about the delay of pins. + First two elements are related to the *fast corner* of the technological process, + the second two elements to the *slow corner*. The first element of the pair + is the minimum value of the corner, the second describes the maximum value. + They are given in us (nanoseconds). + + - ``in_cap`` - the input capacitance of the :term:`PIP ` in uF (microfarads). + + - ``res`` - the resistance of the :term:`PIP ` in mΩ (miliohms). - ``dst_wire`` - the destination wire name -- ``is_directional`` - contains the information whether :term:`PIP ` is directional. +- ``is_directional`` - contains the information whether :term:`PIP ` is directional. -- ``is_pass_transisstor`` - contains the information whether :term:`PIP ` acts +- ``is_pass_transisstor`` - contains the information whether :term:`PIP ` acts as a pass transistor -- ``is_pseudo`` - contains the information whether :term:`PIP ` is a pseudo-PIP +- ``is_pseudo`` - contains the information whether :term:`PIP ` is a pseudo-PIP - ``src_to_dst`` - contains the information about the connection in the direction from source to destination. It is described by the same set of properties as @@ -115,19 +121,25 @@ characterized by the following attributes: "sites" section: ^^^^^^^^^^^^^^^^ -The "sites" section describes all :term:`sites ` in the :term:`tile `. -Every :term:`site ` may be characterized by the following attributes: +The "sites" section describes all :term:`sites ` in the :term:`tile `. +Every :term:`site ` may be characterized by the following attributes: -- ``name`` - location in the :term:`tile ` grid +- ``name`` - location in the :term:`tile ` grid -- ``prefix`` - the type of the :term:`site ` +- ``prefix`` - the type of the :term:`site ` -- ``site_pins`` - describes the pins that belong to the :term:`site `. +- ``site_pins`` - describes the pins that belong to the :term:`site `. Every pin has it's name - ```` and may be described by the following attributes: - - ``cap`` - pin capacitance - - ``delay`` - pin delay + - ``cap`` - pin capacitance in uF (microfarads). + + - ``delay`` - a four-element list, which contain information about the delay of pins. + First two elements are related to the *fast corner* of the technological process, + the second two elements to the *slow corner*. The first element of the pair + is the minimum value of the corner, the second describes the maximum value. + They are given in us (nanoseconds). + - ``wire`` - wire associated with the pin - ``type`` - indicates the type of the site @@ -139,18 +151,17 @@ Every :term:`site ` may be characterized by the following attributes: "wires" section ^^^^^^^^^^^^^^^ -The "wires" section describes the wires located in the :term:`tile `. +The "wires" section describes the wires located in the :term:`tile `. Every wire has it's name - ```` and may be characterized by the following attributes: -- ``cap`` - wire capacitance -- ``res`` - wire resistance +- ``cap`` - wire capacitance in uF (microfarads) +- ``res`` - wire resistance in mΩ (miliohms). Other ^^^^^ - ``tile_type`` - indicates the type of the tile - Example -------