diff --git a/minitests/carry_cin_cyinit/runme.tcl b/minitests/carry_cin_cyinit/runme.tcl
new file mode 100644
index 00000000..b0c4ed1d
--- /dev/null
+++ b/minitests/carry_cin_cyinit/runme.tcl
@@ -0,0 +1,22 @@
+create_project -force -part $::env(XRAY_PART) design design
+
+read_verilog top.v
+synth_design -top top
+
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports ci]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports cyinit]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports s0]
+set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports o0]
+
+set_property LOC SLICE_X17Y119 [get_cells carry4_inst]
+
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+place_design
+route_design
+
+write_checkpoint -force design.dcp
+write_bitstream -force design.bit
+
diff --git a/minitests/carry_cin_cyinit/top.v b/minitests/carry_cin_cyinit/top.v
new file mode 100644
index 00000000..770d8d0a
--- /dev/null
+++ b/minitests/carry_cin_cyinit/top.v
@@ -0,0 +1,23 @@
+module top (input ci, input cyinit, input s0, output o0);
+	wire [3:0] o, passthru_co, passthru_o;
+
+	CARRY4 carry4_inst (
+		// This will produce the following warning, but will still generate a bitstream.. needs some testing in hardware.
+		// WARNING: [DRC REQP-16] virt5_carry4_input_rule1: CYINIT and CI of carry4_inst cannot be used at the same time.
+		.CI(passthru_co[3]),
+		.CYINIT(cyinit),
+		.DI(4'b0000),
+		.S({3'b000, s0}),
+		.O(o)
+	);
+
+	CARRY4 carry4_passthru (
+		.CI(1'b1),
+		.CYINIT(1'b1),
+		.DI({ci, 3'b000}),
+		.S(4'b0000),
+		.CO(passthru_co)
+	);
+
+	assign o0 = o[0];
+endmodule