From ff4425b91ac06808fafd6069f0ebe755f9287a9b Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Mon, 22 Jul 2019 10:30:12 -0700
Subject: [PATCH] Update 035a using knowledge from #954 tool.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 fuzzers/035a-iob-idelay/bits.dbf    | 14 ++++++++++++++
 fuzzers/035a-iob-idelay/generate.py |  9 ++++++---
 2 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/fuzzers/035a-iob-idelay/bits.dbf b/fuzzers/035a-iob-idelay/bits.dbf
index e69de29b..46f87e1a 100644
--- a/fuzzers/035a-iob-idelay/bits.dbf
+++ b/fuzzers/035a-iob-idelay/bits.dbf
@@ -0,0 +1,14 @@
+34_08 34_14   ,IOI3.IDELAY_Y1.IDELAY_TYPE_FIXED
+35_113 35_119 ,IOI3.IDELAY_Y0.IDELAY_TYPE_FIXED
+34_120 34_122
+34_114 34_116
+34_108 34_110
+34_100 34_102
+34_94 34_96
+35_05 35_07
+35_11 35_13
+35_17 35_19
+35_25 35_27
+35_31 35_33
+34_72 35_69
+34_58 35_55
diff --git a/fuzzers/035a-iob-idelay/generate.py b/fuzzers/035a-iob-idelay/generate.py
index f93950ff..4335c761 100644
--- a/fuzzers/035a-iob-idelay/generate.py
+++ b/fuzzers/035a-iob-idelay/generate.py
@@ -1,7 +1,7 @@
 #!/usr/bin/env python3
 import json
 
-from prjxray.segmaker import Segmaker
+from prjxray.segmaker import Segmaker, add_site_group_zero
 from prjxray import util
 from prjxray import verilog
 
@@ -22,14 +22,16 @@ for params in data:
     value = verilog.unquote(params["IDELAY_TYPE"])
     value = value.replace(
         "_PIPE", "")  # VAR_LOAD and VAR_LOAD_PIPE are the same
-    for x in idelay_types:
-        segmk.add_site_tag(loc, "IDELAY_TYPE_%s" % x, int(value == x))
+    add_site_group_zero(
+        segmk, loc, "IDELAY_TYPE_", idelay_types, "FIXED", value)
 
     # Delay value
     value = int(params["IDELAY_VALUE"])
     for i in range(5):
         segmk.add_site_tag(
             loc, "IDELAY_VALUE[%01d]" % i, ((value >> i) & 1) != 0)
+        segmk.add_site_tag(
+            loc, "ZIDELAY_VALUE[%01d]" % i, ((value >> i) & 1) == 0)
 
     # Delay source
     value = verilog.unquote(params["DELAY_SRC"])
@@ -47,6 +49,7 @@ for params in data:
 
     if "IS_C_INVERTED" in params:
         segmk.add_site_tag(loc, "IS_C_INVERTED", int(params["IS_C_INVERTED"]))
+        segmk.add_site_tag(loc, "ZINV_C", 1 ^ int(params["IS_C_INVERTED"]))
 
     segmk.add_site_tag(
         loc, "IS_DATAIN_INVERTED", int(params["IS_DATAIN_INVERTED"]))