From 328903d2be94b2271d40958233042ae32105c793 Mon Sep 17 00:00:00 2001 From: Keith Rothman <537074+litghost@users.noreply.github.com> Date: Fri, 14 Feb 2020 11:33:28 -0800 Subject: [PATCH] Add workaround for double counting of long wire delay. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> --- utils/create_timing_worksheet_db.py | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/utils/create_timing_worksheet_db.py b/utils/create_timing_worksheet_db.py index ab269b36..3680cc57 100644 --- a/utils/create_timing_worksheet_db.py +++ b/utils/create_timing_worksheet_db.py @@ -125,7 +125,13 @@ class Net(object): def extend_rc_tree(self, ws, current_rc_root, timing_lookup, node): rc_elements = [] - for wire in node['wires']: + + # LV nodes have a workaround applied because of a working in the + # pip timing. + is_lv_node = any( + wire['name'].split('/')[1].startswith('LV') + for wire in node['wires']) + for idx, wire in enumerate(node['wires']): wire_timing = timing_lookup.find_wire(wire['name']) ws['A{}'.format(self.row)] = wire['name'] ws['B{}'.format(self.row)] = 'Part of wire' @@ -134,8 +140,20 @@ class Net(object): cells = {} cells['R'] = 'C{}'.format(self.row) cells['C'] = 'D{}'.format(self.row) - ws[cells['R']] = wire_timing.resistance - ws[cells['C']] = wire_timing.capacitance + if not is_lv_node: + ws[cells['R']] = wire_timing.resistance + ws[cells['C']] = wire_timing.capacitance + else: + # Only use first 2 wire RC's, ignore the rest. It appears + # that some of the RC constant was lumped into the switch + # timing, so don't double count. + if idx < 2: + ws[cells['R']] = wire_timing.resistance + ws[cells['C']] = wire_timing.capacitance + else: + ws[cells['R']] = 0 + ws[cells['C']] = 0 + rc_elements.append( RcElement( resistance=cells['R'],