From 31ef5df168cff83cfb610642e5ce2e3cb7a13ce3 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Thu, 4 Apr 2019 10:09:24 -0700 Subject: [PATCH] docs: Whitespace cleanup. Signed-off-by: Tim 'mithro' Ansell --- docs/architecture/dram_configuration.rst | 2 +- docs/db_dev_process/overview.rst | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/architecture/dram_configuration.rst b/docs/architecture/dram_configuration.rst index 2bdbe2f3..642f1c9d 100644 --- a/docs/architecture/dram_configuration.rst +++ b/docs/architecture/dram_configuration.rst @@ -30,7 +30,7 @@ Each LUT element when operating in RAM mode is a DPRAM64. | Port name | Direction | Width | Description | +============+============+===========+==============+ | WA | IN | 8 | Write address| -+------------+------------+-----------+--------------+ ++------------+------------+-----------+--------------+ | A | IN | 6 | Read address | +------------+------------+-----------+--------------+ | DI | IN | 2 | Data input | diff --git a/docs/db_dev_process/overview.rst b/docs/db_dev_process/overview.rst index 7647e663..2e9e2247 100644 --- a/docs/db_dev_process/overview.rst +++ b/docs/db_dev_process/overview.rst @@ -8,7 +8,7 @@ This is where we describe the logical components in a device to VPR. * VtR stands for `Verilog to Routing `_, * VPR stands for VtR Place and Route. * VtR also has its own synthesis tool called ODIN-II, but we are using `Yosys `_ instead of that. - + Fuzzers ^^^^^^^