From 31ba200080fd92198ae6a646a7062e16e4a5875d Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Fri, 20 Sep 2019 11:20:30 +0200 Subject: [PATCH] Minitest for PLLE2_ADV. Signed-off-by: Maciej Kurc --- minitests/plle2_adv/Makefile | 38 +++++++++ minitests/plle2_adv/README.md | 23 ++++++ minitests/plle2_adv/basys3.xdc | 45 +++++++++++ minitests/plle2_adv/basys3_plle2_adv.v | 50 ++++++++++++ minitests/plle2_adv/src/plle2_test.v | 108 +++++++++++++++++++++++++ minitests/plle2_adv/tcl/par.tcl | 16 ++++ minitests/plle2_adv/tcl/syn.tcl | 11 +++ 7 files changed, 291 insertions(+) create mode 100644 minitests/plle2_adv/Makefile create mode 100644 minitests/plle2_adv/README.md create mode 100644 minitests/plle2_adv/basys3.xdc create mode 100644 minitests/plle2_adv/basys3_plle2_adv.v create mode 100644 minitests/plle2_adv/src/plle2_test.v create mode 100644 minitests/plle2_adv/tcl/par.tcl create mode 100644 minitests/plle2_adv/tcl/syn.tcl diff --git a/minitests/plle2_adv/Makefile b/minitests/plle2_adv/Makefile new file mode 100644 index 00000000..05d7bfbd --- /dev/null +++ b/minitests/plle2_adv/Makefile @@ -0,0 +1,38 @@ +SYNTH ?= vivado +YOSYS = $(XRAY_DIR)/third_party/yosys/yosys +PART = xc7a35tcsg324-1 + +clean: + @find . -name "build-par.*" | xargs rm -rf + @find . -name "build-syn.*" | xargs rm -rf + @rm -f *.edif + @rm -f *.bit + @rm -f *.bin + @rm -f *.log + @rm -f *.dcp + +help: + @echo "Usage: make all [SYNTH=]" + +.PHONY: clean help + +$(YOSYS): + cd $(XRAY_DIR)/third_party/yosys && make config-gcc && make -j$(shell nproc) + +ifeq ($(SYNTH), yosys) +%.edif: %.v $(YOSYS) + $(YOSYS) -p "read_verilog $< ; synth_xilinx -flatten -nosrl; write_edif -pvector bra -attrprop $@" -l $@.log + +else ifeq ($(SYNTH), vivado) +%.edif: %.v tcl/syn.tcl + mkdir -p build-syn.$(basename $@) + cd build-syn.$(basename $@) && env PROJECT_NAME=$(basename $@) $(XRAY_VIVADO) -mode batch -source ../tcl/syn.tcl -nojournal -log ../$@.log + rm -rf *.backup.log + +endif + +%.bit: %.edif tcl/par.tcl + mkdir -p build-par.$(basename $@) + cd build-par.$(basename $@) && env PROJECT_NAME=$(basename $@) $(XRAY_VIVADO) -mode batch -source ../tcl/par.tcl -nojournal -log ../$@.log + rm -rf *.backup.log + diff --git a/minitests/plle2_adv/README.md b/minitests/plle2_adv/README.md new file mode 100644 index 00000000..bf2ac019 --- /dev/null +++ b/minitests/plle2_adv/README.md @@ -0,0 +1,23 @@ +# PLLE2_ADV minitest + +## Description + +This test verifies operation of the `PLLE2_ADV` primitive. The PLL is configured to output clocks using the following dividers: + +- CLKOUT0: 16/16 +- CLKOUT1: 16/32 +- CLKOUT2: 16/48 +- CLKOUT3: 16/64 +- CLKOUT4: 16/80 +- CLKOUT5: 16/96 + +The input clock can be swtched between 100MHz and 50MHz using the `sw[1]` switch. The 50MHz clock is generated using a `BUFR` driven by a `BUFMR`. + +Clocks from the PLL are further divided by 2^21 and then fed to LEDs 0:5. PLL lock indicator is connected to LED 15. The switch `sw[0]` provides reset signal to the PLL. + +## Building + +To build the project run the following command and the bit file will be generated. +``` +make basys3_plle2_adv.bit +``` diff --git a/minitests/plle2_adv/basys3.xdc b/minitests/plle2_adv/basys3.xdc new file mode 100644 index 00000000..ea8281cf --- /dev/null +++ b/minitests/plle2_adv/basys3.xdc @@ -0,0 +1,45 @@ +create_clock -period 10.000 -name clk [get_ports clk] + +set_property PACKAGE_PIN W5 [get_ports clk] + +set_property PACKAGE_PIN B18 [get_ports rx] +set_property PACKAGE_PIN A18 [get_ports tx] + +set_property PACKAGE_PIN V17 [get_ports sw[ 0]] +set_property PACKAGE_PIN V16 [get_ports sw[ 1]] +set_property PACKAGE_PIN W16 [get_ports sw[ 2]] +set_property PACKAGE_PIN W17 [get_ports sw[ 3]] +set_property PACKAGE_PIN W15 [get_ports sw[ 4]] +set_property PACKAGE_PIN V15 [get_ports sw[ 5]] +set_property PACKAGE_PIN W14 [get_ports sw[ 6]] +set_property PACKAGE_PIN W13 [get_ports sw[ 7]] +set_property PACKAGE_PIN V2 [get_ports sw[ 8]] +set_property PACKAGE_PIN T3 [get_ports sw[ 9]] +set_property PACKAGE_PIN T2 [get_ports sw[10]] +set_property PACKAGE_PIN R3 [get_ports sw[11]] +set_property PACKAGE_PIN W2 [get_ports sw[12]] +set_property PACKAGE_PIN U1 [get_ports sw[13]] +set_property PACKAGE_PIN T1 [get_ports sw[14]] +set_property PACKAGE_PIN R2 [get_ports sw[15]] + +set_property PACKAGE_PIN U16 [get_ports led[ 0]] +set_property PACKAGE_PIN E19 [get_ports led[ 1]] +set_property PACKAGE_PIN U19 [get_ports led[ 2]] +set_property PACKAGE_PIN V19 [get_ports led[ 3]] +set_property PACKAGE_PIN W18 [get_ports led[ 4]] +set_property PACKAGE_PIN U15 [get_ports led[ 5]] +set_property PACKAGE_PIN U14 [get_ports led[ 6]] +set_property PACKAGE_PIN V14 [get_ports led[ 7]] +set_property PACKAGE_PIN V13 [get_ports led[ 8]] +set_property PACKAGE_PIN V3 [get_ports led[ 9]] +set_property PACKAGE_PIN W3 [get_ports led[10]] +set_property PACKAGE_PIN U3 [get_ports led[11]] +set_property PACKAGE_PIN P3 [get_ports led[12]] +set_property PACKAGE_PIN N3 [get_ports led[13]] +set_property PACKAGE_PIN P1 [get_ports led[14]] +set_property PACKAGE_PIN L1 [get_ports led[15]] + +foreach port [get_ports] { + set_property IOSTANDARD LVCMOS33 $port + set_property SLEW FAST $port +} diff --git a/minitests/plle2_adv/basys3_plle2_adv.v b/minitests/plle2_adv/basys3_plle2_adv.v new file mode 100644 index 00000000..aace7c85 --- /dev/null +++ b/minitests/plle2_adv/basys3_plle2_adv.v @@ -0,0 +1,50 @@ +`include "src/plle2_test.v" + +`default_nettype none + +// ============================================================================ + +module top +( +input wire clk, + +input wire rx, +output wire tx, + +input wire [15:0] sw, +output wire [15:0] led +); + +// ============================================================================ +// Clock & reset +reg [3:0] rst_sr; + +initial rst_sr <= 4'hF; + +always @(posedge clk) + if (sw[0]) + rst_sr <= 4'hF; + else + rst_sr <= rst_sr >> 1; + +wire CLK = clk; +wire RST = rst_sr[0]; + +// ============================================================================ +// The tester + +plle2_test plle2_test +( +.CLK (CLK), +.RST (RST), + +.I_CLKINSEL (sw[1]), + +.O_LOCKED (led[15]), +.O_CNT (led[5:0]) +); + +assign led [14:6] = 0; + +endmodule + diff --git a/minitests/plle2_adv/src/plle2_test.v b/minitests/plle2_adv/src/plle2_test.v new file mode 100644 index 00000000..2eef55e8 --- /dev/null +++ b/minitests/plle2_adv/src/plle2_test.v @@ -0,0 +1,108 @@ +`default_nettype none + +module plle2_test +( +input wire CLK, +input wire RST, + +input wire I_CLKINSEL, +output wire O_LOCKED, +output wire [5:0] O_CNT +); + +// ============================================================================ +// Input clock divider (to get different clkins) +wire clk100; +wire clk50; + +assign clk100 = CLK; + +wire clkbuf; +BUFMR mr_buf (.I(CLK), .O(clkbuf)); + +BUFR # +( +.BUFR_DIVIDE ("2") +) +bufr +( +.I (clkbuf), +.CLR (RST), +.CE (1'b1), +.O (clk50) +); + +// ============================================================================ +// The PLL +wire clk_fb; + +wire [5:0] clk; + +PLLE2_ADV # +( +.CLKIN1_PERIOD (20.0), // 50MHz +.CLKIN2_PERIOD (10.0), // 100MHz + +.CLKFBOUT_MULT (16), +.CLKFBOUT_PHASE (0.0), + +.CLKOUT0_DIVIDE (16), +.CLKOUT0_DUTY_CYCLE (0.5), +.CLKOUT0_PHASE (0.0), +.CLKOUT1_DIVIDE (32), +.CLKOUT1_DUTY_CYCLE (0.5), +.CLKOUT1_PHASE (0.0), +.CLKOUT2_DIVIDE (48), +.CLKOUT2_DUTY_CYCLE (0.5), +.CLKOUT2_PHASE (0.0), +.CLKOUT3_DIVIDE (64), +.CLKOUT3_DUTY_CYCLE (0.5), +.CLKOUT3_PHASE (0.0), +.CLKOUT4_DIVIDE (80), +.CLKOUT4_DUTY_CYCLE (0.5), +.CLKOUT4_PHASE (0.0), +.CLKOUT5_DIVIDE (96), +.CLKOUT5_DUTY_CYCLE (0.5), +.CLKOUT5_PHASE (0.0), + +.STARTUP_WAIT ("FALSE") +) +pll +( +.CLKIN1 (clk50), +.CLKIN2 (clk100), +.CLKINSEL (I_CLKINSEL), + +.RST (RST), +.LOCKED (O_LOCKED), + +.CLKFBIN (clk_fb), +.CLKFBOUT (clk_fb), + +.CLKOUT0 (clk[0]), +.CLKOUT1 (clk[1]), +.CLKOUT2 (clk[2]), +.CLKOUT3 (clk[3]), +.CLKOUT4 (clk[4]), +.CLKOUT5 (clk[5]) +); + +// ============================================================================ +// Counters + +wire rst = RST || !O_LOCKED; + +genvar i; +generate for (i=0; i<6; i=i+1) begin + + reg [23:0] counter; + + always @(posedge clk[i] or posedge rst) + if (rst) counter <= 0; + else counter <= counter + 1; + + assign O_CNT[i] = counter[21]; + +end endgenerate + +endmodule diff --git a/minitests/plle2_adv/tcl/par.tcl b/minitests/plle2_adv/tcl/par.tcl new file mode 100644 index 00000000..60d66e80 --- /dev/null +++ b/minitests/plle2_adv/tcl/par.tcl @@ -0,0 +1,16 @@ +create_project -force -name $env(PROJECT_NAME) -part xc7a35tcpg236-1 + +read_edif ../$env(PROJECT_NAME).edif + +link_design -part xc7a35tcpg236-1 +source ../basys3.xdc + +set_property SEVERITY {Warning} [get_drc_checks UCIO-1] +set_property SEVERITY {Warning} [get_drc_checks NSTD-1] + +place_design +route_design + +write_checkpoint -force ../$env(PROJECT_NAME).dcp + +write_bitstream -force ../$env(PROJECT_NAME).bit diff --git a/minitests/plle2_adv/tcl/syn.tcl b/minitests/plle2_adv/tcl/syn.tcl new file mode 100644 index 00000000..c4501ce6 --- /dev/null +++ b/minitests/plle2_adv/tcl/syn.tcl @@ -0,0 +1,11 @@ +create_project -force -name $env(PROJECT_NAME) -part xc7a35tcpg236-1 + +read_verilog ../$env(PROJECT_NAME).v + +synth_design -top top + +report_timing_summary -file top_timing_synth.rpt +report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt +report_utilization -file top_utilization_synth.rpt + +write_edif -force ../$env(PROJECT_NAME).edif