diff --git a/fuzzers/001-part-yaml/Makefile b/fuzzers/001-part-yaml/Makefile
index d66ec913..3e049293 100644
--- a/fuzzers/001-part-yaml/Makefile
+++ b/fuzzers/001-part-yaml/Makefile
@@ -1,17 +1,23 @@
 N := 1
 SPECIMENS := $(addprefix specimen_,$(shell seq -f '%03.0f' $(N)))
 
-.PHONY: database pushdb clean $(SPECIMENS)
+database: $(SPECIMENS)
+	cp specimen_001/part.yaml ${XRAY_PART}.yaml
 
 $(SPECIMENS): Makefile.specimen
 	mkdir -p $@
 	$(MAKE) -C $@ -f ../Makefile.specimen
 
-database: $(SPECIMENS)
-	cp specimen_001/part.yaml ${XRAY_PART}.yaml
-
 pushdb:
 	cp ${XRAY_PART}.yaml ${XRAY_DATABASE_DIR}/$(XRAY_DATABASE)
 
+run:
+	$(MAKE) clean
+	$(MAKE) database
+	$(MAKE) pushdb
+	touch run.ok
+
 clean:
-	rm -rf specimen_[0-9][0-9][0-9]/ *.yaml
+	rm -rf specimen_[0-9][0-9][0-9]/ *.yaml run.ok
+
+.PHONY: database pushdb clean run $(SPECIMENS)
diff --git a/fuzzers/005-tilegrid/Makefile b/fuzzers/005-tilegrid/Makefile
index df8671b9..c59f83bf 100644
--- a/fuzzers/005-tilegrid/Makefile
+++ b/fuzzers/005-tilegrid/Makefile
@@ -13,8 +13,14 @@ $(SPECIMENS_OK):
 	bash generate.sh $(subst /OK,,$@)
 	touch $@
 
+run:
+	$(MAKE) clean
+	$(MAKE) database
+	$(MAKE) pushdb
+	touch run.ok
+
 clean:
-	rm -rf specimen_[0-9][0-9][0-9]/ tilegrid.json
+	rm -rf specimen_[0-9][0-9][0-9]/ tilegrid.json run.ok
 
-.PHONY: database pushdb clean
+.PHONY: database pushdb clean run
 
diff --git a/fuzzers/005-tilegrid/generate.sh b/fuzzers/005-tilegrid/generate.sh
old mode 100755
new mode 100644
diff --git a/fuzzers/010-lutinit/Makefile b/fuzzers/010-lutinit/Makefile
index dafe5067..7ef252ff 100644
--- a/fuzzers/010-lutinit/Makefile
+++ b/fuzzers/010-lutinit/Makefile
@@ -17,8 +17,14 @@ $(SPECIMENS_OK):
 	bash generate.sh $(subst /OK,,$@)
 	touch $@
 
+run:
+	$(MAKE) clean
+	$(MAKE) database
+	$(MAKE) pushdb
+	touch run.ok
+
 clean:
-	rm -rf specimen_[0-9][0-9][0-9]/ seg_clbll.segbits seg_clblm.segbits
+	rm -rf specimen_[0-9][0-9][0-9]/ seg_clbll.segbits seg_clblm.segbits run.ok
 
-.PHONY: database pushdb clean
+.PHONY: database pushdb run clean
 
diff --git a/fuzzers/011-ffconfig/Makefile b/fuzzers/011-ffconfig/Makefile
index cdd3cf23..cf669fbf 100644
--- a/fuzzers/011-ffconfig/Makefile
+++ b/fuzzers/011-ffconfig/Makefile
@@ -15,8 +15,15 @@ $(SPECIMENS_OK):
 	bash generate.sh $(subst /OK,,$@)
 	touch $@
 
+run:
+	$(MAKE) clean
+	$(MAKE) database
+	$(MAKE) pushdb
+	touch run.ok
+
 clean:
-	rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v
+	rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits __pycache__ run.ok
+	rm -rf vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v
 
-.PHONY: database pushdb clean
+.PHONY: database pushdb run clean
 
diff --git a/fuzzers/012-clbn5ffmux/Makefile b/fuzzers/012-clbn5ffmux/Makefile
index cdd3cf23..1a7faa6e 100644
--- a/fuzzers/012-clbn5ffmux/Makefile
+++ b/fuzzers/012-clbn5ffmux/Makefile
@@ -15,8 +15,14 @@ $(SPECIMENS_OK):
 	bash generate.sh $(subst /OK,,$@)
 	touch $@
 
+run:
+	$(MAKE) clean
+	$(MAKE) database
+	$(MAKE) pushdb
+	touch run.ok
+
 clean:
-	rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v
+	rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v run.ok
 
-.PHONY: database pushdb clean
+.PHONY: database pushdb run clean
 
diff --git a/fuzzers/013-clbncy0/Makefile b/fuzzers/013-clbncy0/Makefile
index cdd3cf23..1a7faa6e 100644
--- a/fuzzers/013-clbncy0/Makefile
+++ b/fuzzers/013-clbncy0/Makefile
@@ -15,8 +15,14 @@ $(SPECIMENS_OK):
 	bash generate.sh $(subst /OK,,$@)
 	touch $@
 
+run:
+	$(MAKE) clean
+	$(MAKE) database
+	$(MAKE) pushdb
+	touch run.ok
+
 clean:
-	rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v
+	rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v run.ok
 
-.PHONY: database pushdb clean
+.PHONY: database pushdb run clean
 
diff --git a/fuzzers/014-ffsrcemux/Makefile b/fuzzers/014-ffsrcemux/Makefile
index cdd3cf23..1a7faa6e 100644
--- a/fuzzers/014-ffsrcemux/Makefile
+++ b/fuzzers/014-ffsrcemux/Makefile
@@ -15,8 +15,14 @@ $(SPECIMENS_OK):
 	bash generate.sh $(subst /OK,,$@)
 	touch $@
 
+run:
+	$(MAKE) clean
+	$(MAKE) database
+	$(MAKE) pushdb
+	touch run.ok
+
 clean:
-	rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v
+	rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v run.ok
 
-.PHONY: database pushdb clean
+.PHONY: database pushdb run clean
 
diff --git a/fuzzers/015-clbnffmux/Makefile b/fuzzers/015-clbnffmux/Makefile
index 8e623c60..f8fedf89 100644
--- a/fuzzers/015-clbnffmux/Makefile
+++ b/fuzzers/015-clbnffmux/Makefile
@@ -16,8 +16,14 @@ $(SPECIMENS_OK):
 	bash generate.sh $(subst /OK,,$@)
 	touch $@
 
+run:
+	$(MAKE) clean
+	$(MAKE) database
+	$(MAKE) pushdb
+	touch run.ok
+
 clean:
-	rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v
+	rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v run.ok
 
-.PHONY: database pushdb clean
+.PHONY: database pushdb run clean
 
diff --git a/fuzzers/016-clbnoutmux/Makefile b/fuzzers/016-clbnoutmux/Makefile
index 6c52b6b5..b4d9daa1 100644
--- a/fuzzers/016-clbnoutmux/Makefile
+++ b/fuzzers/016-clbnoutmux/Makefile
@@ -16,8 +16,14 @@ $(SPECIMENS_OK):
 	bash generate.sh $(subst /OK,,$@)
 	touch $@
 
+run:
+	$(MAKE) clean
+	$(MAKE) database
+	$(MAKE) pushdb
+	touch run.ok
+
 clean:
-	rm -rf specimen_[0-9][0-9][0-9]/ *.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v
+	rm -rf specimen_[0-9][0-9][0-9]/ *.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v run.ok
 
-.PHONY: database pushdb clean
+.PHONY: database pushdb run clean
 
diff --git a/fuzzers/017-clbprecyinit/Makefile b/fuzzers/017-clbprecyinit/Makefile
index 8e623c60..f8fedf89 100644
--- a/fuzzers/017-clbprecyinit/Makefile
+++ b/fuzzers/017-clbprecyinit/Makefile
@@ -16,8 +16,14 @@ $(SPECIMENS_OK):
 	bash generate.sh $(subst /OK,,$@)
 	touch $@
 
+run:
+	$(MAKE) clean
+	$(MAKE) database
+	$(MAKE) pushdb
+	touch run.ok
+
 clean:
-	rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v
+	rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v run.ok
 
-.PHONY: database pushdb clean
+.PHONY: database pushdb run clean
 
diff --git a/fuzzers/018-clbram/Makefile b/fuzzers/018-clbram/Makefile
index cdd3cf23..1a7faa6e 100644
--- a/fuzzers/018-clbram/Makefile
+++ b/fuzzers/018-clbram/Makefile
@@ -15,8 +15,14 @@ $(SPECIMENS_OK):
 	bash generate.sh $(subst /OK,,$@)
 	touch $@
 
+run:
+	$(MAKE) clean
+	$(MAKE) database
+	$(MAKE) pushdb
+	touch run.ok
+
 clean:
-	rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v
+	rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v run.ok
 
-.PHONY: database pushdb clean
+.PHONY: database pushdb run clean
 
diff --git a/fuzzers/019-ndi1mux/Makefile b/fuzzers/019-ndi1mux/Makefile
index cdd3cf23..1a7faa6e 100644
--- a/fuzzers/019-ndi1mux/Makefile
+++ b/fuzzers/019-ndi1mux/Makefile
@@ -15,8 +15,14 @@ $(SPECIMENS_OK):
 	bash generate.sh $(subst /OK,,$@)
 	touch $@
 
+run:
+	$(MAKE) clean
+	$(MAKE) database
+	$(MAKE) pushdb
+	touch run.ok
+
 clean:
-	rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v
+	rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit top.v run.ok
 
-.PHONY: database pushdb clean
+.PHONY: database pushdb run clean
 
diff --git a/fuzzers/050-intpips/Makefile b/fuzzers/050-intpips/Makefile
index eccb2cd3..6e3b0f05 100644
--- a/fuzzers/050-intpips/Makefile
+++ b/fuzzers/050-intpips/Makefile
@@ -25,10 +25,13 @@ $(SPECIMENS_OK):
 	touch $@
 
 run:
-	+set -ex; make clean; make; make pushdb
+	$(MAKE) clean
+	$(MAKE) database
+	$(MAKE) pushdb
+	touch run.ok
 
 clean:
-	rm -rf specimen_[0-9][0-9][0-9]/ seg_int_[lr].segbits mask_clbl[lm]_[lr].segbits
+	rm -rf specimen_[0-9][0-9][0-9]/ seg_int_[lr].segbits mask_clbl[lm]_[lr].segbits run.ok
 
 .PHONY: database pushdb run clean
 
diff --git a/fuzzers/051-imuxlout/Makefile b/fuzzers/051-imuxlout/Makefile
index e9a4c82f..da59695b 100644
--- a/fuzzers/051-imuxlout/Makefile
+++ b/fuzzers/051-imuxlout/Makefile
@@ -21,10 +21,11 @@ todo.txt:
 	python3 maketodo.py > todo.txt
 
 run:
-	+set -ex; while make clean; make todo.txt; test -s todo.txt; do make; make pushdb; done; true
+	+set -ex; while make clean; make todo.txt; test -s todo.txt; do make database; make pushdb; done; true
+	touch run.ok
 
 clean:
-	rm -rf .Xil/ .cache/ filtered_seg_int_[lr].segbits
+	rm -rf .Xil/ .cache/ filtered_seg_int_[lr].segbits run.ok
 	rm -rf todo.txt vivado* piplist/ piplist.dcp pattern_[lr].txt pips_int_[lr].txt
 	rm -rf specimen_[0-9][0-9][0-9]/ seg_int_[lr].segbits mask_clbl[lm]_[lr].segbits
 
diff --git a/fuzzers/052-clkin/Makefile b/fuzzers/052-clkin/Makefile
index d8f82463..5d71a14a 100644
--- a/fuzzers/052-clkin/Makefile
+++ b/fuzzers/052-clkin/Makefile
@@ -21,10 +21,11 @@ todo.txt:
 	python3 maketodo.py | sort -R | head -n10 > todo.txt
 
 run:
-	+set -ex; while make clean; make todo.txt; test -s todo.txt; do make; make pushdb; done; true
+	+set -ex; while make clean; make todo.txt; test -s todo.txt; do make database; make pushdb; done; true
+	touch run.ok
 
 clean:
-	rm -rf .Xil/ .cache/ filtered_seg_int_[lr].segbits
+	rm -rf .Xil/ .cache/ filtered_seg_int_[lr].segbits run.ok
 	rm -rf todo.txt vivado* piplist/ piplist.dcp pattern_[lr].txt pips_int_[lr].txt
 	rm -rf specimen_[0-9][0-9][0-9]/ seg_int_[lr].segbits mask_clbl[lm]_[lr].segbits
 
diff --git a/fuzzers/053-ctrlin/Makefile b/fuzzers/053-ctrlin/Makefile
index d8f82463..5d71a14a 100644
--- a/fuzzers/053-ctrlin/Makefile
+++ b/fuzzers/053-ctrlin/Makefile
@@ -21,10 +21,11 @@ todo.txt:
 	python3 maketodo.py | sort -R | head -n10 > todo.txt
 
 run:
-	+set -ex; while make clean; make todo.txt; test -s todo.txt; do make; make pushdb; done; true
+	+set -ex; while make clean; make todo.txt; test -s todo.txt; do make database; make pushdb; done; true
+	touch run.ok
 
 clean:
-	rm -rf .Xil/ .cache/ filtered_seg_int_[lr].segbits
+	rm -rf .Xil/ .cache/ filtered_seg_int_[lr].segbits run.ok
 	rm -rf todo.txt vivado* piplist/ piplist.dcp pattern_[lr].txt pips_int_[lr].txt
 	rm -rf specimen_[0-9][0-9][0-9]/ seg_int_[lr].segbits mask_clbl[lm]_[lr].segbits
 
diff --git a/fuzzers/054-gfan/Makefile b/fuzzers/054-gfan/Makefile
index d8f82463..5d71a14a 100644
--- a/fuzzers/054-gfan/Makefile
+++ b/fuzzers/054-gfan/Makefile
@@ -21,10 +21,11 @@ todo.txt:
 	python3 maketodo.py | sort -R | head -n10 > todo.txt
 
 run:
-	+set -ex; while make clean; make todo.txt; test -s todo.txt; do make; make pushdb; done; true
+	+set -ex; while make clean; make todo.txt; test -s todo.txt; do make database; make pushdb; done; true
+	touch run.ok
 
 clean:
-	rm -rf .Xil/ .cache/ filtered_seg_int_[lr].segbits
+	rm -rf .Xil/ .cache/ filtered_seg_int_[lr].segbits run.ok
 	rm -rf todo.txt vivado* piplist/ piplist.dcp pattern_[lr].txt pips_int_[lr].txt
 	rm -rf specimen_[0-9][0-9][0-9]/ seg_int_[lr].segbits mask_clbl[lm]_[lr].segbits
 
diff --git a/fuzzers/055-gnd/Makefile b/fuzzers/055-gnd/Makefile
index 7ff0abff..069063e0 100644
--- a/fuzzers/055-gnd/Makefile
+++ b/fuzzers/055-gnd/Makefile
@@ -23,10 +23,13 @@ todo.txt:
 	echo "INT_R.GFAN1.GND_WIRE" >> todo.txt
 
 run:
-	+set -ex; make clean; make; make pushdb
+	$(MAKE) clean
+	$(MAKE) database
+	$(MAKE) pushdb
+	touch run.ok
 
 clean:
-	rm -rf .Xil/ .cache/ filtered_seg_int_[lr].segbits
+	rm -rf .Xil/ .cache/ filtered_seg_int_[lr].segbits run.ok
 	rm -rf todo.txt vivado* piplist/ piplist.dcp pattern_[lr].txt pips_int_[lr].txt
 	rm -rf specimen_[0-9][0-9][0-9]/ seg_int_[lr].segbits mask_clbl[lm]_[lr].segbits
 
diff --git a/fuzzers/056-rempips/Makefile b/fuzzers/056-rempips/Makefile
index 339a1cff..9c96fe66 100644
--- a/fuzzers/056-rempips/Makefile
+++ b/fuzzers/056-rempips/Makefile
@@ -21,10 +21,11 @@ todo.txt:
 	python3 maketodo.py | sort -R | head -n10 > todo.txt
 
 run:
-	+set -ex; while make clean; make todo.txt; test -s todo.txt; do if make; then make pushdb; fi; done; true
+	+set -ex; while make clean; make todo.txt; test -s todo.txt; do if make database; then make pushdb; fi; done; true
+	touch run.ok
 
 clean:
-	rm -rf .Xil/ .cache/ filtered_seg_int_[lr].segbits
+	rm -rf .Xil/ .cache/ filtered_seg_int_[lr].segbits run.ok
 	rm -rf todo.txt vivado* piplist/ piplist.dcp pattern_[lr].txt pips_int_[lr].txt
 	rm -rf specimen_[0-9][0-9][0-9]/ seg_int_[lr].segbits
 
diff --git a/fuzzers/057-bipips/Makefile b/fuzzers/057-bipips/Makefile
index 4cf12810..4ade5699 100644
--- a/fuzzers/057-bipips/Makefile
+++ b/fuzzers/057-bipips/Makefile
@@ -21,10 +21,11 @@ todo.txt:
 	python3 maketodo.py | sort -R | head -n5 > todo.txt
 
 run:
-	+set -ex; while make clean; make todo.txt; test -s todo.txt; do make; make pushdb; done; true
+	+set -ex; while make clean; make todo.txt; test -s todo.txt; do make database; make pushdb; done; true
+	touch run.ok
 
 clean:
-	rm -rf .Xil/ .cache/ vivado* todo.txt
+	rm -rf .Xil/ .cache/ vivado* todo.txt run.ok
 	rm -rf bipiplist/ bipiplist.dcp bipips_int_[lr].txt
 	rm -rf specimen_[0-9][0-9][0-9]/ seg_int_[lr].segbits
 
diff --git a/fuzzers/058-hclkpips/Makefile b/fuzzers/058-hclkpips/Makefile
index 477b9a06..df6a8fd4 100644
--- a/fuzzers/058-hclkpips/Makefile
+++ b/fuzzers/058-hclkpips/Makefile
@@ -25,10 +25,12 @@ $(SPECIMENS_OK):
 	touch $@
 
 run:
-	+set -ex; make clean; make; make pushdb
+	$(MAKE) clean
+	$(MAKE) database
+	$(MAKE) pushdb
 
 clean:
-	rm -rf specimen_[0-9][0-9][0-9]/ seg_hclk_[lr].segbits mask_hclk_[lr].segbits ppips_hclk_[lr].txt
+	rm -rf specimen_[0-9][0-9][0-9]/ seg_hclk_[lr].segbits mask_hclk_[lr].segbits ppips_hclk_[lr].txt run.ok
 
 .PHONY: database pushdb run clean
 
diff --git a/fuzzers/070-tileconn/Makefile b/fuzzers/070-tileconn/Makefile
index 40eec548..73b0a649 100644
--- a/fuzzers/070-tileconn/Makefile
+++ b/fuzzers/070-tileconn/Makefile
@@ -14,10 +14,13 @@ $(SPECIMENS_OK):
 	touch $@
 
 run:
-	+set -ex; make clean; make; make pushdb
+	$(MAKE) clean
+	$(MAKE) database
+	$(MAKE) pushdb
+	touch run.ok
 
 clean:
-	rm -rf specimen_[0-9][0-9][0-9]/ tileconn.json
+	rm -rf specimen_[0-9][0-9][0-9]/ tileconn.json run.ok
 
 .PHONY: database pushdb run clean
 
diff --git a/fuzzers/070-tileconn/generate.py b/fuzzers/070-tileconn/generate.py
index 29787eee..2fda59e7 100644
--- a/fuzzers/070-tileconn/generate.py
+++ b/fuzzers/070-tileconn/generate.py
@@ -24,6 +24,22 @@ with open("nodewires.txt") as f:
                 tilenodes[wire_tile] = dict()
             tilenodes[wire_tile][node] = wire_name
 
+def filter_pair(type1, type2, wire1, wire2, delta_x, delta_y):
+    if type1 in ["HCLK_L", "HCLK_R"]:
+        is_vertical_wire = False
+        if wire1.startswith("HCLK_S"): is_vertical_wire = True
+        if wire1.startswith("HCLK_N"): is_vertical_wire = True
+        if wire1.startswith("HCLK_W"): is_vertical_wire = True
+        if wire1.startswith("HCLK_E"): is_vertical_wire = True
+        if wire1.startswith("HCLK_LV"): is_vertical_wire = True
+        if wire1.startswith("HCLK_BYP"): is_vertical_wire = True
+        if wire1.startswith("HCLK_FAN"): is_vertical_wire = True
+        if wire1.startswith("HCLK_LEAF_CLK_"): is_vertical_wire = True
+        if is_vertical_wire and delta_y == 0: return True
+        if not is_vertical_wire and delta_x == 0: return True
+
+    return False
+
 def handle_pair(tile1, tile2):
     if tile1 not in tilenodes: return
     if tile2 not in tilenodes: return
@@ -44,6 +60,10 @@ def handle_pair(tile1, tile2):
     for node, wire1 in tilenodes[tile1].items():
         if node in tilenodes[tile2]:
             wire2 = tilenodes[tile2][node]
+            if filter_pair(key[0], key[1], wire1, wire2, key[2], key[3]):
+                continue
+            if filter_pair(key[1], key[0], wire2, wire1, -key[2], -key[3]):
+                continue
             wire_pairs.add((wire1, wire2))
 
     if key not in database:
diff --git a/fuzzers/070-tileconn/generate.sh b/fuzzers/070-tileconn/generate.sh
old mode 100755
new mode 100644
diff --git a/fuzzers/071-ppips/Makefile b/fuzzers/071-ppips/Makefile
index a0064299..d6583293 100644
--- a/fuzzers/071-ppips/Makefile
+++ b/fuzzers/071-ppips/Makefile
@@ -24,10 +24,13 @@ $(SPECIMENS_OK):
 	touch $@
 
 run:
-	+set -ex; make clean; make; make pushdb
+	$(MAKE) clean
+	$(MAKE) database
+	$(MAKE) pushdb
+	touch run.ok
 
 clean:
-	rm -rf specimen_[0-9][0-9][0-9]/ ppips_clbl[ml]_[lr].txt ppips_int_[lr].txt
+	rm -rf specimen_[0-9][0-9][0-9]/ ppips_clbl[ml]_[lr].txt ppips_int_[lr].txt run.ok
 
 .PHONY: database pushdb run clean
 
diff --git a/fuzzers/071-ppips/generate.sh b/fuzzers/071-ppips/generate.sh
old mode 100755
new mode 100644
diff --git a/fuzzers/Makefile b/fuzzers/Makefile
new file mode 100644
index 00000000..48e0ad0a
--- /dev/null
+++ b/fuzzers/Makefile
@@ -0,0 +1,31 @@
+define fuzzer
+all:: $(1)/run.ok
+clean::
+	$(MAKE) -C $(1) clean
+$(1)/run.ok: $(addsuffix /run.ok,$(2))
+	$(MAKE) -C $(1) run
+endef
+
+$(eval $(call fuzzer,001-part-yaml,))
+$(eval $(call fuzzer,005-tilegrid,))
+$(eval $(call fuzzer,010-lutinit,005-tilegrid))
+$(eval $(call fuzzer,011-ffconfig,005-tilegrid))
+$(eval $(call fuzzer,012-clbn5ffmux,005-tilegrid))
+$(eval $(call fuzzer,013-clbncy0,005-tilegrid))
+$(eval $(call fuzzer,014-ffsrcemux,005-tilegrid))
+$(eval $(call fuzzer,015-clbnffmux,005-tilegrid))
+$(eval $(call fuzzer,016-clbnoutmux,005-tilegrid))
+$(eval $(call fuzzer,017-clbprecyinit,005-tilegrid))
+$(eval $(call fuzzer,018-clbram,005-tilegrid))
+$(eval $(call fuzzer,019-ndi1mux,005-tilegrid))
+$(eval $(call fuzzer,050-intpips,005-tilegrid))
+$(eval $(call fuzzer,051-imuxlout,050-intpips))
+$(eval $(call fuzzer,052-clkin,050-intpips))
+$(eval $(call fuzzer,053-ctrlin,050-intpips))
+$(eval $(call fuzzer,054-gfan,050-intpips))
+$(eval $(call fuzzer,055-gnd,050-intpips))
+$(eval $(call fuzzer,056-rempips,051-imuxlout 052-clkin 053-ctrlin 054-gfan 055-gnd))
+$(eval $(call fuzzer,057-bipips,056-rempips))
+$(eval $(call fuzzer,058-hclkpips,056-rempips))
+$(eval $(call fuzzer,070-tileconn,005-tilegrid))
+$(eval $(call fuzzer,071-ppips,057-bipips 058-hclkpips))
diff --git a/minitests/roi_harness/.gitignore b/minitests/roi_harness/.gitignore
new file mode 100644
index 00000000..82a01aa0
--- /dev/null
+++ b/minitests/roi_harness/.gitignore
@@ -0,0 +1,8 @@
+/.Xil
+/design/
+/design.bit
+/design.bits
+/design.dcp
+/usage_statistics_webtalk.*
+/vivado*
+/design.txt
diff --git a/minitests/roi_harness/Makefile b/minitests/roi_harness/Makefile
new file mode 100644
index 00000000..e9e022b0
--- /dev/null
+++ b/minitests/roi_harness/Makefile
@@ -0,0 +1,8 @@
+all:
+	bash runme.sh
+
+clean:
+	rm -rf specimen_[0-9][0-9][0-9]/ seg_clblx.segbits vivado*.log vivado_*.str vivado*.jou design *.bits *.dcp *.bit design.txt .Xil
+
+.PHONY: all clean
+
diff --git a/minitests/roi_harness/README.txt b/minitests/roi_harness/README.txt
new file mode 100644
index 00000000..c8fe8978
--- /dev/null
+++ b/minitests/roi_harness/README.txt
@@ -0,0 +1,12 @@
+Creates an ROI with clk, inputs, and outputs to use as a partial reconfiguration test harness 
+
+Basic idea:
+-LOC LUTs in the ROI to terminate input and output routing
+-Let Vivado LOC the rest of the logic
+-Manually route signals in and out of the ROI enough to avoid routing loops into the ROI
+-Let Vivado finish the rest of the routes
+
+There is no logic outside of the ROI in order to keep IOB to ROI delays short
+Its expected the end user will rip out everything inside the ROI
+
+To target Arty A7 you should source the artix DB environment script then source arty.sh
diff --git a/minitests/roi_harness/arty.sh b/minitests/roi_harness/arty.sh
new file mode 100644
index 00000000..2b9b208c
--- /dev/null
+++ b/minitests/roi_harness/arty.sh
@@ -0,0 +1 @@
+export XRAY_PART=xc7a35tcsg324-1
diff --git a/minitests/roi_harness/runme.sh b/minitests/roi_harness/runme.sh
new file mode 100644
index 00000000..149ec619
--- /dev/null
+++ b/minitests/roi_harness/runme.sh
@@ -0,0 +1,6 @@
+#!/bin/bash
+
+set -ex
+vivado -mode batch -source runme.tcl
+test -z "$(fgrep CRITICAL vivado.log)"
+
diff --git a/minitests/roi_harness/runme.tcl b/minitests/roi_harness/runme.tcl
new file mode 100644
index 00000000..5b95f719
--- /dev/null
+++ b/minitests/roi_harness/runme.tcl
@@ -0,0 +1,273 @@
+# WARNING: this is somewhat paramaterized, but is only tested on A50T/A35T with the traditional ROI
+# Your ROI should at least have a SLICEL on the left
+
+set DIN_N 8
+set DOUT_N 8
+# X12 in the ROI, X10 just to the left
+# Start at bottom left of ROI and work up
+# (IOs are to left)
+# SLICE_X12Y100:SLICE_X27Y149
+# set X_BASE 12
+set X_BASE [lindex [split [lindex [split "$::env(XRAY_ROI)" Y] 0] X] 1]
+set Y_BASE [lindex [split [lindex [split "$::env(XRAY_ROI)" Y] 1] :] 0]
+# set Y_DIN_BASE 100
+set Y_CLK_BASE $Y_BASE 
+# Clock lut in middle
+set Y_DIN_BASE [expr "$Y_CLK_BASE + 1"]
+set Y_DOUT_BASE [expr "$Y_DIN_BASE + $DIN_N"]
+
+puts "Environment"
+puts "  XRAY_ROI: $::env(XRAY_ROI)"
+puts "  X_BASE: $X_BASE"
+puts "  Y_DIN_BASE: $Y_DIN_BASE"
+puts "  Y_CLK_BASE: $Y_CLK_BASE"
+puts "  Y_DOUT_BASE: $Y_DOUT_BASE"
+
+source ../../utils/utils.tcl
+
+create_project -force -part $::env(XRAY_PART) design design
+read_verilog top.v
+# added flatten_hierarchy
+# dout_shr was getting folded into the pblock
+# synth_design -top top -flatten_hierarchy none -no_lc -keep_equivalent_registers -resource_sharing off
+synth_design -top top -flatten_hierarchy none -verilog_define DIN_N=$DIN_N -verilog_define DOUT_N=$DOUT_N
+
+# TODO: find a way to more automatically assign these?
+# Sequential I/O Bank 16 layout
+set part "$::env(XRAY_PART)"
+if {$part eq "xc7a50tfgg484-1"} {
+    # Partial list, expand as needed
+    set bank_16 "F21 G22 G21 D21 E21 D22 E22 A21 B21 B22 C22 C20 D20 F20 F19 A19 A18"
+    set banki 0
+
+    # CLK
+    set pin [lindex $bank_16 $banki]
+    incr banki
+    set_property -dict "PACKAGE_PIN $pin IOSTANDARD LVCMOS33" [get_ports "clk"]
+
+    # DIN
+    for {set j 0} {$j < $DIN_N} {incr j} {
+        set pin [lindex $bank_16 $banki]
+        incr banki
+        set_property -dict "PACKAGE_PIN $pin IOSTANDARD LVCMOS33" [get_ports "din[$j]"]
+    }
+
+    # DOUT
+    for {set j 0} {$j < $DOUT_N} {incr j} {
+        set pin [lindex $bank_16 $banki]
+        incr banki
+        set_property -dict "PACKAGE_PIN $pin IOSTANDARD LVCMOS33" [get_ports "dout[$j]"]
+   }
+# Arty A7 optimized I/O layout
+} elseif {$part eq "xc7a35tcsg324-1"} {
+    # https://reference.digilentinc.com/reference/programmable-logic/arty/reference-manual?redirect=1
+    set pmod_ja "G13 B11 A11 D12  D13 B18 A18 K16"
+    set pmod_jb "E15 E16 D15 C15  J17 J18 K15 J15"
+    set pmod_jc "U12 V12 V10 V11  U14 V14 T13 U13"
+
+    # CLK on Pmod JA
+    set pin [lindex $pmod_ja 0]
+    set_property -dict "PACKAGE_PIN G13 IOSTANDARD LVCMOS33" [get_ports "clk"]
+
+    # DIN on Pmod JB
+    for {set i 0} {$i < $DIN_N} {incr i} {
+        set pin [lindex $pmod_jb $i]
+        set_property -dict "PACKAGE_PIN $pin IOSTANDARD LVCMOS33" [get_ports "din[$i]"]
+    }
+
+    # DOUT on Pmod JC
+    for {set i 0} {$i < $DOUT_N} {incr i} {
+        set pin [lindex $pmod_jc $i]
+        set_property -dict "PACKAGE_PIN $pin IOSTANDARD LVCMOS33" [get_ports "dout[$i]"]
+   }
+} else {
+    error "Unsupported part $part"
+}
+
+create_pblock roi
+set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi]
+add_cells_to_pblock [get_pblocks roi] [get_cells roi]
+resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
+
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
+
+#write_checkpoint -force synth.dcp
+
+
+
+proc loc_roi_clk_left {ff_x ff_y} {
+    # Place an ROI clk on the left edge of the ROI
+    # It doesn't actually matter where we place this, just do it to keep things neat looking
+    # ff_x: ROI SLICE X position
+    # ff_yy: row primitives will be placed at
+
+    set slice_ff "SLICE_X${ff_x}Y${ff_y}"
+
+    # Fix FFs to guide route in
+    set cell [get_cells "roi/clk_reg_reg"]
+    set_property LOC $slice_ff $cell
+    set_property BEL AFF $cell
+}
+
+proc loc_roi_in_left {index lut_x y} {
+    # Place an ROI input on the left edge of the ROI
+    # index: input bus index
+    # lut_x: ROI SLICE X position. FF position is implicit to left
+    # y: row primitives will be placed at
+
+    set slice_lut "SLICE_X${lut_x}Y${y}"
+
+    # Fix LUTs near the edge
+    set cell [get_cells "roi/ins[$index].lut"]
+    set_property LOC $slice_lut $cell
+    set_property BEL A6LUT $cell
+}
+
+proc loc_roi_out_left {index lut_x y} {
+    # Place an ROI output on the left edge of the ROI
+    # index: input bus index
+    # lut_x: ROI SLICE X position. FF position is implicit to left
+    # y: row primitives will be placed at
+
+    set slice_lut "SLICE_X${lut_x}Y${y}"
+
+    # Fix LUTs near the edge
+    set cell [get_cells "roi/outs[$index].lut"]
+    set_property LOC $slice_lut $cell
+    set_property BEL A6LUT $cell
+}
+
+
+if {1} {
+    set x $X_BASE
+
+    # Place ROI clock right after inputs
+    puts "Placing ROI clock"
+    loc_roi_clk_left $x $Y_CLK_BASE
+
+    # Place ROI inputs
+    puts "Placing ROI inputs"
+    set y $Y_DIN_BASE
+    for {set i 0} {$i < $DIN_N} {incr i} {
+        loc_roi_in_left $i $x $y
+        set y [expr {$y + 1}]
+    }
+
+    # Place ROI outputs
+    set y $Y_DOUT_BASE
+    puts "Placing ROI outputs"
+    for {set i 0} {$i < $DOUT_N} {incr i} {
+        loc_roi_out_left $i $x $y
+        set y [expr {$y + 1}]
+    }
+}
+
+place_design
+#write_checkpoint -force placed.dcp
+
+# Version with more error checking for missing end node
+# Will do best effort in this case
+proc route_via2 {net nodes} {
+    # net: net as string
+    # nodes: string list of one or more intermediate routing nodes to visit
+
+	set net [get_nets $net]
+	# Start at the net source
+	set fixed_route [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]]
+	# End at the net destination
+	# For sone reason this doesn't always show up
+	set site_pins [get_site_pins -filter {DIRECTION == IN} -of_objects $net]
+    if {$site_pins eq ""} {
+        puts "WARNING: could not find end node"
+        #error "Could not find end node"
+    } else {
+    	set end_node [get_nodes -of_objects]
+    	lappend nodes [$end_node]
+	}
+
+	puts ""
+	puts "Routing net $net:"
+
+	foreach to_node $nodes {
+        if {$to_node eq ""} {
+            error "Empty node"
+        }
+
+	    # Node string to object
+		set to_node [get_nodes -of_objects [get_wires $to_node]]
+		# Start at last routed position
+		set from_node [lindex $fixed_route end]
+		# Let vivado do heavy liftin in between
+		set route [find_routing_path -quiet -from $from_node -to $to_node]
+		if {$route == ""} {
+		    # Some errors print a huge route
+			puts [concat [string range "  $from_node -> $to_node" 0 1000] ": no route found - assuming direct PIP"]
+			lappend fixed_route $to_node
+		} {
+			puts [concat [string range "  $from_node -> $to_node: $route" 0 1000] "routed"]
+			set fixed_route [concat $fixed_route [lrange $route 1 end]]
+		}
+		set_property -quiet FIXED_ROUTE $fixed_route $net
+	}
+
+	set_property -quiet FIXED_ROUTE $fixed_route $net
+	puts ""
+}
+
+# XXX: maybe add IOB?
+set fp [open "design.txt" w]
+puts $fp "name node"
+if {1} {
+    set x $X_BASE
+
+    # Nothing needed for clk
+    # It will go to high level interconnect that goes everywhere
+
+    puts "Routing ROI inputs"
+    # Arbitrary offset as observed
+    set y [expr {$Y_DIN_BASE - 1}]
+    for {set i 0} {$i < $DIN_N} {incr i} {
+        #route_via2 "din_IBUF[$i]" "INT_R_X9Y${y}/NE2BEG3"
+        # needed to force routes away to avoid looping into ROI
+        #set x_EE2BEG3 [expr {$x - 2}]
+        set x_EE2BEG3 7
+        set x_NE2BEG3 9
+        set node "INT_R_X${x_NE2BEG3}Y${y}/NE2BEG3"
+        route_via2 "din_IBUF[$i]" "INT_R_X${x_EE2BEG3}Y${y}/EE2BEG3 $node"
+        puts $fp "din[$i] $node"
+
+        set y [expr {$y + 1}]
+    }
+
+    puts "Routing ROI outputs"
+    # Arbitrary offset as observed
+    set y [expr {$Y_DOUT_BASE + 0}]
+    for {set i 0} {$i < $DOUT_N} {incr i} {
+        # XXX: find a better solution if we need harness long term
+        # works on 50t but not 35t
+        if {$part eq "xc7a50tfgg484-1"} {
+            set node "INT_L_X10Y${y}/WW2BEG0"
+            route_via2 "roi/dout[$i]" "$node"
+        # works on 35t but not 50t
+        } elseif {$part eq "xc7a35tcsg324-1"} {
+            set node "INT_L_X10Y${y}/SW6BEG0"
+            route_via2 "roi/dout[$i]" "$node"
+        } else {
+            error "Unsupported part $part"
+        }
+        puts $fp "dout[$i] $node"
+        set y [expr {$y + 1}]
+    }
+}
+close $fp
+
+puts "routing design"
+route_design
+
+write_checkpoint -force design.dcp
+write_bitstream -force design.bit
+
diff --git a/minitests/roi_harness/top.v b/minitests/roi_harness/top.v
new file mode 100644
index 00000000..efe551fe
--- /dev/null
+++ b/minitests/roi_harness/top.v
@@ -0,0 +1,65 @@
+//See README and tcl for more info
+
+`ifndef DIN_N
+`define DIN_N 4
+`endif
+
+`ifndef DOUT_N
+`define DOUT_N 4
+`endif
+
+module top(input wire clk,
+        input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
+    parameter DIN_N = `DIN_N;
+    parameter DOUT_N = `DOUT_N;
+
+    roi #(.DIN_N(DIN_N), .DOUT_N(DOUT_N)) roi (
+        .clk(clk),
+        .din(din), .dout(dout));
+endmodule
+
+module roi(input clk,
+        input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
+    parameter DIN_N = 4;
+    parameter DOUT_N = 4;
+
+    genvar i;
+    generate
+        //CLK
+        (* KEEP, DONT_TOUCH *)
+        reg clk_reg;
+        always @(posedge clk) begin
+            clk_reg <= clk_reg;
+        end
+
+        //DIN
+        for (i = 0; i < DIN_N; i = i+1) begin:ins
+            (* KEEP, DONT_TOUCH *)
+            LUT6 #(
+                .INIT(64'b01)
+            ) lut (
+                .I0(din[i]),
+                .I1(1'b0),
+                .I2(1'b0),
+                .I3(1'b0),
+                .I4(1'b0),
+                .I5(1'b0),
+                .O());
+        end
+
+        //DOUT
+        for (i = 0; i < DOUT_N; i = i+1) begin:outs
+            (* KEEP, DONT_TOUCH *)
+            LUT6 #(
+                .INIT(64'b01)
+            ) lut (
+                .I0(1'b0),
+                .I1(1'b0),
+                .I2(1'b0),
+                .I3(1'b0),
+                .I4(1'b0),
+                .I5(1'b0),
+                .O(dout[i]));
+        end
+    endgenerate
+endmodule
diff --git a/utils/tileconnwire.py b/utils/tileconnwire.py
new file mode 100644
index 00000000..edddc605
--- /dev/null
+++ b/utils/tileconnwire.py
@@ -0,0 +1,34 @@
+#!/usr/bin/env python3
+
+import os, sys, json
+
+if len(sys.argv) != 3:
+    print("Usage example: python3 %s HCLK_R HCLK_SW6E3" % sys.argv[0])
+    sys.exit(1)
+
+with open("%s/%s/tileconn.json" % (os.getenv("XRAY_DATABASE_DIR"), os.getenv("XRAY_DATABASE")), "r") as f:
+    tileconn = json.load(f)
+
+outdata = list()
+max_tiletype_len = 1
+
+for entry in tileconn:
+    if entry["tile_types"][0] == sys.argv[1]:
+        this_idx, other_idx = 0, 1
+        delta_x, delta_y = entry["grid_deltas"]
+    elif entry["tile_types"][1] == sys.argv[1]:
+        this_idx, other_idx = 1, 0
+        delta_x, delta_y = -entry["grid_deltas"][0], -entry["grid_deltas"][1]
+    else:
+        continue
+
+    for wire_pair in entry["wire_pairs"]:
+        if wire_pair[this_idx] != sys.argv[2]:
+            continue
+
+        outdata.append((delta_x, delta_y, entry["tile_types"][other_idx], wire_pair[other_idx]))
+        max_tiletype_len = max(max_tiletype_len, len(entry["tile_types"][other_idx]))
+
+for entry in outdata:
+    print("%3d %3d  %-*s  %s" % (entry[0], entry[1], max_tiletype_len, entry[2], entry[3]))
+