From 2f143b18b8f00867499adec57bd346ad1756c680 Mon Sep 17 00:00:00 2001 From: Maciej Kurc Date: Tue, 3 Sep 2019 16:35:08 +0200 Subject: [PATCH] Code polish Signed-off-by: Maciej Kurc --- .../iserdes.idelay/sim/error_counter_tb.v | 3 - minitests/iserdes.idelay/src/error_counter.v | 2 + .../iserdes.idelay/src/idelay_histogram.v | 216 ------------------ .../src/iserdes_idelay_histogram.v | 2 + minitests/iserdes.idelay/src/lfsr.v | 28 +-- .../iserdes_idelay_histogram_receiver.py | 19 +- 6 files changed, 31 insertions(+), 239 deletions(-) delete mode 100644 minitests/iserdes.idelay/src/idelay_histogram.v diff --git a/minitests/iserdes.idelay/sim/error_counter_tb.v b/minitests/iserdes.idelay/sim/error_counter_tb.v index 00d901bf..142e99f9 100644 --- a/minitests/iserdes.idelay/sim/error_counter_tb.v +++ b/minitests/iserdes.idelay/sim/error_counter_tb.v @@ -38,9 +38,6 @@ always @(posedge CLK) // ============================================================================ -//re i_stb = (cycle_cnt == 10); -//re [32*2-1:0] i_dat = 64'h01234567_ABCD4321; - wire o_stb; wire [4*8-1:0] o_dat; diff --git a/minitests/iserdes.idelay/src/error_counter.v b/minitests/iserdes.idelay/src/error_counter.v index 0758b18a..28df2ebd 100644 --- a/minitests/iserdes.idelay/src/error_counter.v +++ b/minitests/iserdes.idelay/src/error_counter.v @@ -1,5 +1,7 @@ `default_nettype none +// ============================================================================ + module error_counter # ( parameter COUNT_WIDTH = 24, diff --git a/minitests/iserdes.idelay/src/idelay_histogram.v b/minitests/iserdes.idelay/src/idelay_histogram.v deleted file mode 100644 index b5cd3752..00000000 --- a/minitests/iserdes.idelay/src/idelay_histogram.v +++ /dev/null @@ -1,216 +0,0 @@ -module idelay_histogram # -( -parameter UART_PRESCALER = 868 // UART prescaler -) -( -// Closk & reset -input wire CLK, -input wire RST, - -// UART -input wire UART_RX, -output wire UART_TX, - -// TEST - internal loopback -input wire TEST, - -// Input and output pins -output wire O, -input wire I, - -output wire REF_O, -output wire REF_I, - -// IDELAY delay setting output -output wire [4:0] DELAY -); - -// ============================================================================ -// Data generator -reg [1:0] ce_cnt; -wire ce; - -always @(posedge CLK) - ce_cnt <= ce_cnt + 1; - -assign ce = (ce_cnt == 0); - -// LFSR -wire [15:0] lfsr_r; - -lfsr lfsr -( -.clk (CLK), -.rst (RST), -.ce (ce), -.r (lfsr_r) -); - -reg o_stb; -wire o_dat; - -always @(posedge CLK) - if (RST) - o_stb <= 1'b0; - else - o_stb <= ce; - -assign o_dat = lfsr_r[0]; -assign O = o_dat; - -// ============================================================================ -// Data input with IDELAY -wire dly_dat; -wire dly_ld; -wire [5:0] dly_cnt; - -IDELAYE2 # -( -.IDELAY_TYPE ("VAR_LOAD"), -.DELAY_SRC ("IDATAIN") -) -idelay -( -.IDATAIN (I), -.DATAOUT (dly_dat), - -.C (CLK), -.LD (dly_ld), -.CNTVALUEIN (dly_cnt), -.CNTVALUEOUT(DELAY) -); - -assign OI = dly_dat; - -// ============================================================================ -// Data comparator -reg o_dat_r; - -reg cmp_s0_stb; -reg cmp_s0_o_dat; -reg cmp_s0_i_dat; - -reg cmp_s1_stb; -reg cmp_s1_err; - -always @(posedge CLK) - o_dat_r <= o_dat; - -always @(posedge CLK) - if (RST) - cmp_s0_stb <= 1'b0; - else - cmp_s0_stb <= o_stb; - -always @(posedge CLK) - if (o_stb) - cmp_s0_o_dat <= o_dat_r; -always @(posedge CLK) - if (o_stb) - cmp_s0_i_dat <= (TEST) ? O : dly_dat; - - -always @(posedge CLK) - if (RST) - cmp_s1_stb <= 1'b0; - else - cmp_s1_stb <= cmp_s0_stb; - -always @(posedge CLK) - cmp_s1_err <= cmp_s0_o_dat ^ cmp_s0_i_dat; - -assign REF_O = o_dat_r; -assign REF_I = dly_dat; - -// ============================================================================ -// Error counter -wire cnt_stb; -wire [32*24-1:0] cnt_dat; - -error_counter # -( -.COUNT_WIDTH (24), -.DELAY_TAPS (32), - -.TRIGGER_INTERVAL (50000000), -.HOLDOFF_TIME (100), -.MEASURE_TIME (10000) -) -error_counter -( -.CLK (CLK), -.RST (RST), - -.I_STB (cmp_s1_stb), -.I_ERR (cmp_s1_err), - -.DLY_LD (dly_ld), -.DLY_CNT(dly_cnt), - -.O_STB (cnt_stb), -.O_DAT (cnt_dat) -); - -// ============================================================================ -// Message formatter -wire uart_x_stb; -wire [7:0] uart_x_dat; - -message_formatter # -( -.WIDTH (24), -.COUNT (32), -.TX_INTERVAL (UART_PRESCALER * 11) // 10 bits plus one more. -) -message_formatter -( -.CLK (CLK), -.RST (RST), - -.I_STB (cnt_stb), -.I_DAT (cnt_dat), - -.O_STB (uart_x_stb), -.O_DAT (uart_x_dat) -); - -// ============================================================================ -// UART - -// Baudrate prescaler initializer -reg [7:0] reg_div_we_sr; -wire reg_div_we; - -always @(posedge CLK) - if (RST) reg_div_we_sr <= 8'h01; - else reg_div_we_sr <= {reg_div_we_sr[6:0], 1'd0}; - -assign reg_div_we = reg_div_we_sr[7]; - -// The UART -simpleuart uart -( -.clk (CLK), -.resetn (!RST), - -.ser_rx (UART_RX), -.ser_tx (UART_TX), - -.reg_div_we ({reg_div_we, reg_div_we, reg_div_we, reg_div_we}), -.reg_div_di (UART_PRESCALER), -.reg_div_do (), - -.reg_dat_we (uart_x_stb), -.reg_dat_re (1'd0), -.reg_dat_di ({24'd0, uart_x_dat}), -.reg_dat_do (), -.reg_dat_wait () -); - -// Debug -always @(posedge CLK) - if (uart_x_stb) - $display("%c", uart_x_dat); - -endmodule - diff --git a/minitests/iserdes.idelay/src/iserdes_idelay_histogram.v b/minitests/iserdes.idelay/src/iserdes_idelay_histogram.v index 4e152248..d8fc6e2d 100644 --- a/minitests/iserdes.idelay/src/iserdes_idelay_histogram.v +++ b/minitests/iserdes.idelay/src/iserdes_idelay_histogram.v @@ -1,3 +1,5 @@ +// ============================================================================ + module iserdes_idelay_histogram # ( parameter UART_PRESCALER = 868, // UART prescaler diff --git a/minitests/iserdes.idelay/src/lfsr.v b/minitests/iserdes.idelay/src/lfsr.v index 93c7d9e8..647e3a11 100644 --- a/minitests/iserdes.idelay/src/lfsr.v +++ b/minitests/iserdes.idelay/src/lfsr.v @@ -4,25 +4,25 @@ module lfsr # ( - parameter WIDTH = 16, - parameter [WIDTH-1:0] POLY = 16'hD008, - parameter [WIDTH-1:0] SEED = 1 +parameter WIDTH = 16, // LFSR width +parameter [WIDTH-1:0] POLY = 16'hD008, // Polynomial +parameter [WIDTH-1:0] SEED = 1 // Initial value ) ( - input wire clk, - input wire rst, - input wire ce, - output reg [WIDTH-1:0] r +input wire clk, +input wire rst, +input wire ce, +output reg [WIDTH-1:0] r ); - wire feedback = ^(r & POLY); +wire feedback = ^(r & POLY); - always @(posedge clk) begin - if(rst) begin - r <= SEED; - end else if(ce) begin - r <= {r[WIDTH-2:0], feedback}; - end +always @(posedge clk) begin + if(rst) begin + r <= SEED; + end else if(ce) begin + r <= {r[WIDTH-2:0], feedback}; end +end endmodule diff --git a/minitests/iserdes.idelay/utils/iserdes_idelay_histogram_receiver.py b/minitests/iserdes.idelay/utils/iserdes_idelay_histogram_receiver.py index aab448bb..afc48fff 100755 --- a/minitests/iserdes.idelay/utils/iserdes_idelay_histogram_receiver.py +++ b/minitests/iserdes.idelay/utils/iserdes_idelay_histogram_receiver.py @@ -1,18 +1,26 @@ #!/usr/bin/env python3 - """ -This script +This script receives and parses data generated by the "histogram" test design. """ +import argparse import serial # ============================================================================= def main(): - + + parser = argparse.ArgumentParser( + description=__doc__, + formatter_class=argparse.RawDescriptionHelpFormatter) + parser.add_argument("port", type=str, help="Serial port name") + parser.add_argument("--baud", type=int, default=115200, help="Baudrate") + + args = parser.parse_args() + # Open serial port - port = serial.Serial("/dev/ttyUSB3", baudrate=115200) + port = serial.Serial(args.port, baudrate=args.baud) # Get first line and discard it. It may be broken port.readline() @@ -26,9 +34,8 @@ def main(): data = [int(x, base=16) for x in line.split("_")] print(" ".join("%4d" % x for x in data)) -# ============================================================================= +# ============================================================================= if __name__ == "__main__": main() -