From 2f08afa6ef61be77ce1c1ceadb8f6f3b246d7fd4 Mon Sep 17 00:00:00 2001 From: Hans Baier Date: Thu, 5 Jun 2025 05:30:50 +0700 Subject: [PATCH] 036-iob-ologic: Also fuzz DATA_WIDTH 10 and 14 Signed-off-by: Hans Baier --- fuzzers/036-iob-ologic/generate.py | 2 +- fuzzers/036-iob-ologic/generate.tcl | 2 ++ fuzzers/036-iob-ologic/top.py | 2 +- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/fuzzers/036-iob-ologic/generate.py b/fuzzers/036-iob-ologic/generate.py index 7aa10284..79568e19 100644 --- a/fuzzers/036-iob-ologic/generate.py +++ b/fuzzers/036-iob-ologic/generate.py @@ -42,7 +42,7 @@ def no_oserdes(segmk, site): widths = [2, 3, 4, 5, 6, 7, 8] else: assert mode == 'DDR' - widths = [4, 6, 8] + widths = [4, 6, 8, 10, 14] for opt in widths: segmk.add_site_tag( diff --git a/fuzzers/036-iob-ologic/generate.tcl b/fuzzers/036-iob-ologic/generate.tcl index b61e69d8..04de7c51 100644 --- a/fuzzers/036-iob-ologic/generate.tcl +++ b/fuzzers/036-iob-ologic/generate.tcl @@ -94,6 +94,8 @@ proc run {} { set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] set_property IS_ENABLED 0 [get_drc_checks {REQP-79}] set_property IS_ENABLED 0 [get_drc_checks {REQP-144}] + set_property IS_ENABLED 0 [get_drc_checks {REQP-150}] + set_property IS_ENABLED 0 [get_drc_checks {REQP-152}] write_checkpoint -force design_pre_place.dcp diff --git a/fuzzers/036-iob-ologic/top.py b/fuzzers/036-iob-ologic/top.py index 4977a5ef..65e67f12 100644 --- a/fuzzers/036-iob-ologic/top.py +++ b/fuzzers/036-iob-ologic/top.py @@ -64,7 +64,7 @@ def use_oserdese2(p, luts, connects): if verilog.unquote(p['DATA_RATE_OQ']) == 'SDR': data_widths = [2, 3, 4, 5, 6, 7, 8] else: - data_widths = [4, 6, 8] + data_widths = [4, 6, 8, 10, 14] p['DATA_WIDTH'] = random.choice(data_widths)