diff --git a/fuzzers/035-iob-ilogic/generate.py b/fuzzers/035-iob-ilogic/generate.py index f907b938..ab23951f 100644 --- a/fuzzers/035-iob-ilogic/generate.py +++ b/fuzzers/035-iob-ilogic/generate.py @@ -4,6 +4,16 @@ from prjxray.segmaker import Segmaker from prjxray import verilog import json +# Set to true to enable additional tags useful for tracing bit toggles. +DEBUG_FUZZER = False + + +def bitfilter(frame, word): + if frame < 25 or frame > 31: + return False + + return True + def handle_data_width(segmk, d): if 'DATA_WIDTH' not in d: @@ -41,6 +51,11 @@ def main(): handle_data_width(segmk, d) handle_data_rate(segmk, d) + segmk.add_site_tag(site, 'ISERDES.IN_USE', d['use_iserdese2']) + segmk.add_site_tag( + site, 'IDDR_OR_ISERDES.IN_USE', d['use_iserdese2'] + or d['iddr_mux_config'] != 'none') + if 'INTERFACE_TYPE' in d: for opt in ( 'MEMORY', @@ -52,6 +67,13 @@ def main(): segmk.add_site_tag( site, 'ISERDES.INTERFACE_TYPE.{}'.format(opt), opt == verilog.unquote(d['INTERFACE_TYPE'])) + segmk.add_site_tag( + site, 'ISERDES.INTERFACE_TYPE.Z_{}'.format(opt), + opt != verilog.unquote(d['INTERFACE_TYPE'])) + + segmk.add_site_tag( + site, 'ISERDES.INTERFACE_TYPE.NOT_MEMORY', + 'MEMORY' not in verilog.unquote(d['INTERFACE_TYPE'])) if d['iddr_mux_config'] != 'none': segmk.add_site_tag(site, 'IFF.ZINIT_Q1', not d['INIT_Q1']) @@ -71,6 +93,10 @@ def main(): if 'IS_CLK_INVERTED' in d: if verilog.unquote(d['INTERFACE_TYPE']) == 'MEMORY_DDR3': + segmk.add_site_tag( + site, 'IFF.INV_CLK', d['IS_CLK_INVERTED']) + segmk.add_site_tag( + site, 'IFF.INV_CLKB', d['IS_CLKB_INVERTED']) segmk.add_site_tag( site, 'IFF.ZINV_CLK', not d['IS_CLK_INVERTED']) segmk.add_site_tag( @@ -98,8 +124,20 @@ def main(): and d['IS_CLKB_INVERTED'])) if 'IS_OCLK_INVERTED' in d: + segmk.add_site_tag( + site, 'IFF.INV_OCLK', d['IS_OCLK_INVERTED']) segmk.add_site_tag( site, 'IFF.ZINV_OCLK', not d['IS_OCLK_INVERTED']) + segmk.add_site_tag( + site, 'IFF.INV_OCLKB', d['IS_OCLKB_INVERTED']) + segmk.add_site_tag( + site, 'IFF.ZINV_OCLKB', not d['IS_OCLKB_INVERTED']) + + if 'IS_CLKDIV_INVERTED' in d: + segmk.add_site_tag( + site, 'IFF.INV_CLKDIV', d['IS_CLKDIV_INVERTED']) + segmk.add_site_tag( + site, 'IFF.ZINV_CLKDIV', not d['IS_CLKDIV_INVERTED']) if 'IS_C_INVERTED' in d: segmk.add_site_tag( @@ -120,32 +158,14 @@ def main(): site, 'IFF.DDR_CLK_EDGE.{}'.format(opt), verilog.unquote(d['DDR_CLK_EDGE']) == opt) - ofb_used = False - if 'OFB_USED' in d and d['OFB_USED']: - ofb_used = True - if d['iddr_mux_config'] == 'direct': segmk.add_site_tag(site, 'IFFDELMUXE3.0', 0) segmk.add_site_tag(site, 'IFFDELMUXE3.1', 1) segmk.add_site_tag(site, 'IFFDELMUXE3.2', 0) - - if ofb_used: - segmk.add_site_tag(site, 'IFFMUX.1', 1) - segmk.add_site_tag(site, 'IFFMUX.0', 0) - else: - segmk.add_site_tag(site, 'IFFMUX.1', 0) - segmk.add_site_tag(site, 'IFFMUX.0', 1) elif d['iddr_mux_config'] == 'idelay': segmk.add_site_tag(site, 'IFFDELMUXE3.0', 1) segmk.add_site_tag(site, 'IFFDELMUXE3.1', 0) segmk.add_site_tag(site, 'IFFDELMUXE3.2', 0) - - if ofb_used: - segmk.add_site_tag(site, 'IFFMUX.1', 1) - segmk.add_site_tag(site, 'IFFMUX.0', 0) - else: - segmk.add_site_tag(site, 'IFFMUX.1', 0) - segmk.add_site_tag(site, 'IFFMUX.0', 1) elif d['iddr_mux_config'] == 'none': segmk.add_site_tag(site, 'IFFDELMUXE3.0', 0) segmk.add_site_tag(site, 'IFFDELMUXE3.1', 0) @@ -158,23 +178,11 @@ def main(): segmk.add_site_tag(site, 'IDELMUXE3.1', 1) segmk.add_site_tag(site, 'IDELMUXE3.2', 0) - if ofb_used: - segmk.add_site_tag(site, 'IMUX.1', 1) - segmk.add_site_tag(site, 'IMUX.0', 0) - else: - segmk.add_site_tag(site, 'IMUX.1', 0) - segmk.add_site_tag(site, 'IMUX.0', 1) elif d['mux_config'] == 'idelay': segmk.add_site_tag(site, 'IDELMUXE3.0', 1) segmk.add_site_tag(site, 'IDELMUXE3.1', 0) segmk.add_site_tag(site, 'IDELMUXE3.2', 0) - if ofb_used: - segmk.add_site_tag(site, 'IMUX.1', 1) - segmk.add_site_tag(site, 'IMUX.0', 0) - else: - segmk.add_site_tag(site, 'IMUX.1', 0) - segmk.add_site_tag(site, 'IMUX.0', 1) elif d['mux_config'] == 'none': segmk.add_site_tag(site, 'IDELMUXE3.0', 0) segmk.add_site_tag(site, 'IDELMUXE3.1', 0) @@ -182,7 +190,13 @@ def main(): else: assert False, d['mux_config'] - segmk.compile() + if DEBUG_FUZZER: + for k in d: + segmk.add_site_tag( + site, 'param_' + k + '_' + str(d[k]).replace( + ' ', '').replace('\n', ''), 1) + + segmk.compile(bitfilter=bitfilter) segmk.write(allow_empty=True) diff --git a/fuzzers/035-iob-ilogic/generate.tcl b/fuzzers/035-iob-ilogic/generate.tcl index 85caab36..b4132fe9 100644 --- a/fuzzers/035-iob-ilogic/generate.tcl +++ b/fuzzers/035-iob-ilogic/generate.tcl @@ -86,6 +86,7 @@ proc run {} { set_property CONFIG_VOLTAGE 3.3 [current_design] set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] set_property IS_ENABLED 0 [get_drc_checks {REQP-79}] + set_property IS_ENABLED 0 [get_drc_checks {PDRC-26}] write_checkpoint -force design_pre_place.dcp diff --git a/fuzzers/035-iob-ilogic/top.py b/fuzzers/035-iob-ilogic/top.py index 7dc7320e..b7e6e1dc 100644 --- a/fuzzers/035-iob-ilogic/top.py +++ b/fuzzers/035-iob-ilogic/top.py @@ -58,6 +58,8 @@ def use_iserdese2(p, luts, connects): p['IS_CLK_INVERTED'] = random.randint(0, 1) p['IS_CLKB_INVERTED'] = random.randint(0, 1) p['IS_OCLK_INVERTED'] = random.randint(0, 1) + p['IS_OCLKB_INVERTED'] = random.randint(0, 1) + p['IS_CLKDIV_INVERTED'] = random.randint(0, 1) p['IS_D_INVERTED'] = random.randint(0, 1) p['INTERFACE_TYPE'] = verilog.quote( random.choice( @@ -163,6 +165,30 @@ def use_iserdese2(p, luts, connects): else: p['ofb_connections'] = '' + if random.randint(0, 1): + clknet = luts.get_next_output_net() + else: + clknet = random.choice(( + 'clk_BUFG1', + 'clk_BUFG2', + )) + + if random.randint(0, 1): + clkbnet = luts.get_next_output_net() + else: + clkbnet = random.choice(( + 'clk_BUFG1', + 'clk_BUFG2', + )) + + if random.randint(0, 1): + oclknet = luts.get_next_output_net() + else: + oclknet = random.choice(( + 'clk_BUFG1', + 'clk_BUFG2', + )) + print( ''' (* KEEP, DONT_TOUCH, LOC = "{ilogic_loc}" *) @@ -182,6 +208,8 @@ def use_iserdese2(p, luts, connects): .IS_CLK_INVERTED({IS_CLK_INVERTED}), .IS_CLKB_INVERTED({IS_CLKB_INVERTED}), .IS_OCLK_INVERTED({IS_OCLK_INVERTED}), + .IS_OCLKB_INVERTED({IS_OCLKB_INVERTED}), + .IS_CLKDIV_INVERTED({IS_CLKDIV_INVERTED}), .IS_D_INVERTED({IS_D_INVERTED}), .OFB_USED({OFB_USED}), .NUM_CE({NUM_CE}), @@ -198,9 +226,9 @@ def use_iserdese2(p, luts, connects): .Q1({q1net}), .CLKDIV(0) );'''.format( - clknet=luts.get_next_output_net(), - clkbnet=luts.get_next_output_net(), - oclknet=luts.get_next_output_net(), + clknet=clknet, + clkbnet=clkbnet, + oclknet=oclknet, onet=luts.get_next_input_net(), q1net=luts.get_next_input_net(), shiftout1net=luts.get_next_input_net(), @@ -385,6 +413,18 @@ module top(input clk, inout wire [`N_DI-1:0] dio); wire [`N_DI-1:0] di_buf; wire [`N_DI-1:0] do_buf; wire [`N_DI-1:0] t; + + wire clk_BUFG1; + wire clk_BUFG2; + + (* KEEP, DONT_TOUCH *) + BUFG bufg1( + .O(clk_BUFG1) + ); + (* KEEP, DONT_TOUCH *) + BUFG bufg2( + .O(clk_BUFG2) + ); '''.format(n_di=idx)) # Always output a LUT6 to make placer happy.