diff --git a/fuzzers/037-iob-pips/generate.tcl b/fuzzers/037-iob-pips/generate.tcl
index 1aab4b0b..c5f74c59 100644
--- a/fuzzers/037-iob-pips/generate.tcl
+++ b/fuzzers/037-iob-pips/generate.tcl
@@ -23,6 +23,51 @@ proc write_pip_txtdata {filename} {
     close $fp
 }
 
+proc make_manual_routes {filename} {
+    puts "MANROUTE: Loading routes from $filename"
+
+    set fp [open $filename r]
+    foreach line [split [read $fp] "\n"] {
+        if {$line eq ""} {
+            continue
+        }
+
+        puts "MANROUTE: Line: $line"
+
+        # Parse the line
+        set fields [split $line " "]
+        set net_name [lindex $fields 0]
+        set wire_name [lindex $fields 1]
+
+        # Check if that net exist
+        if {[get_nets $net_name] eq ""} {
+            puts "MANROUTE: net $net_name does not exist"
+            continue
+        }
+
+        set net [get_nets $net_name]
+
+        # Rip it up
+        set_property -quiet FIXED_ROUTE "" $net
+        set_property IS_ROUTE_FIXED 0 $net
+        route_design -unroute -nets $net
+
+        # Make the route
+        set nodes [get_nodes -of_objects [get_wires $wire_name]]
+        set status [route_via $net_name [list $nodes] 0]
+
+        # Failure, skip manual routing of this net
+        if { $status != 1 } {
+            puts "MANROUTE: Manual routing failed!"
+            set_property -quiet FIXED_ROUTE "" $net
+            set_property IS_ROUTE_FIXED 0 $net
+            continue
+        }
+
+        puts "MANROUTE: Success!"
+    }
+}
+
 proc run {} {
     create_project -force -part $::env(XRAY_PART) design design
     read_verilog top.v
@@ -46,7 +91,8 @@ proc run {} {
 
     place_design -directive Quick
     write_checkpoint -force design_before_route.dcp
-    route_design -directive Quick
+    make_manual_routes routes.txt
+    route_design -directive Quick -preserve
     write_checkpoint -force design.dcp
 
     write_bitstream -force design.bit
diff --git a/fuzzers/037-iob-pips/top.py b/fuzzers/037-iob-pips/top.py
index 283c5ba3..ed5017cd 100644
--- a/fuzzers/037-iob-pips/top.py
+++ b/fuzzers/037-iob-pips/top.py
@@ -186,6 +186,7 @@ def run():
       """
 
     output = []
+    route_file = open("routes.txt", "w")
 
     for tile in gen_sites():
         if tile['tile_type'] in NOT_INCLUDED_TILES:
@@ -222,29 +223,48 @@ def run():
                         oclkb = random.randint(0, 1)
 
             DATA_RATE = random.choice(['DDR', 'SDR'])
-            clk, is_lut = clocks.get_clock(
+            clk, clk_is_lut = clocks.get_clock(
                 ilogic_site,
                 allow_ioclks=True,
                 allow_rclks=True,
                 allow_empty=DATA_RATE == 'SDR')
-            if False:
-                clkb = clk
-            else:
-                clkb = clk
-                if random.randint(0, 1):
-                    while clkb == clk:
-                        clkb, _ = clocks.get_clock(
-                            ilogic_site,
-                            allow_ioclks=True,
-                            allow_rclks=True,
-                            allow_empty=False)
-                else:
-                    # Explicitly provide IMUX stimulus to resolve IMUX pips
-                    clk = random.randint(0, 1)
-                    clkb = random.randint(0, 1)
+
+            clkb = clk
+            while clkb == clk:
+                clkb, clkb_is_lut = clocks.get_clock(
+                    ilogic_site,
+                    allow_ioclks=True,
+                    allow_rclks=True,
+                    allow_empty=False)
+
+            imux_available = {
+                0: set(("IOI_IMUX20_0", "IOI_IMUX22_0")),
+                1: set(("IOI_IMUX20_1", "IOI_IMUX22_1")),
+            }
+
+            # Force CLK route through IMUX when connected to a LUT
+            if clk_is_lut:
+                y = (xy[1] + 1) % 2
+
+                route = random.choice(list(imux_available[y]))
+                imux_available[y].remove(route)
+
+                route = "{}/{}".format(tile["tile"], route)
+                route_file.write("{} {}\n".format(clk, route))
+
+            # Force CLKB route through IMUX when connected to a LUT
+            if clkb_is_lut:
+                y = (xy[1] + 1) % 2
+
+                route = random.choice(list(imux_available[y]))
+                imux_available[y].remove(route)
+
+                route = "{}/{}".format(tile["tile"], route)
+                route_file.write("{} {}\n".format(clkb, route))
 
             if ilogic_site_type is None:
                 pass
+
             elif ilogic_site_type == 'ISERDESE2':
                 INTERFACE_TYPE = random.choice(
                     [