From 21b0cc54f88850f7f8e40291fb5aa57527b9ca72 Mon Sep 17 00:00:00 2001
From: Keith Rothman <537074+litghost@users.noreply.github.com>
Date: Mon, 5 Aug 2019 17:34:54 -0700
Subject: [PATCH] Split CCIO ACTIVE into two features.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
---
 fuzzers/045-hclk-cmt-pips/generate.py    | 45 +++++++++++++++++++++---
 fuzzers/045-hclk-cmt-pips/output_cmt.tcl |  2 +-
 fuzzers/045-hclk-cmt-pips/top.py         | 26 ++++++++++----
 3 files changed, 60 insertions(+), 13 deletions(-)

diff --git a/fuzzers/045-hclk-cmt-pips/generate.py b/fuzzers/045-hclk-cmt-pips/generate.py
index 492e3f28..4c964b3a 100644
--- a/fuzzers/045-hclk-cmt-pips/generate.py
+++ b/fuzzers/045-hclk-cmt-pips/generate.py
@@ -12,6 +12,16 @@ def bitfilter(frame, word):
     return True
 
 
+IOCLK_MAP = {
+    'HCLK_IOI_I2IOCLK_TOP0': 'HCLK_CMT_CCIO0',
+    'HCLK_IOI_I2IOCLK_TOP1': 'HCLK_CMT_CCIO1',
+    'HCLK_IOI_I2IOCLK_BOT0': 'HCLK_CMT_CCIO2',
+    'HCLK_IOI_I2IOCLK_BOT1': 'HCLK_CMT_CCIO3',
+}
+
+IOCLK_SRCS = set(IOCLK_MAP.values())
+
+
 def main():
     segmk = Segmaker("design.bits")
 
@@ -44,14 +54,25 @@ def main():
             tile_ports[tile_type].add(src)
             tile_ports[tile_type].add(dst)
 
+    tile_to_cmt = {}
+    cmt_to_hclk_cmt = {}
+    with open(os.path.join(os.getenv('FUZDIR'), 'build',
+                           'cmt_regions.csv')) as f:
+        for l in f:
+            site, cmt, tile = l.strip().split(',')
+
+            tile_to_cmt[tile] = cmt
+
+            if tile.startswith('HCLK_CMT'):
+                cmt_to_hclk_cmt[cmt] = tile
+
+    active_ioclks = set()
+
     print("Loading tags from design.txt.")
     with open("design.txt", "r") as f:
         for line in f:
             tile, pip, src, dst, pnum, pdir = line.split()
 
-            if not tile.startswith('HCLK_CMT'):
-                continue
-
             pip_prefix, _ = pip.split(".")
             tile_from_pip, tile_type = pip_prefix.split('/')
             assert tile == tile_from_pip
@@ -60,6 +81,13 @@ def main():
             pnum = int(pnum)
             pdir = int(pdir)
 
+            if src in IOCLK_MAP:
+                active_ioclks.add(
+                    (cmt_to_hclk_cmt[tile_to_cmt[tile]], IOCLK_MAP[src]))
+
+            if not tile.startswith('HCLK_CMT'):
+                continue
+
             if tile not in tiledata:
                 tiledata[tile] = {
                     "type": tile_type,
@@ -93,9 +121,16 @@ def main():
 
         for port in tile_ports[tile_type]:
             if port in tiledata[tile]["dsts"] or port in tiledata[tile]["srcs"]:
-                segmk.add_tile_tag(tile, "{}_ACTIVE".format(port), 1)
+                segmk.add_tile_tag(tile, "{}_USED".format(port), 1)
             else:
-                segmk.add_tile_tag(tile, "{}_ACTIVE".format(port), 0)
+                segmk.add_tile_tag(tile, "{}_USED".format(port), 0)
+
+        for ioclk in IOCLK_SRCS:
+            if ioclk in tiledata[tile]["srcs"] or (tile,
+                                                   ioclk) in active_ioclks:
+                segmk.add_tile_tag(tile, "{}_ACTIVE".format(ioclk), 1)
+            else:
+                segmk.add_tile_tag(tile, "{}_ACTIVE".format(ioclk), 0)
 
     segmk.compile(bitfilter=bitfilter)
     segmk.write()
diff --git a/fuzzers/045-hclk-cmt-pips/output_cmt.tcl b/fuzzers/045-hclk-cmt-pips/output_cmt.tcl
index 1ad5c1a0..6cc74090 100644
--- a/fuzzers/045-hclk-cmt-pips/output_cmt.tcl
+++ b/fuzzers/045-hclk-cmt-pips/output_cmt.tcl
@@ -5,7 +5,7 @@ open_io_design -name io_1
 set fp [open "cmt_regions.csv" "w"]
 foreach site_type {MMCME2_ADV PLLE2_ADV BUFMRCE BUFHCE IOB33M IOB18M BUFR} {
     foreach site [get_sites -filter "SITE_TYPE == $site_type"] {
-        puts $fp "$site,[get_property CLOCK_REGION $site]"
+        puts $fp "$site,[get_property CLOCK_REGION $site],[get_tiles -of $site]"
     }
 }
 close $fp
diff --git a/fuzzers/045-hclk-cmt-pips/top.py b/fuzzers/045-hclk-cmt-pips/top.py
index 5e67b0a2..4f2e8462 100644
--- a/fuzzers/045-hclk-cmt-pips/top.py
+++ b/fuzzers/045-hclk-cmt-pips/top.py
@@ -15,7 +15,7 @@ def read_site_to_cmt():
     with open(os.path.join(os.getenv('FUZDIR'), 'build',
                            'cmt_regions.csv')) as f:
         for l in f:
-            site, cmt = l.strip().split(',')
+            site, cmt, _ = l.strip().split(',')
             yield (site, cmt)
 
 
@@ -206,15 +206,26 @@ def main():
         '// mmcm_pll_only {} mmcm_pll_dir {}'.format(
             mmcm_pll_only, mmcm_pll_dir))
 
+    have_iob_clocks = random.random() > .1
+
+    iob_clks = {}
     for tile_name in sorted(hclk_cmt_tiles):
         for _, site, volt in get_paired_iobs(db, grid, tile_name):
+            iob_clock = 'clock_IBUF_{site}'.format(site=site)
+
+            cmt = site_to_cmt[site]
+
+            if cmt not in iob_clks:
+                iob_clks[cmt] = ['']
+
+            iob_clks[cmt].append(iob_clock)
 
             ins.append('input clk_{site}'.format(site=site))
-            if check_allowed(mmcm_pll_dir, site_to_cmt[site]):
-                clock_sources.add_clock_source(
-                    'clock_IBUF_{site}'.format(site=site), site_to_cmt[site])
-            adv_clock_sources.add_clock_source(
-                'clock_IBUF_{site}'.format(site=site), site_to_cmt[site])
+
+            if have_iob_clocks:
+                if check_allowed(mmcm_pll_dir, cmt):
+                    clock_sources.add_clock_source(iob_clock, cmt)
+                adv_clock_sources.add_clock_source(iob_clock, cmt)
 
             print(
                 """
@@ -400,8 +411,9 @@ module top({inputs});
     wire O_{site};
     (* KEEP, DONT_TOUCH, LOC = "{site}" *)
     BUFR bufr_{site} (
+        .I({I}),
         .O(O_{site})
-        );""".format(site=site))
+        );""".format(I=random.choice(iob_clks[site_to_cmt[site]]), site=site))
 
     for _, site in gen_sites('PLLE2_ADV'):
         for cin in ('cin1', 'cin2', 'clkfbin'):