diff --git a/fuzzers/041-clk-hrow-pips/Makefile b/fuzzers/041-clk-hrow-pips/Makefile
index 5aa5450e..f3677cf7 100644
--- a/fuzzers/041-clk-hrow-pips/Makefile
+++ b/fuzzers/041-clk-hrow-pips/Makefile
@@ -1,6 +1,7 @@
 export FUZDIR=$(shell pwd)
-PIP_TYPE?=clk_hrow
+PIP_TYPE?=clk_hrow_bot
 PIPLIST_TCL=$(FUZDIR)/clk_hrow_pip_list.tcl
+
 ifeq (${XRAY_PART}, xc7z010clg400-1)
 # xc7z010clg400-1 is missing some side clock connections, so these bits cannot
 # be documented.
@@ -9,7 +10,7 @@ else
 TODO_RE="[^\.]+\.CLK_HROW_CK_MUX_OUT_"
 endif
 
-MAKETODO_FLAGS=--no-l --pip-type clk_hrow_bot --seg-type clk_hrow_bot --re $(TODO_RE)
+MAKETODO_FLAGS=--no-l --pip-type ${PIP_TYPE} --seg-type clk_hrow_bot --re $(TODO_RE)
 N = 50
 
 # These PIPs all appear to be either a 1 bit solutions.
@@ -30,7 +31,7 @@ build/segbits_clk_hrow.rdb: $(SPECIMENS_OK)
 		$(shell find build -name segdata_clk_hrow_top_r.txt) \
 		$(shell find build -name segdata_clk_hrow_bot_r.txt)
 
-build/segbits_clk_hrow.db: build/segbits_clk_hrow.rdb $(XRAY_FUZZERS_DIR)/piplist/build/clk_hrow/clk_hrow_bot_r.txt
+build/segbits_clk_hrow.db: build/segbits_clk_hrow.rdb piplist
 	${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf \
 		--seg-fn-in build/segbits_clk_hrow.rdb \
 		--seg-fn-out build/segbits_clk_hrow_rc.db
@@ -38,7 +39,7 @@ build/segbits_clk_hrow.db: build/segbits_clk_hrow.rdb $(XRAY_FUZZERS_DIR)/piplis
 	# Convert row/column into PIP definition.
 	python3 merge_clk_entries.py \
 		build/segbits_clk_hrow_rc.db \
-		$(XRAY_FUZZERS_DIR)/piplist/build/clk_hrow/clk_hrow_bot_r.txt \
+		$(XRAY_FUZZERS_DIR)/piplist/build/${PIP_TYPE}/clk_hrow_bot_r.txt \
 		build/segbits_clk_hrow.db
 
 	# Keep a copy to track iter progress