From 1d394949e4dc3ebdb1b4be8a4cb81787aaf48c52 Mon Sep 17 00:00:00 2001
From: Maciej Kurc <mkurc@antmicro.com>
Date: Thu, 7 May 2020 13:57:10 +0200
Subject: [PATCH] Added setting INTERNAL_VREF in IOSTANDARD minitest.

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
---
 minitests/iostandard/features/generate.py | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/minitests/iostandard/features/generate.py b/minitests/iostandard/features/generate.py
index 669c7737..b938284d 100644
--- a/minitests/iostandard/features/generate.py
+++ b/minitests/iostandard/features/generate.py
@@ -39,9 +39,14 @@ IOBUF_NOT_ALLOWED = [
 
 DIFF_MAP = {
     'SSTL135': 'DIFF_SSTL135',
-    'SSTL15':  'DIFF_SSTL15',
+    'SSTL15': 'DIFF_SSTL15',
 }
 
+VREF_ALLOWED = [
+    'SSTL135',
+    'SSTL15',
+]
+
 
 def gen_iosettings():
     """
@@ -145,6 +150,9 @@ def run():
         region_data = []
         for region in sorted(list(iob_sites.keys())):
 
+            # Get IO bank. All sites from a clock region have the same one.
+            bank = iob_sites[region][0]["bank"]
+
             # Get IO settings
             try:
                 iosettings = next(iosettings_gen)
@@ -190,6 +198,7 @@ def run():
             region_data.append(
                 {
                     "region": region,
+                    "bank": bank,
                     "iosettings": iosettings,
                     "unused_sites": unused_sites,
                     "input": used_sites[0:2],
@@ -236,6 +245,9 @@ module top (
             if slew is not None:
                 obuf_param_str += ", .SLEW(\"{}\")".format(slew)
 
+            bank = data["bank"]
+            vref = "0.75"  # FIXME: Maybe loop over VREFs too ?
+
             keys = {
                 "region": data["region"],
                 "ibuf_0_loc": data["input"][0],
@@ -266,6 +278,11 @@ module top (
                 out_idx += 2
                 ino_idx += 1
 
+            # Set VREF if necessary
+            if iostandard in VREF_ALLOWED:
+                tcl += "set_property INTERNAL_VREF {} [get_iobanks {}]\n".format(
+                    vref, bank)
+
             # Single ended
             if not is_diff: