diff --git a/fuzzers/025-bram-config/generate.py b/fuzzers/025-bram-config/generate.py
index 34802ad8..ee1d062e 100644
--- a/fuzzers/025-bram-config/generate.py
+++ b/fuzzers/025-bram-config/generate.py
@@ -50,6 +50,7 @@ def isinv_tags(segmk, ps, site, actual_ps):
 
         segmk.add_site_tag(site, tagname, tag)
 
+
 def bus_tags(segmk, ps, site):
     for param in ("DOA_REG", "DOB_REG"):
         segmk.add_site_tag(site, param, verilog.parsei(ps[param]))
@@ -98,18 +99,21 @@ def write_mode_tags(segmk, ps, site):
         segmk.add_site_tag(
             site, '%s_NO_CHANGE' % (param), set_val == "NO_CHANGE")
 
+
 def write_rstreg_priority(segmk, ps, site):
     for param in ["RSTREG_PRIORITY_A", "RSTREG_PRIORITY_B"]:
         set_val = verilog.unquote(ps[param])
         for opt in ["RSTREG", "REGCE"]:
-            segmk.add_site_tag(site, "{}_{}".format(param, opt),
-                    set_val == opt)
+            segmk.add_site_tag(
+                site, "{}_{}".format(param, opt), set_val == opt)
+
 
 def write_rdaddr_collision(segmk, ps, site):
     for opt in ["DELAYED_WRITE", "PERFORMANCE"]:
         set_val = verilog.unquote(ps['RDADDR_COLLISION_HWCONFIG'])
-        segmk.add_site_tag(site, "RDADDR_COLLISION_HWCONFIG_{}".format(opt),
-                set_val == opt)
+        segmk.add_site_tag(
+            site, "RDADDR_COLLISION_HWCONFIG_{}".format(opt), set_val == opt)
+
 
 def run():
 
diff --git a/fuzzers/025-bram-config/top.py b/fuzzers/025-bram-config/top.py
index 3a1cba28..6ad6b695 100644
--- a/fuzzers/025-bram-config/top.py
+++ b/fuzzers/025-bram-config/top.py
@@ -36,6 +36,52 @@ def gen_brams():
         yield ('RAMB18E1', site)
 
 
+def place_bram18(site, loci):
+    ports = {
+        'clk': 'clk',
+        'din': 'din[  %d +: 8]' % (8 * loci, ),
+        'dout': 'dout[  %d +: 8]' % (8 * loci, ),
+    }
+
+    write_modes = ["WRITE_FIRST", "READ_FIRST", "NO_CHANGE"]
+    collisions = ["DELAYED_WRITE", "PERFORMANCE"]
+    priorities = ["RSTREG", "REGCE"]
+
+    # Datasheet says 72 is legal in some cases, but think its a copy paste error from BRAM36
+    # also 0 and 36 aren't real sizes
+    # Bias choice to 18 as its needed to solve certain bits quickly
+    widths = [1, 2, 4, 9, 18, 18, 18, 18]
+    params = {
+        'LOC': verilog.quote(site),
+        'IS_CLKARDCLK_INVERTED': vrandbit(),
+        'IS_CLKBWRCLK_INVERTED': vrandbit(),
+        'IS_ENARDEN_INVERTED': vrandbit(),
+        'IS_ENBWREN_INVERTED': vrandbit(),
+        'IS_RSTRAMARSTRAM_INVERTED': vrandbit(),
+        'IS_RSTRAMB_INVERTED': vrandbit(),
+        'IS_RSTREGARSTREG_INVERTED': vrandbit(),
+        'IS_RSTREGB_INVERTED': vrandbit(),
+        'RAM_MODE': '"TDP"',
+        'WRITE_MODE_A': verilog.quote(random.choice(write_modes)),
+        'WRITE_MODE_B': verilog.quote(random.choice(write_modes)),
+        "DOA_REG": vrandbit(),
+        "DOB_REG": vrandbit(),
+        "SRVAL_A": vrandbits(18),
+        "SRVAL_B": vrandbits(18),
+        "INIT_A": vrandbits(18),
+        "INIT_B": vrandbits(18),
+        "READ_WIDTH_A": random.choice(widths),
+        "READ_WIDTH_B": random.choice(widths),
+        "WRITE_WIDTH_A": random.choice(widths),
+        "WRITE_WIDTH_B": random.choice(widths),
+        "RDADDR_COLLISION_HWCONFIG": verilog.quote(random.choice(collisions)),
+        "RSTREG_PRIORITY_A": verilog.quote(random.choice(priorities)),
+        "RSTREG_PRIORITY_B": verilog.quote(random.choice(priorities)),
+    }
+
+    return ('my_RAMB18E1', ports, params)
+
+
 def main():
     brams = list(gen_brams())
     DUTN = len(brams)
@@ -51,56 +97,10 @@ def main():
         (DIN_N - 1, DOUT_N - 1))
 
     for loci, (site_type, site) in enumerate(brams):
-
-        def place_bram18():
-            ports = {
-                'clk': 'clk',
-                'din': 'din[  %d +: 8]' % (8 * loci, ),
-                'dout': 'dout[  %d +: 8]' % (8 * loci, ),
-            }
-
-            write_modes = ["WRITE_FIRST", "READ_FIRST", "NO_CHANGE"]
-            collisions = ["DELAYED_WRITE", "PERFORMANCE"]
-            priorities = ["RSTREG", "REGCE"]
-
-            # Datasheet says 72 is legal in some cases, but think its a copy paste error from BRAM36
-            # also 0 and 36 aren't real sizes
-            # Bias choice to 18 as its needed to solve certain bits quickly
-            widths = [1, 2, 4, 9, 18, 18, 18, 18]
-            params = {
-                'LOC': verilog.quote(site),
-                'IS_CLKARDCLK_INVERTED': vrandbit(),
-                'IS_CLKBWRCLK_INVERTED': vrandbit(),
-                'IS_ENARDEN_INVERTED': vrandbit(),
-                'IS_ENBWREN_INVERTED': vrandbit(),
-                'IS_RSTRAMARSTRAM_INVERTED': vrandbit(),
-                'IS_RSTRAMB_INVERTED': vrandbit(),
-                'IS_RSTREGARSTREG_INVERTED': vrandbit(),
-                'IS_RSTREGB_INVERTED': vrandbit(),
-                'RAM_MODE': '"TDP"',
-                'WRITE_MODE_A': verilog.quote(random.choice(write_modes)),
-                'WRITE_MODE_B': verilog.quote(random.choice(write_modes)),
-                "DOA_REG": vrandbit(),
-                "DOB_REG": vrandbit(),
-                "SRVAL_A": vrandbits(18),
-                "SRVAL_B": vrandbits(18),
-                "INIT_A": vrandbits(18),
-                "INIT_B": vrandbits(18),
-                "READ_WIDTH_A": random.choice(widths),
-                "READ_WIDTH_B": random.choice(widths),
-                "WRITE_WIDTH_A": random.choice(widths),
-                "WRITE_WIDTH_B": random.choice(widths),
-                "RDADDR_COLLISION_HWCONFIG": verilog.quote(random.choice(collisions)),
-                "RSTREG_PRIORITY_A": verilog.quote(random.choice(priorities)),
-                "RSTREG_PRIORITY_B": verilog.quote(random.choice(priorities)),
-            }
-
-            return ('my_RAMB18E1', ports, params)
-
         modname, ports, params = {
             'RAMB18E1': place_bram18,
             #'RAMBFIFO36E1': place_bram36,
-        }[site_type]()
+        }[site_type](site, loci)
 
         verilog.instance(modname, 'inst_%u' % loci, ports, params=params)
 
@@ -213,5 +213,6 @@ def main():
     endmodule
     ''')
 
+
 if __name__ == "__main__":
     main()