From 1c63972bd2730e5ef139970bfc45e9a5f4445ffb Mon Sep 17 00:00:00 2001 From: Dr Jonathan Richard Robert Kimmitt Date: Sat, 30 May 2026 16:02:48 +0100 Subject: [PATCH] 005-tilegrid: propagate SING bits for HP-only LIOB18 / LIOI columns propagate_IOB_SING and propagate_IOI_SING walk each IO column from a parent IOB/IOI tile down to the SING half-tiles at the column endpoints and alias the parent's CLB_IO_CLK bits into both halves (offset=0 for the bottom SING, offset=99 for the top SING). The parent-type allowlists were missing the HP-bank L-column types: propagate_IOB_SING: ["LIOB33", "RIOB33", "RIOB18"] # LIOB18 missing propagate_IOI_SING: ["LIOI3", "RIOI3", "RIOI"] # LIOI missing On artix7 / kintex7 the leftmost HP column doesn't exist as a parent LIOB18 / LIOI in the tilegrid, so the omission was latent. On virtex7 VX (HP-only) both LIOB18 and RIOB18 columns exist, and the gap surfaces as half the SING IOB / IOI tiles (the L-column ones) having empty bits in tilegrid.json: LIOB18_SING: 0/14 with bits -> 14/14 RIOB18_SING: 14/14 (unchanged) LIOI_SING: 0/14 with bits -> 14/14 RIOI_SING: 14/14 (unchanged) Add the missing types. Cross-checked against iob18's own measured parent bases (e.g. LIOB18_X81Y2 -> 0x00421000 lines up with the propagated LIOB18_SING_X81Y1 base 0x00421000 offset=0 and Y51 offset=99). Also de-wire the iob18_sing sub-fuzzer from TILEGRID_TDB_DEPENDENCIES: SING tiles aren't independently addressed (they share the parent IOB's base with a word-offset variant), and half of iob18_sing's tdb entries land at an unaligned frame (offset+1) that add_tdb's frame-alignment assertion would reject anyway. The build rule stays so the fuzzer can be invoked manually as a Vivado-measurement guard for the propagation. Co-Authored-By: Claude Opus 4.7 --- fuzzers/005-tilegrid/Makefile | 7 ++++++- fuzzers/005-tilegrid/generate_full.py | 5 +++-- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/fuzzers/005-tilegrid/Makefile b/fuzzers/005-tilegrid/Makefile index 93dacc98..800b2ba6 100644 --- a/fuzzers/005-tilegrid/Makefile +++ b/fuzzers/005-tilegrid/Makefile @@ -72,7 +72,12 @@ endif ifeq (${HAS_HIGH_PERFORMANCE_BANKS}, 1) TILEGRID_TDB_DEPENDENCIES += iob18/$(BUILD_FOLDER)/segbits_tilegrid.tdb TILEGRID_TDB_DEPENDENCIES += iob18_int/$(BUILD_FOLDER)/segbits_tilegrid.tdb -TILEGRID_TDB_DEPENDENCIES += iob18_sing/$(BUILD_FOLDER)/segbits_tilegrid.tdb +# iob18_sing is intentionally NOT a tilegrid dependency: SING tiles inherit +# their base address from the parent IOB18 column via propagate_IOB_SING in +# generate_full.py, not via direct measurement. The iob18_sing rule below is +# kept so the build can still be invoked manually as a Vivado-measurement +# guard (its tdb half-aligns at offset+1 - exactly what propagate_IOB_SING's +# top-tile alias models with offset=99). TILEGRID_TDB_DEPENDENCIES += ioi18/$(BUILD_FOLDER)/segbits_tilegrid.tdb # GTX transceiver fuzzers. Kintex-7 only: the xc7vx485t-ffg1761 package used for # virtex7 bonds only ~7 of its 14 GTX quads, so the unbonded GTX_COMMON tiles diff --git a/fuzzers/005-tilegrid/generate_full.py b/fuzzers/005-tilegrid/generate_full.py index cec07ddf..fe3355bf 100644 --- a/fuzzers/005-tilegrid/generate_full.py +++ b/fuzzers/005-tilegrid/generate_full.py @@ -369,7 +369,8 @@ def propagate_IOB_SING(database, tiles_by_grid): if tile in seen_iobs: continue - if database[tile]["type"] not in ["LIOB33", "RIOB33", "RIOB18"]: + if database[tile]["type"] not in ["LIOB33", "RIOB33", "LIOB18", + "RIOB18"]: continue while True: @@ -439,7 +440,7 @@ def propagate_IOI_SING(database, tiles_by_grid): if tile in seen_iois: continue - if database[tile]["type"] not in ["LIOI3", "RIOI3", "RIOI"]: + if database[tile]["type"] not in ["LIOI3", "RIOI3", "LIOI", "RIOI"]: continue while True: