diff --git a/minitests/roi_harness/README.txt b/minitests/roi_harness/README.txt
index e2f90c13..2f24f2da 100644
--- a/minitests/roi_harness/README.txt
+++ b/minitests/roi_harness/README.txt
@@ -12,8 +12,8 @@ Its expected the end user will rip out everything inside the ROI
 To target Arty A7 you should source the artix DB environment script then source arty.sh
 
 To build the baseline harness:
-make
-
-To build a sample design using the harness:
-XRAY_ROIV=roi_inv.v make
+./runme.sh
 
+To build a sample Vivado design using the harness:
+XRAY_ROIV=roi_inv.v XRAY_FIXED_XDC=out_xc7a35tcpg236-1_BASYS3-SWBUT_roi_basev/fixed_noclk.xdc ./runme.sh
+Note: this was intended for verification only and not as an end user flow (they should use SymbiFlow)
diff --git a/minitests/roi_harness/runme.sh b/minitests/roi_harness/runme.sh
old mode 100644
new mode 100755
index a15ab84e..4fa2c200
--- a/minitests/roi_harness/runme.sh
+++ b/minitests/roi_harness/runme.sh
@@ -10,4 +10,11 @@ ${XRAY_BITREAD} -F $XRAY_ROI_FRAMES -o design.bits -z -y design.bit
 ${XRAY_SEGPRINT} -zd design.bits >design.segp
 ${XRAY_DIR}/tools/segprint2fasm.py design.segp design.fasm
 ${XRAY_DIR}/tools/fasm2frame.py design.fasm design.frm
+# Hack to get around weird clock error related to clk net not found
+# Remove following lines:
+#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
+#set_property FIXED_ROUTE { { CLK_BUFG_BUFGCTRL0_O CLK_BUFG_CK_GCLK0 ... CLK_L1 CLBLM_M_CLK }  } [get_nets clk_net]
+if [ -f fixed.xdc ] ; then
+    cat fixed.xdc |fgrep -v 'CLOCK_DEDICATED_ROUTE FALSE' |fgrep -v 'set_property FIXED_ROUTE { { CLK_BUFG_BUFGCTRL0_O' >fixed_noclk.xdc
+fi
 popd
diff --git a/minitests/roi_harness/runme.tcl b/minitests/roi_harness/runme.tcl
index 58e4d876..43f43748 100644
--- a/minitests/roi_harness/runme.tcl
+++ b/minitests/roi_harness/runme.tcl
@@ -60,11 +60,20 @@ source ../../utils/utils.tcl
 create_project -force -part $::env(XRAY_PART) design design
 read_verilog top.v
 read_verilog $roiv
+set fixed_xdc ""
+if { [info exists ::env(XRAY_FIXED_XDC) ] } {
+    set fixed_xdc "$::env(XRAY_FIXED_XDC)"
+}
+
 # added flatten_hierarchy
 # dout_shr was getting folded into the pblock
 # synth_design -top top -flatten_hierarchy none -no_lc -keep_equivalent_registers -resource_sharing off
 synth_design -top top -flatten_hierarchy none -verilog_define DIN_N=$DIN_N -verilog_define DOUT_N=$DOUT_N
 
+if {$fixed_xdc ne ""} {
+    read_xdc $fixed_xdc
+}
+
 # Map of top level net names to IOB pin names
 array set net2pin [list]
 
@@ -180,19 +189,22 @@ foreach {net pin} [array get net2pin] {
     set_property -dict "PACKAGE_PIN $pin IOSTANDARD LVCMOS33" [get_ports $net]
 }
 
-create_pblock roi
-set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi]
-add_cells_to_pblock [get_pblocks roi] [get_cells roi]
-resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
+if {$fixed_xdc eq ""} {
+    create_pblock roi
+    set_property EXCLUDE_PLACEMENT 1 [get_pblocks roi]
+    set_property CONTAIN_ROUTING true [get_pblocks roi]
+    set_property DONT_TOUCH true [get_cells roi]
+    add_cells_to_pblock [get_pblocks roi] [get_cells roi]
+    resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)"
 
-set_property CFGBVS VCCO [current_design]
-set_property CONFIG_VOLTAGE 3.3 [current_design]
-set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
+    set_property CFGBVS VCCO [current_design]
+    set_property CONFIG_VOLTAGE 3.3 [current_design]
+    set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
 
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
-
-#write_checkpoint -force synth.dcp
+    set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF]
 
+    #write_checkpoint -force $outdir/synth.dcp
+}
 
 
 proc loc_roi_clk_left {ff_x ff_y} {
@@ -257,7 +269,7 @@ proc net_bank_left {net} {
 }
 
 # Manual placement
-if {1} {
+if {$fixed_xdc eq ""} {
     set x $X_BASE
 
     # Place ROI clock right after inputs
@@ -286,7 +298,7 @@ if {1} {
 }
 
 place_design
-#write_checkpoint -force placed.dcp
+#write_checkpoint -force $outdir/placed.dcp
 
 # Version with more error checking for missing end node
 # Will do best effort in this case
@@ -341,7 +353,7 @@ proc route_via2 {net nodes} {
 set fp [open "design.txt" w]
 puts $fp "name node pin"
 # Manual routing
-if {1} {
+if {$fixed_xdc eq ""} {
     set x $X_BASE
 
     # No routing strictly needed for clk
@@ -406,6 +418,15 @@ close $fp
 puts "routing design"
 route_design
 
+# Don't set for user designs
+# Makes things easier to debug
+if {$fixed_xdc eq ""} {
+    set_property IS_ROUTE_FIXED 1 [get_nets -hierarchical]
+    #set_property IS_LOC_FIXED 1 [get_cells -hierarchical]
+    #set_property IS_BEL_FIXED 1 [get_cells -hierarchical]
+    write_xdc -force $outdir/fixed.xdc
+}
+
 write_checkpoint -force $outdir/design.dcp
 set_property BITSTREAM.GENERAL.DEBUGBITSTREAM YES [current_design]
 write_bitstream -force $outdir/design.bit
diff --git a/minitests/roi_harness/top.v b/minitests/roi_harness/top.v
index 997231a9..2e8852ad 100644
--- a/minitests/roi_harness/top.v
+++ b/minitests/roi_harness/top.v
@@ -3,7 +3,7 @@
 `include "defines.v"
 
 module top(input wire clk,
-        input [DIN_N-1:0] din, output [DOUT_N-1:0] dout);
+        inout wire [DIN_N-1:0] din, output wire [DOUT_N-1:0] dout);
     parameter DIN_N = `DIN_N;
     parameter DOUT_N = `DOUT_N;