From 18acada7136adf065cad4eb1bc0a79133542380b Mon Sep 17 00:00:00 2001 From: Tomasz Michalak Date: Wed, 11 Dec 2019 11:14:51 +0100 Subject: [PATCH] minitests: Add min litex with DDR test Signed-off-by: Tomasz Michalak --- .../litex/min_ddr/arty/scripts/min_arty.py | 99 + .../litex/min_ddr/arty/src.vivado/Makefile | 33 + .../litex/min_ddr/arty/src.vivado/top.tcl | 27 + .../litex/min_ddr/arty/src.vivado/top.xdc | 230 + .../litex/min_ddr/arty/src.yosys/Makefile | 51 + .../litex/min_ddr/arty/src.yosys/mem.init | 1 + .../litex/min_ddr/arty/src.yosys/mem_1.init | 1 + .../arty/src.yosys/missing_bit_report.py | 81 + .../litex/min_ddr/arty/src.yosys/synth.ys | 3 + .../litex/min_ddr/arty/src.yosys/top.tcl | 60 + .../litex/min_ddr/arty/src.yosys/top.xdc | 230 + .../min_ddr/arty/verilog/VexRiscv_Lite.v | 4819 ++++++ minitests/litex/min_ddr/arty/verilog/mem.init | 4723 ++++++ .../litex/min_ddr/arty/verilog/mem_1.init | 0 minitests/litex/min_ddr/arty/verilog/top.v | 12368 ++++++++++++++++ 15 files changed, 22726 insertions(+) create mode 100755 minitests/litex/min_ddr/arty/scripts/min_arty.py create mode 100644 minitests/litex/min_ddr/arty/src.vivado/Makefile create mode 100644 minitests/litex/min_ddr/arty/src.vivado/top.tcl create mode 100644 minitests/litex/min_ddr/arty/src.vivado/top.xdc create mode 100644 minitests/litex/min_ddr/arty/src.yosys/Makefile create mode 120000 minitests/litex/min_ddr/arty/src.yosys/mem.init create mode 120000 minitests/litex/min_ddr/arty/src.yosys/mem_1.init create mode 100644 minitests/litex/min_ddr/arty/src.yosys/missing_bit_report.py create mode 100644 minitests/litex/min_ddr/arty/src.yosys/synth.ys create mode 100644 minitests/litex/min_ddr/arty/src.yosys/top.tcl create mode 100644 minitests/litex/min_ddr/arty/src.yosys/top.xdc create mode 100644 minitests/litex/min_ddr/arty/verilog/VexRiscv_Lite.v create mode 100644 minitests/litex/min_ddr/arty/verilog/mem.init create mode 100644 minitests/litex/min_ddr/arty/verilog/mem_1.init create mode 100644 minitests/litex/min_ddr/arty/verilog/top.v diff --git a/minitests/litex/min_ddr/arty/scripts/min_arty.py b/minitests/litex/min_ddr/arty/scripts/min_arty.py new file mode 100755 index 00000000..7ec6191d --- /dev/null +++ b/minitests/litex/min_ddr/arty/scripts/min_arty.py @@ -0,0 +1,99 @@ +#!/usr/bin/env python3 + +# This file is Copyright (c) 2015-2019 Florent Kermarrec +# License: BSD + +import argparse + +from migen import * + +from litex.boards.platforms import arty +from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict + +from litex.soc.cores.clock import * +from litex.soc.integration.soc_sdram import * +from litex.soc.integration.builder import * + +from litedram.modules import MT41K128M16 +from litedram.phy import s7ddrphy + +# CRG ---------------------------------------------------------------------------------------------- + + +class _CRG(Module): + def __init__(self, platform, sys_clk_freq): + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) + self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) + self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_eth = ClockDomain() + + # # # + pll_clkin = Signal() + self.specials += Instance( + "BUFG", i_I=platform.request("clk100"), o_O=pll_clkin) + self.submodules.pll = pll = S7PLL(speedgrade=-1) + self.comb += pll.reset.eq(~platform.request("cpu_reset")) + pll.register_clkin(pll_clkin, 100e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys4x, 4 * sys_clk_freq) + pll.create_clkout(self.cd_sys4x_dqs, 4 * sys_clk_freq, phase=90) + pll.create_clkout(self.cd_clk200, 200e6) + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) + + +# BaseSoC ------------------------------------------------------------------------------------------ + + +class MinSoC(SoCSDRAM): + def __init__( + self, sys_clk_freq=int(50e6), integrated_rom_size=0x8000, + **kwargs): + platform = arty.Platform() + + # SoCSDRAM --------------------------------------------------------------------------------- + SoCSDRAM.__init__( + self, + platform, + clk_freq=sys_clk_freq, + integrated_rom_size=integrated_rom_size, + integrated_sram_size=0x8000, + cpu_variant="lite", + **kwargs) + + # CRG -------------------------------------------------------------------------------------- + self.submodules.crg = _CRG(platform, sys_clk_freq) + + # DDR3 SDRAM ------------------------------------------------------------------------------- + if not self.integrated_main_ram_size: + self.submodules.ddrphy = s7ddrphy.A7DDRPHY( + platform.request("ddram"), + memtype="DDR3", + nphases=4, + sys_clk_freq=sys_clk_freq) + self.add_csr("ddrphy") + sdram_module = MT41K128M16(sys_clk_freq, "1:4") + self.register_sdram( + self.ddrphy, + geom_settings=sdram_module.geom_settings, + timing_settings=sdram_module.timing_settings) + + +# Build -------------------------------------------------------------------------------------------- + + +def main(): + parser = argparse.ArgumentParser(description="LiteX SoC on Arty") + builder_args(parser) + soc_sdram_args(parser) + vivado_build_args(parser) + args = parser.parse_args() + + cls = MinSoC + soc = cls(**soc_sdram_argdict(args)) + builder = Builder(soc, **builder_argdict(args)) + builder.build(**vivado_build_argdict(args)) + + +if __name__ == "__main__": + main() diff --git a/minitests/litex/min_ddr/arty/src.vivado/Makefile b/minitests/litex/min_ddr/arty/src.vivado/Makefile new file mode 100644 index 00000000..d7d802a6 --- /dev/null +++ b/minitests/litex/min_ddr/arty/src.vivado/Makefile @@ -0,0 +1,33 @@ +PART = xc7a35tcsg324-1 +BIT2FASM_ARGS = --part "$(XRAY_DIR)/database/artix7/$(PART)" --verbose +SOURCES = ../verilog/mem.init ../verilog/mem_1.init ../verilog/top.v ../verilog/VexRiscv_Lite.v + +all: top.fasm top.bits segprint.log + +clean: + @rm -f *.bit + @rm -f *.bin + @rm -f *.bits + @rm -f *.fasm + @rm -f *.log + @rm -rf build + +.PHONY: all clean + +top.bit: $(VIVADO) $(SOURCES) top.xdc top.tcl + mkdir -p build + cd build && $(XRAY_VIVADO) -mode batch -source ../top.tcl -nojournal -tempDir build -log vivado.log -verbose + cp build/*.bit ./ + +top.fasm: top.bit + PYTHONPATH="$(XRAY_DIR):$(XRAY_DIR)/utils:$(XRAY_DIR)/third_party/fasm" \ + PATH="$(XRAY_DIR)/build/tools:$(PATH)" \ + $(XRAY_BIT2FASM) $(BIT2FASM_ARGS) \ + top.bit >top.fasm \ + || (rm -f top.fasm && exit 1) + +top.bits: top.bit + $(XRAY_BITREAD) -part_file $(XRAY_DIR)/database/artix7/$(PART).yaml -o top.bits -z -y top.bit + +segprint.log: top.bits + $(XRAY_SEGPRINT) -z -D -b top.bits > segprint.log diff --git a/minitests/litex/min_ddr/arty/src.vivado/top.tcl b/minitests/litex/min_ddr/arty/src.vivado/top.tcl new file mode 100644 index 00000000..26bd28e2 --- /dev/null +++ b/minitests/litex/min_ddr/arty/src.vivado/top.tcl @@ -0,0 +1,27 @@ +create_project -force -name top -part xc7a35ticsg324-1L +add_files {../../verilog/top.v} +add_files {../../verilog/VexRiscv_Lite.v} +read_xdc ../top.xdc +synth_design -top top -part xc7a35ticsg324-1L +report_timing_summary -file top_timing_synth.rpt +report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt +report_utilization -file top_utilization_synth.rpt +opt_design +place_design +report_utilization -hierarchical -file top_utilization_hierarchical_place.rpt +report_utilization -file top_utilization_place.rpt +report_io -file top_io.rpt +report_control_sets -verbose -file top_control_sets.rpt +report_clock_utilization -file top_clock_utilization.rpt +route_design +phys_opt_design +report_timing_summary -no_header -no_detailed_paths +write_checkpoint -force top_route.dcp +report_route_status -file top_route_status.rpt +report_drc -file top_drc.rpt +report_timing_summary -datasheet -max_paths 10 -file top_timing.rpt +report_power -file top_power.rpt +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +write_bitstream -force top.bit +write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit "up 0x0 top.bit" -file top.bin +quit diff --git a/minitests/litex/min_ddr/arty/src.vivado/top.xdc b/minitests/litex/min_ddr/arty/src.vivado/top.xdc new file mode 100644 index 00000000..7de3d702 --- /dev/null +++ b/minitests/litex/min_ddr/arty/src.vivado/top.xdc @@ -0,0 +1,230 @@ + ## serial:0.tx +set_property LOC D10 [get_ports serial_tx] +set_property IOSTANDARD LVCMOS33 [get_ports serial_tx] + ## serial:0.rx +set_property LOC A9 [get_ports serial_rx] +set_property IOSTANDARD LVCMOS33 [get_ports serial_rx] + ## clk100:0 +set_property LOC E3 [get_ports clk100] +set_property IOSTANDARD LVCMOS33 [get_ports clk100] + ## cpu_reset:0 +set_property LOC C2 [get_ports cpu_reset] +set_property IOSTANDARD LVCMOS33 [get_ports cpu_reset] + ## ddram:0.a +set_property LOC R2 [get_ports ddram_a[0]] +set_property SLEW FAST [get_ports ddram_a[0]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[0]] + ## ddram:0.a +set_property LOC M6 [get_ports ddram_a[1]] +set_property SLEW FAST [get_ports ddram_a[1]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[1]] + ## ddram:0.a +set_property LOC N4 [get_ports ddram_a[2]] +set_property SLEW FAST [get_ports ddram_a[2]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[2]] + ## ddram:0.a +set_property LOC T1 [get_ports ddram_a[3]] +set_property SLEW FAST [get_ports ddram_a[3]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[3]] + ## ddram:0.a +set_property LOC N6 [get_ports ddram_a[4]] +set_property SLEW FAST [get_ports ddram_a[4]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[4]] + ## ddram:0.a +set_property LOC R7 [get_ports ddram_a[5]] +set_property SLEW FAST [get_ports ddram_a[5]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[5]] + ## ddram:0.a +set_property LOC V6 [get_ports ddram_a[6]] +set_property SLEW FAST [get_ports ddram_a[6]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[6]] + ## ddram:0.a +set_property LOC U7 [get_ports ddram_a[7]] +set_property SLEW FAST [get_ports ddram_a[7]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[7]] + ## ddram:0.a +set_property LOC R8 [get_ports ddram_a[8]] +set_property SLEW FAST [get_ports ddram_a[8]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[8]] + ## ddram:0.a +set_property LOC V7 [get_ports ddram_a[9]] +set_property SLEW FAST [get_ports ddram_a[9]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[9]] + ## ddram:0.a +set_property LOC R6 [get_ports ddram_a[10]] +set_property SLEW FAST [get_ports ddram_a[10]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[10]] + ## ddram:0.a +set_property LOC U6 [get_ports ddram_a[11]] +set_property SLEW FAST [get_ports ddram_a[11]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[11]] + ## ddram:0.a +set_property LOC T6 [get_ports ddram_a[12]] +set_property SLEW FAST [get_ports ddram_a[12]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[12]] + ## ddram:0.a +set_property LOC T8 [get_ports ddram_a[13]] +set_property SLEW FAST [get_ports ddram_a[13]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[13]] + ## ddram:0.ba +set_property LOC R1 [get_ports ddram_ba[0]] +set_property SLEW FAST [get_ports ddram_ba[0]] +set_property IOSTANDARD SSTL135 [get_ports ddram_ba[0]] + ## ddram:0.ba +set_property LOC P4 [get_ports ddram_ba[1]] +set_property SLEW FAST [get_ports ddram_ba[1]] +set_property IOSTANDARD SSTL135 [get_ports ddram_ba[1]] + ## ddram:0.ba +set_property LOC P2 [get_ports ddram_ba[2]] +set_property SLEW FAST [get_ports ddram_ba[2]] +set_property IOSTANDARD SSTL135 [get_ports ddram_ba[2]] + ## ddram:0.ras_n +set_property LOC P3 [get_ports ddram_ras_n] +set_property SLEW FAST [get_ports ddram_ras_n] +set_property IOSTANDARD SSTL135 [get_ports ddram_ras_n] + ## ddram:0.cas_n +set_property LOC M4 [get_ports ddram_cas_n] +set_property SLEW FAST [get_ports ddram_cas_n] +set_property IOSTANDARD SSTL135 [get_ports ddram_cas_n] + ## ddram:0.we_n +set_property LOC P5 [get_ports ddram_we_n] +set_property SLEW FAST [get_ports ddram_we_n] +set_property IOSTANDARD SSTL135 [get_ports ddram_we_n] + ## ddram:0.cs_n +set_property LOC U8 [get_ports ddram_cs_n] +set_property SLEW FAST [get_ports ddram_cs_n] +set_property IOSTANDARD SSTL135 [get_ports ddram_cs_n] + ## ddram:0.dm +set_property LOC L1 [get_ports ddram_dm[0]] +set_property SLEW FAST [get_ports ddram_dm[0]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dm[0]] + ## ddram:0.dm +set_property LOC U1 [get_ports ddram_dm[1]] +set_property SLEW FAST [get_ports ddram_dm[1]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dm[1]] + ## ddram:0.dq +set_property LOC K5 [get_ports ddram_dq[0]] +set_property SLEW FAST [get_ports ddram_dq[0]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[0]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[0]] + ## ddram:0.dq +set_property LOC L3 [get_ports ddram_dq[1]] +set_property SLEW FAST [get_ports ddram_dq[1]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[1]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[1]] + ## ddram:0.dq +set_property LOC K3 [get_ports ddram_dq[2]] +set_property SLEW FAST [get_ports ddram_dq[2]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[2]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[2]] + ## ddram:0.dq +set_property LOC L6 [get_ports ddram_dq[3]] +set_property SLEW FAST [get_ports ddram_dq[3]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[3]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[3]] + ## ddram:0.dq +set_property LOC M3 [get_ports ddram_dq[4]] +set_property SLEW FAST [get_ports ddram_dq[4]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[4]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[4]] + ## ddram:0.dq +set_property LOC M1 [get_ports ddram_dq[5]] +set_property SLEW FAST [get_ports ddram_dq[5]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[5]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[5]] + ## ddram:0.dq +set_property LOC L4 [get_ports ddram_dq[6]] +set_property SLEW FAST [get_ports ddram_dq[6]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[6]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[6]] + ## ddram:0.dq +set_property LOC M2 [get_ports ddram_dq[7]] +set_property SLEW FAST [get_ports ddram_dq[7]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[7]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[7]] + ## ddram:0.dq +set_property LOC V4 [get_ports ddram_dq[8]] +set_property SLEW FAST [get_ports ddram_dq[8]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[8]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[8]] + ## ddram:0.dq +set_property LOC T5 [get_ports ddram_dq[9]] +set_property SLEW FAST [get_ports ddram_dq[9]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[9]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[9]] + ## ddram:0.dq +set_property LOC U4 [get_ports ddram_dq[10]] +set_property SLEW FAST [get_ports ddram_dq[10]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[10]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[10]] + ## ddram:0.dq +set_property LOC V5 [get_ports ddram_dq[11]] +set_property SLEW FAST [get_ports ddram_dq[11]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[11]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[11]] + ## ddram:0.dq +set_property LOC V1 [get_ports ddram_dq[12]] +set_property SLEW FAST [get_ports ddram_dq[12]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[12]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[12]] + ## ddram:0.dq +set_property LOC T3 [get_ports ddram_dq[13]] +set_property SLEW FAST [get_ports ddram_dq[13]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[13]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[13]] + ## ddram:0.dq +set_property LOC U3 [get_ports ddram_dq[14]] +set_property SLEW FAST [get_ports ddram_dq[14]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[14]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[14]] + ## ddram:0.dq +set_property LOC R3 [get_ports ddram_dq[15]] +set_property SLEW FAST [get_ports ddram_dq[15]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[15]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[15]] + ## ddram:0.dqs_p +set_property LOC N2 [get_ports ddram_dqs_p[0]] +set_property SLEW FAST [get_ports ddram_dqs_p[0]] +set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_p[0]] + ## ddram:0.dqs_p +set_property LOC U2 [get_ports ddram_dqs_p[1]] +set_property SLEW FAST [get_ports ddram_dqs_p[1]] +set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_p[1]] + ## ddram:0.dqs_n +set_property LOC N1 [get_ports ddram_dqs_n[0]] +set_property SLEW FAST [get_ports ddram_dqs_n[0]] +set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_n[0]] + ## ddram:0.dqs_n +set_property LOC V2 [get_ports ddram_dqs_n[1]] +set_property SLEW FAST [get_ports ddram_dqs_n[1]] +set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_n[1]] + ## ddram:0.clk_p +set_property LOC U9 [get_ports ddram_clk_p] +set_property SLEW FAST [get_ports ddram_clk_p] +set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_p] + ## ddram:0.clk_n +set_property LOC V9 [get_ports ddram_clk_n] +set_property SLEW FAST [get_ports ddram_clk_n] +set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_n] + ## ddram:0.cke +set_property LOC N5 [get_ports ddram_cke] +set_property SLEW FAST [get_ports ddram_cke] +set_property IOSTANDARD SSTL135 [get_ports ddram_cke] + ## ddram:0.odt +set_property LOC R5 [get_ports ddram_odt] +set_property SLEW FAST [get_ports ddram_odt] +set_property IOSTANDARD SSTL135 [get_ports ddram_odt] + ## ddram:0.reset_n +set_property LOC K6 [get_ports ddram_reset_n] +set_property SLEW FAST [get_ports ddram_reset_n] +set_property IOSTANDARD SSTL135 [get_ports ddram_reset_n] + +set_property INTERNAL_VREF 0.675 [get_iobanks 34] + +create_clock -name clk100 -period 10.0 [get_nets clk100] + +set_false_path -quiet -to [get_nets -quiet -filter {mr_ff == TRUE}] + +set_false_path -quiet -to [get_pins -quiet -filter {REF_PIN_NAME == PRE} -of [get_cells -quiet -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]] + +set_max_delay 2 -quiet -from [get_pins -quiet -filter {REF_PIN_NAME == Q} -of [get_cells -quiet -filter {ars_ff1 == TRUE}]] -to [get_pins -quiet -filter {REF_PIN_NAME == D} -of [get_cells -quiet -filter {ars_ff2 == TRUE}]] \ No newline at end of file diff --git a/minitests/litex/min_ddr/arty/src.yosys/Makefile b/minitests/litex/min_ddr/arty/src.yosys/Makefile new file mode 100644 index 00000000..059bb501 --- /dev/null +++ b/minitests/litex/min_ddr/arty/src.yosys/Makefile @@ -0,0 +1,51 @@ +export XRAY_PART = xc7a35tcsg324-1 +export XRAY_PART_YAML = $(XRAY_DATABASE_DIR)/$(XRAY_DATABASE)/$(XRAY_PART).yaml +YOSYS = $(XRAY_DIR)/third_party/yosys/yosys +SOURCES = ../verilog/mem.init ../verilog/mem_1.init ../verilog/top.v ../verilog/VexRiscv_Lite.v +PORT ?= /dev/ttyUSB1 + +all: top.f2b.bit + +clean: + @rm -f *.edif + @rm -f *.bit + @rm -f *.bin + @rm -f *.bits + @rm -f *.fasm + @rm -f *.frames + @rm -f *.log + @rm -rf build + +.PHONY: all clean + +$(YOSYS): + cd $(XRAY_DIR)/third_party/yosys && make config-gcc && make -j$(shell nproc) + +top.edif: $(YOSYS) synth.ys $(SOURCES) + $(YOSYS) -s synth.ys -l yosys.log + +top.bit: $(VIVADO) top.edif top.xdc top.tcl + mkdir -p build + cd build && $(XRAY_VIVADO) -mode batch -source ../top.tcl -nojournal -tempDir build -log vivado.log -verbose + python3 $(XRAY_DIR)/minitests/timing/clean_json5.py < build/iobuf_report.json5 > build/iobuf_report.json + cp build/*.bit ./ + +top.fasm: top.bit + $(XRAY_BIT2FASM) --verbose $< > $@ \ + || (rm -f top.fasm && exit 1) + +top.bits: top.bit + $(XRAY_BITREAD) -part_file $(XRAY_PART_YAML) -o top.bits -z -y top.bit + +segprint.log: top.bits + $(XRAY_SEGPRINT) -z -D -b top.bits > segprint.log + +top.frames: top.fasm + $(XRAY_FASM2FRAMES) $< $@ + +top.f2b.bit: top.frames + $(XRAY_DIR)/build/tools/xc7frames2bit --output_file $@ --part_name $(XRAY_PART) --part_file $(XRAY_PART_YAML) --frm_file $< + +program: top.f2b.bit + xc3sprog -c nexys4 top.f2b.bit + diff --git a/minitests/litex/min_ddr/arty/src.yosys/mem.init b/minitests/litex/min_ddr/arty/src.yosys/mem.init new file mode 120000 index 00000000..2e1a8e86 --- /dev/null +++ b/minitests/litex/min_ddr/arty/src.yosys/mem.init @@ -0,0 +1 @@ +../verilog/mem.init \ No newline at end of file diff --git a/minitests/litex/min_ddr/arty/src.yosys/mem_1.init b/minitests/litex/min_ddr/arty/src.yosys/mem_1.init new file mode 120000 index 00000000..0b2da260 --- /dev/null +++ b/minitests/litex/min_ddr/arty/src.yosys/mem_1.init @@ -0,0 +1 @@ +../verilog/mem_1.init \ No newline at end of file diff --git a/minitests/litex/min_ddr/arty/src.yosys/missing_bit_report.py b/minitests/litex/min_ddr/arty/src.yosys/missing_bit_report.py new file mode 100644 index 00000000..4d4ec472 --- /dev/null +++ b/minitests/litex/min_ddr/arty/src.yosys/missing_bit_report.py @@ -0,0 +1,81 @@ +""" Generates a missing feature/bit report for LiteX design. + +This script is fairly fragile, because it depends on the specific observation +that all of the remaining bits appear to either belong to HCLK_IOI or IOI3 +tiles. A more general version of this script could be created, but that was +not the point of this script. + +""" +from fasm import parse_fasm_filename + + +def main(): + fasm_file = 'top.fasm' + fasm_model = list(parse_fasm_filename(fasm_file)) + + unknown_bits = { + 'HCLK_IOI': {}, + 'IOI3': {}, + } + + total_unknown = 0 + for l in fasm_model: + if l.annotations is None: + continue + + annotations = {} + for annotation in l.annotations: + annotations[annotation.name] = annotation.value + + if 'unknown_bit' not in annotations: + continue + + total_unknown += 1 + + frame, word, bit = annotations['unknown_bit'].split('_') + + frame = int(frame, 16) + word = int(word) + bit = int(bit) + + frame_offset = frame % 0x80 + base_frame = frame - frame_offset + + # All remaining LiteX bits appear to be in this one IO bank, so limit + # the tool this this one IO bank. + assert base_frame == 0x00401580, hex(frame) + + SIZE = 4 + INITIAL_OFFSET = -2 + + if word == 50: + group = 'HCLK_IOI' + offset = 45 + elif word < 50: + group = 'IOI3' + offset = ((word - INITIAL_OFFSET) // SIZE) * SIZE + INITIAL_OFFSET + else: + group = 'IOI3' + word -= 1 + offset = ((word - INITIAL_OFFSET) // SIZE) * SIZE + INITIAL_OFFSET + offset += 1 + word += 1 + + bit = '{}_{:02d}'.format( + frame_offset, + (word - offset) * 32 + bit, + ) + + if bit not in unknown_bits[group]: + unknown_bits[group][bit] = 0 + unknown_bits[group][bit] += 1 + + print('Total unknown bits: {}'.format(total_unknown)) + for group in unknown_bits: + print('Group {} (count = {}):'.format(group, len(unknown_bits[group]))) + for bit in sorted(unknown_bits[group]): + print(' {} (count = {})'.format(bit, unknown_bits[group][bit])) + + +if __name__ == "__main__": + main() diff --git a/minitests/litex/min_ddr/arty/src.yosys/synth.ys b/minitests/litex/min_ddr/arty/src.yosys/synth.ys new file mode 100644 index 00000000..30b434e6 --- /dev/null +++ b/minitests/litex/min_ddr/arty/src.yosys/synth.ys @@ -0,0 +1,3 @@ +read_verilog ../verilog/top.v +read_verilog ../verilog/VexRiscv_Lite.v +synth_xilinx -edif top.edif diff --git a/minitests/litex/min_ddr/arty/src.yosys/top.tcl b/minitests/litex/min_ddr/arty/src.yosys/top.tcl new file mode 100644 index 00000000..5537f2f4 --- /dev/null +++ b/minitests/litex/min_ddr/arty/src.yosys/top.tcl @@ -0,0 +1,60 @@ +proc write_iobuf_report {filename} { + set fp [open $filename w] + puts $fp "{ \"tiles\": \[" + foreach port [get_ports] { + set net [get_nets -of $port] + if { $net == "" } { + continue + } + + set cell [get_cells -of $net] + set site [get_sites -of $cell] + set tile [get_tiles -of $site] + + puts $fp "{" + puts $fp "\"port\": \"$port\"," + puts $fp "\"pad_wire\": \"$net\"," + puts $fp "\"cell\": \"$cell\"," + puts $fp "\"site\": \"$site\"," + puts $fp "\"tile\": \"$tile\"," + puts $fp "\"type\": \"[get_property REF_NAME $cell]\"," + puts $fp "\"IOSTANDARD\": \"\\\"[get_property IOSTANDARD $cell]\\\"\"," + puts $fp "\"PULLTYPE\": \"\\\"[get_property PULLTYPE $cell]\\\"\"," + puts $fp "\"DRIVE\": \"[get_property DRIVE $cell]\"," + puts $fp "\"SLEW\": \"\\\"[get_property SLEW $cell]\\\"\"," + puts $fp "}," + } + puts $fp "\]}" + close $fp +} + +create_project -force -name top -part xc7a35ticsg324-1L +read_xdc ../top.xdc +read_edif ../top.edif +link_design -top top -part xc7a35ticsg324-1L +report_timing_summary -file top_timing_synth.rpt +report_utilization -hierarchical -file top_utilization_hierarchical_synth.rpt +report_utilization -file top_utilization_synth.rpt +opt_design +place_design +report_utilization -hierarchical -file top_utilization_hierarchical_place.rpt +report_utilization -file top_utilization_place.rpt +report_io -file top_io.rpt +report_control_sets -verbose -file top_control_sets.rpt +report_clock_utilization -file top_clock_utilization.rpt +route_design +phys_opt_design +report_timing_summary -no_header -no_detailed_paths +write_checkpoint -force top_route.dcp +report_route_status -file top_route_status.rpt +report_drc -file top_drc.rpt +report_timing_summary -datasheet -max_paths 10 -file top_timing.rpt +report_power -file top_power.rpt +set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] +write_bitstream -force top.bit +write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit "up 0x0 top.bit" -file top.bin + +write_iobuf_report iobuf_report.json5 + + +quit diff --git a/minitests/litex/min_ddr/arty/src.yosys/top.xdc b/minitests/litex/min_ddr/arty/src.yosys/top.xdc new file mode 100644 index 00000000..7de3d702 --- /dev/null +++ b/minitests/litex/min_ddr/arty/src.yosys/top.xdc @@ -0,0 +1,230 @@ + ## serial:0.tx +set_property LOC D10 [get_ports serial_tx] +set_property IOSTANDARD LVCMOS33 [get_ports serial_tx] + ## serial:0.rx +set_property LOC A9 [get_ports serial_rx] +set_property IOSTANDARD LVCMOS33 [get_ports serial_rx] + ## clk100:0 +set_property LOC E3 [get_ports clk100] +set_property IOSTANDARD LVCMOS33 [get_ports clk100] + ## cpu_reset:0 +set_property LOC C2 [get_ports cpu_reset] +set_property IOSTANDARD LVCMOS33 [get_ports cpu_reset] + ## ddram:0.a +set_property LOC R2 [get_ports ddram_a[0]] +set_property SLEW FAST [get_ports ddram_a[0]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[0]] + ## ddram:0.a +set_property LOC M6 [get_ports ddram_a[1]] +set_property SLEW FAST [get_ports ddram_a[1]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[1]] + ## ddram:0.a +set_property LOC N4 [get_ports ddram_a[2]] +set_property SLEW FAST [get_ports ddram_a[2]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[2]] + ## ddram:0.a +set_property LOC T1 [get_ports ddram_a[3]] +set_property SLEW FAST [get_ports ddram_a[3]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[3]] + ## ddram:0.a +set_property LOC N6 [get_ports ddram_a[4]] +set_property SLEW FAST [get_ports ddram_a[4]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[4]] + ## ddram:0.a +set_property LOC R7 [get_ports ddram_a[5]] +set_property SLEW FAST [get_ports ddram_a[5]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[5]] + ## ddram:0.a +set_property LOC V6 [get_ports ddram_a[6]] +set_property SLEW FAST [get_ports ddram_a[6]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[6]] + ## ddram:0.a +set_property LOC U7 [get_ports ddram_a[7]] +set_property SLEW FAST [get_ports ddram_a[7]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[7]] + ## ddram:0.a +set_property LOC R8 [get_ports ddram_a[8]] +set_property SLEW FAST [get_ports ddram_a[8]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[8]] + ## ddram:0.a +set_property LOC V7 [get_ports ddram_a[9]] +set_property SLEW FAST [get_ports ddram_a[9]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[9]] + ## ddram:0.a +set_property LOC R6 [get_ports ddram_a[10]] +set_property SLEW FAST [get_ports ddram_a[10]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[10]] + ## ddram:0.a +set_property LOC U6 [get_ports ddram_a[11]] +set_property SLEW FAST [get_ports ddram_a[11]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[11]] + ## ddram:0.a +set_property LOC T6 [get_ports ddram_a[12]] +set_property SLEW FAST [get_ports ddram_a[12]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[12]] + ## ddram:0.a +set_property LOC T8 [get_ports ddram_a[13]] +set_property SLEW FAST [get_ports ddram_a[13]] +set_property IOSTANDARD SSTL135 [get_ports ddram_a[13]] + ## ddram:0.ba +set_property LOC R1 [get_ports ddram_ba[0]] +set_property SLEW FAST [get_ports ddram_ba[0]] +set_property IOSTANDARD SSTL135 [get_ports ddram_ba[0]] + ## ddram:0.ba +set_property LOC P4 [get_ports ddram_ba[1]] +set_property SLEW FAST [get_ports ddram_ba[1]] +set_property IOSTANDARD SSTL135 [get_ports ddram_ba[1]] + ## ddram:0.ba +set_property LOC P2 [get_ports ddram_ba[2]] +set_property SLEW FAST [get_ports ddram_ba[2]] +set_property IOSTANDARD SSTL135 [get_ports ddram_ba[2]] + ## ddram:0.ras_n +set_property LOC P3 [get_ports ddram_ras_n] +set_property SLEW FAST [get_ports ddram_ras_n] +set_property IOSTANDARD SSTL135 [get_ports ddram_ras_n] + ## ddram:0.cas_n +set_property LOC M4 [get_ports ddram_cas_n] +set_property SLEW FAST [get_ports ddram_cas_n] +set_property IOSTANDARD SSTL135 [get_ports ddram_cas_n] + ## ddram:0.we_n +set_property LOC P5 [get_ports ddram_we_n] +set_property SLEW FAST [get_ports ddram_we_n] +set_property IOSTANDARD SSTL135 [get_ports ddram_we_n] + ## ddram:0.cs_n +set_property LOC U8 [get_ports ddram_cs_n] +set_property SLEW FAST [get_ports ddram_cs_n] +set_property IOSTANDARD SSTL135 [get_ports ddram_cs_n] + ## ddram:0.dm +set_property LOC L1 [get_ports ddram_dm[0]] +set_property SLEW FAST [get_ports ddram_dm[0]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dm[0]] + ## ddram:0.dm +set_property LOC U1 [get_ports ddram_dm[1]] +set_property SLEW FAST [get_ports ddram_dm[1]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dm[1]] + ## ddram:0.dq +set_property LOC K5 [get_ports ddram_dq[0]] +set_property SLEW FAST [get_ports ddram_dq[0]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[0]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[0]] + ## ddram:0.dq +set_property LOC L3 [get_ports ddram_dq[1]] +set_property SLEW FAST [get_ports ddram_dq[1]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[1]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[1]] + ## ddram:0.dq +set_property LOC K3 [get_ports ddram_dq[2]] +set_property SLEW FAST [get_ports ddram_dq[2]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[2]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[2]] + ## ddram:0.dq +set_property LOC L6 [get_ports ddram_dq[3]] +set_property SLEW FAST [get_ports ddram_dq[3]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[3]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[3]] + ## ddram:0.dq +set_property LOC M3 [get_ports ddram_dq[4]] +set_property SLEW FAST [get_ports ddram_dq[4]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[4]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[4]] + ## ddram:0.dq +set_property LOC M1 [get_ports ddram_dq[5]] +set_property SLEW FAST [get_ports ddram_dq[5]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[5]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[5]] + ## ddram:0.dq +set_property LOC L4 [get_ports ddram_dq[6]] +set_property SLEW FAST [get_ports ddram_dq[6]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[6]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[6]] + ## ddram:0.dq +set_property LOC M2 [get_ports ddram_dq[7]] +set_property SLEW FAST [get_ports ddram_dq[7]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[7]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[7]] + ## ddram:0.dq +set_property LOC V4 [get_ports ddram_dq[8]] +set_property SLEW FAST [get_ports ddram_dq[8]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[8]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[8]] + ## ddram:0.dq +set_property LOC T5 [get_ports ddram_dq[9]] +set_property SLEW FAST [get_ports ddram_dq[9]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[9]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[9]] + ## ddram:0.dq +set_property LOC U4 [get_ports ddram_dq[10]] +set_property SLEW FAST [get_ports ddram_dq[10]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[10]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[10]] + ## ddram:0.dq +set_property LOC V5 [get_ports ddram_dq[11]] +set_property SLEW FAST [get_ports ddram_dq[11]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[11]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[11]] + ## ddram:0.dq +set_property LOC V1 [get_ports ddram_dq[12]] +set_property SLEW FAST [get_ports ddram_dq[12]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[12]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[12]] + ## ddram:0.dq +set_property LOC T3 [get_ports ddram_dq[13]] +set_property SLEW FAST [get_ports ddram_dq[13]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[13]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[13]] + ## ddram:0.dq +set_property LOC U3 [get_ports ddram_dq[14]] +set_property SLEW FAST [get_ports ddram_dq[14]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[14]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[14]] + ## ddram:0.dq +set_property LOC R3 [get_ports ddram_dq[15]] +set_property SLEW FAST [get_ports ddram_dq[15]] +set_property IOSTANDARD SSTL135 [get_ports ddram_dq[15]] +set_property IN_TERM UNTUNED_SPLIT_40 [get_ports ddram_dq[15]] + ## ddram:0.dqs_p +set_property LOC N2 [get_ports ddram_dqs_p[0]] +set_property SLEW FAST [get_ports ddram_dqs_p[0]] +set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_p[0]] + ## ddram:0.dqs_p +set_property LOC U2 [get_ports ddram_dqs_p[1]] +set_property SLEW FAST [get_ports ddram_dqs_p[1]] +set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_p[1]] + ## ddram:0.dqs_n +set_property LOC N1 [get_ports ddram_dqs_n[0]] +set_property SLEW FAST [get_ports ddram_dqs_n[0]] +set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_n[0]] + ## ddram:0.dqs_n +set_property LOC V2 [get_ports ddram_dqs_n[1]] +set_property SLEW FAST [get_ports ddram_dqs_n[1]] +set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_dqs_n[1]] + ## ddram:0.clk_p +set_property LOC U9 [get_ports ddram_clk_p] +set_property SLEW FAST [get_ports ddram_clk_p] +set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_p] + ## ddram:0.clk_n +set_property LOC V9 [get_ports ddram_clk_n] +set_property SLEW FAST [get_ports ddram_clk_n] +set_property IOSTANDARD DIFF_SSTL135 [get_ports ddram_clk_n] + ## ddram:0.cke +set_property LOC N5 [get_ports ddram_cke] +set_property SLEW FAST [get_ports ddram_cke] +set_property IOSTANDARD SSTL135 [get_ports ddram_cke] + ## ddram:0.odt +set_property LOC R5 [get_ports ddram_odt] +set_property SLEW FAST [get_ports ddram_odt] +set_property IOSTANDARD SSTL135 [get_ports ddram_odt] + ## ddram:0.reset_n +set_property LOC K6 [get_ports ddram_reset_n] +set_property SLEW FAST [get_ports ddram_reset_n] +set_property IOSTANDARD SSTL135 [get_ports ddram_reset_n] + +set_property INTERNAL_VREF 0.675 [get_iobanks 34] + +create_clock -name clk100 -period 10.0 [get_nets clk100] + +set_false_path -quiet -to [get_nets -quiet -filter {mr_ff == TRUE}] + +set_false_path -quiet -to [get_pins -quiet -filter {REF_PIN_NAME == PRE} -of [get_cells -quiet -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]] + +set_max_delay 2 -quiet -from [get_pins -quiet -filter {REF_PIN_NAME == Q} -of [get_cells -quiet -filter {ars_ff1 == TRUE}]] -to [get_pins -quiet -filter {REF_PIN_NAME == D} -of [get_cells -quiet -filter {ars_ff2 == TRUE}]] \ No newline at end of file diff --git a/minitests/litex/min_ddr/arty/verilog/VexRiscv_Lite.v b/minitests/litex/min_ddr/arty/verilog/VexRiscv_Lite.v new file mode 100644 index 00000000..6ed8c8fc --- /dev/null +++ b/minitests/litex/min_ddr/arty/verilog/VexRiscv_Lite.v @@ -0,0 +1,4819 @@ +// Generator : SpinalHDL v1.3.6 git head : 9bf01e7f360e003fac1dd5ca8b8f4bffec0e52b8 +// Date : 16/06/2019, 23:18:37 +// Component : VexRiscv + + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 + +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + +`define EnvCtrlEnum_defaultEncoding_type [0:0] +`define EnvCtrlEnum_defaultEncoding_NONE 1'b0 +`define EnvCtrlEnum_defaultEncoding_XRET 1'b1 + +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input io_cpu_fetch_dataBypassValid, + input [31:0] io_cpu_fetch_dataBypass, + output io_cpu_fetch_mmuBus_cmd_isValid, + output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress, + output io_cpu_fetch_mmuBus_cmd_bypassTranslation, + input [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress, + input io_cpu_fetch_mmuBus_rsp_isIoAccess, + input io_cpu_fetch_mmuBus_rsp_allowRead, + input io_cpu_fetch_mmuBus_rsp_allowWrite, + input io_cpu_fetch_mmuBus_rsp_allowExecute, + input io_cpu_fetch_mmuBus_rsp_exception, + input io_cpu_fetch_mmuBus_rsp_refilling, + output io_cpu_fetch_mmuBus_end, + input io_cpu_fetch_mmuBus_busy, + output [31:0] io_cpu_fetch_physicalAddress, + output io_cpu_fetch_haltIt, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset); + reg [22:0] _zz_10_; + reg [31:0] _zz_11_; + wire _zz_12_; + wire _zz_13_; + wire [0:0] _zz_14_; + wire [0:0] _zz_15_; + wire [22:0] _zz_16_; + reg _zz_1_; + reg _zz_2_; + reg lineLoader_fire; + reg lineLoader_valid; + reg [31:0] lineLoader_address; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [6:0] lineLoader_flushCounter; + reg _zz_3_; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + reg [2:0] lineLoader_wordIndex; + wire lineLoader_write_tag_0_valid; + wire [5:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [20:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [8:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire _zz_4_; + wire [5:0] _zz_5_; + wire _zz_6_; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [20:0] fetchStage_read_waysValues_0_tag_address; + wire [22:0] _zz_7_; + wire [8:0] _zz_8_; + wire _zz_9_; + wire [31:0] fetchStage_read_waysValues_0_data; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + reg [31:0] io_cpu_fetch_data_regNextWhen; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_hit_valid; + reg decodeStage_hit_error; + (* ram_style = "block" *) reg [22:0] ways_0_tags [0:63]; + (* ram_style = "block" *) reg [31:0] ways_0_datas [0:511]; + assign _zz_12_ = (! lineLoader_flushCounter[6]); + assign _zz_13_ = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_14_ = _zz_7_[0 : 0]; + assign _zz_15_ = _zz_7_[1 : 1]; + assign _zz_16_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_2_) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_16_; + end + end + + always @ (posedge clk) begin + if(_zz_6_) begin + _zz_10_ <= ways_0_tags[_zz_5_]; + end + end + + always @ (posedge clk) begin + if(_zz_1_) begin + ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_9_) begin + _zz_11_ <= ways_0_datas[_zz_8_]; + end + end + + always @ (*) begin + _zz_1_ = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1_ = 1'b1; + end + end + + always @ (*) begin + _zz_2_ = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2_ = 1'b1; + end + end + + assign io_cpu_fetch_haltIt = io_cpu_fetch_mmuBus_busy; + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == (3'b111)))begin + lineLoader_fire = 1'b1; + end + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_12_)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3_))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)}; + assign io_mem_cmd_payload_size = (3'b101); + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if((! lineLoader_valid))begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign _zz_4_ = 1'b1; + assign lineLoader_write_tag_0_valid = ((_zz_4_ && lineLoader_fire) || (! lineLoader_flushCounter[6])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[10 : 5] : lineLoader_flushCounter[5 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 11]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_4_); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_5_ = io_cpu_prefetch_pc[10 : 5]; + assign _zz_6_ = (! io_cpu_fetch_isStuck); + assign _zz_7_ = _zz_10_; + assign fetchStage_read_waysValues_0_tag_valid = _zz_14_[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_15_[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_7_[22 : 2]; + assign _zz_8_ = io_cpu_prefetch_pc[10 : 2]; + assign _zz_9_ = (! io_cpu_fetch_isStuck); + assign fetchStage_read_waysValues_0_data = _zz_11_; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuBus_rsp_physicalAddress[31 : 11])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != (1'b0)); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_waysValues_0_data; + assign fetchStage_hit_word = fetchStage_hit_data[31 : 0]; + assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_hit_word); + assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; + assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid; + assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc; + assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0; + assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved); + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress; + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = decodeStage_hit_error; + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = ((! decodeStage_mmuRsp_refilling) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @ (posedge clk) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= (3'b000); + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; + end + if(io_flush)begin + lineLoader_flushPending <= 1'b1; + end + if(_zz_13_)begin + lineLoader_flushPending <= 1'b0; + end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + (3'b001)); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; + end + end + end + end + + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_12_)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + (7'b0000001)); + end + _zz_3_ <= lineLoader_flushCounter[6]; + if(_zz_13_)begin + lineLoader_flushCounter <= (7'b0000000); + end + if((! io_cpu_decode_isStuck))begin + io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuBus_rsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuBus_rsp_isIoAccess; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuBus_rsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuBus_rsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuBus_rsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuBus_rsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuBus_rsp_refilling; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_valid <= fetchStage_hit_valid; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_error <= fetchStage_hit_error; + end + end + +endmodule + +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + input [31:0] externalInterruptArray, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [1:0] iBusWishbone_BTE, + output [2:0] iBusWishbone_CTI, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output reg [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [1:0] dBusWishbone_BTE, + output [2:0] dBusWishbone_CTI, + input clk, + input reset); + wire _zz_205_; + wire _zz_206_; + wire _zz_207_; + wire _zz_208_; + wire [31:0] _zz_209_; + wire _zz_210_; + wire _zz_211_; + wire _zz_212_; + reg _zz_213_; + reg [31:0] _zz_214_; + reg [31:0] _zz_215_; + reg [31:0] _zz_216_; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_fetch_haltIt; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire _zz_217_; + wire _zz_218_; + wire _zz_219_; + wire _zz_220_; + wire _zz_221_; + wire _zz_222_; + wire _zz_223_; + wire _zz_224_; + wire _zz_225_; + wire _zz_226_; + wire _zz_227_; + wire _zz_228_; + wire _zz_229_; + wire _zz_230_; + wire _zz_231_; + wire _zz_232_; + wire _zz_233_; + wire _zz_234_; + wire _zz_235_; + wire [1:0] _zz_236_; + wire _zz_237_; + wire _zz_238_; + wire _zz_239_; + wire _zz_240_; + wire _zz_241_; + wire _zz_242_; + wire _zz_243_; + wire _zz_244_; + wire _zz_245_; + wire _zz_246_; + wire _zz_247_; + wire _zz_248_; + wire _zz_249_; + wire _zz_250_; + wire _zz_251_; + wire _zz_252_; + wire [1:0] _zz_253_; + wire _zz_254_; + wire [4:0] _zz_255_; + wire [2:0] _zz_256_; + wire [31:0] _zz_257_; + wire [11:0] _zz_258_; + wire [31:0] _zz_259_; + wire [19:0] _zz_260_; + wire [11:0] _zz_261_; + wire [31:0] _zz_262_; + wire [31:0] _zz_263_; + wire [19:0] _zz_264_; + wire [11:0] _zz_265_; + wire [2:0] _zz_266_; + wire [0:0] _zz_267_; + wire [0:0] _zz_268_; + wire [0:0] _zz_269_; + wire [0:0] _zz_270_; + wire [0:0] _zz_271_; + wire [0:0] _zz_272_; + wire [0:0] _zz_273_; + wire [0:0] _zz_274_; + wire [0:0] _zz_275_; + wire [0:0] _zz_276_; + wire [0:0] _zz_277_; + wire [0:0] _zz_278_; + wire [0:0] _zz_279_; + wire [0:0] _zz_280_; + wire [0:0] _zz_281_; + wire [0:0] _zz_282_; + wire [0:0] _zz_283_; + wire [2:0] _zz_284_; + wire [4:0] _zz_285_; + wire [11:0] _zz_286_; + wire [11:0] _zz_287_; + wire [31:0] _zz_288_; + wire [31:0] _zz_289_; + wire [31:0] _zz_290_; + wire [31:0] _zz_291_; + wire [31:0] _zz_292_; + wire [31:0] _zz_293_; + wire [31:0] _zz_294_; + wire [31:0] _zz_295_; + wire [32:0] _zz_296_; + wire [11:0] _zz_297_; + wire [19:0] _zz_298_; + wire [11:0] _zz_299_; + wire [31:0] _zz_300_; + wire [31:0] _zz_301_; + wire [31:0] _zz_302_; + wire [11:0] _zz_303_; + wire [19:0] _zz_304_; + wire [11:0] _zz_305_; + wire [2:0] _zz_306_; + wire [1:0] _zz_307_; + wire [1:0] _zz_308_; + wire [1:0] _zz_309_; + wire [1:0] _zz_310_; + wire [0:0] _zz_311_; + wire [5:0] _zz_312_; + wire [33:0] _zz_313_; + wire [32:0] _zz_314_; + wire [33:0] _zz_315_; + wire [32:0] _zz_316_; + wire [33:0] _zz_317_; + wire [32:0] _zz_318_; + wire [0:0] _zz_319_; + wire [5:0] _zz_320_; + wire [32:0] _zz_321_; + wire [32:0] _zz_322_; + wire [31:0] _zz_323_; + wire [31:0] _zz_324_; + wire [32:0] _zz_325_; + wire [32:0] _zz_326_; + wire [32:0] _zz_327_; + wire [0:0] _zz_328_; + wire [32:0] _zz_329_; + wire [0:0] _zz_330_; + wire [32:0] _zz_331_; + wire [0:0] _zz_332_; + wire [31:0] _zz_333_; + wire [0:0] _zz_334_; + wire [0:0] _zz_335_; + wire [0:0] _zz_336_; + wire [0:0] _zz_337_; + wire [0:0] _zz_338_; + wire [0:0] _zz_339_; + wire [26:0] _zz_340_; + wire [6:0] _zz_341_; + wire _zz_342_; + wire _zz_343_; + wire [2:0] _zz_344_; + wire _zz_345_; + wire _zz_346_; + wire _zz_347_; + wire _zz_348_; + wire [0:0] _zz_349_; + wire [0:0] _zz_350_; + wire [0:0] _zz_351_; + wire [0:0] _zz_352_; + wire _zz_353_; + wire [0:0] _zz_354_; + wire [23:0] _zz_355_; + wire [31:0] _zz_356_; + wire [31:0] _zz_357_; + wire _zz_358_; + wire [0:0] _zz_359_; + wire [0:0] _zz_360_; + wire [0:0] _zz_361_; + wire [0:0] _zz_362_; + wire [1:0] _zz_363_; + wire [1:0] _zz_364_; + wire _zz_365_; + wire [0:0] _zz_366_; + wire [20:0] _zz_367_; + wire [31:0] _zz_368_; + wire [31:0] _zz_369_; + wire [31:0] _zz_370_; + wire [31:0] _zz_371_; + wire _zz_372_; + wire [0:0] _zz_373_; + wire [1:0] _zz_374_; + wire [0:0] _zz_375_; + wire [0:0] _zz_376_; + wire _zz_377_; + wire [0:0] _zz_378_; + wire [17:0] _zz_379_; + wire [31:0] _zz_380_; + wire [31:0] _zz_381_; + wire [31:0] _zz_382_; + wire [31:0] _zz_383_; + wire [31:0] _zz_384_; + wire [31:0] _zz_385_; + wire [31:0] _zz_386_; + wire [31:0] _zz_387_; + wire [0:0] _zz_388_; + wire [0:0] _zz_389_; + wire [5:0] _zz_390_; + wire [5:0] _zz_391_; + wire _zz_392_; + wire [0:0] _zz_393_; + wire [14:0] _zz_394_; + wire [31:0] _zz_395_; + wire [31:0] _zz_396_; + wire _zz_397_; + wire [0:0] _zz_398_; + wire [2:0] _zz_399_; + wire _zz_400_; + wire _zz_401_; + wire [0:0] _zz_402_; + wire [2:0] _zz_403_; + wire [0:0] _zz_404_; + wire [0:0] _zz_405_; + wire _zz_406_; + wire [0:0] _zz_407_; + wire [11:0] _zz_408_; + wire [31:0] _zz_409_; + wire [31:0] _zz_410_; + wire [31:0] _zz_411_; + wire _zz_412_; + wire [0:0] _zz_413_; + wire [0:0] _zz_414_; + wire [31:0] _zz_415_; + wire [31:0] _zz_416_; + wire [31:0] _zz_417_; + wire [31:0] _zz_418_; + wire _zz_419_; + wire [0:0] _zz_420_; + wire [0:0] _zz_421_; + wire [31:0] _zz_422_; + wire [31:0] _zz_423_; + wire [0:0] _zz_424_; + wire [0:0] _zz_425_; + wire [0:0] _zz_426_; + wire [0:0] _zz_427_; + wire _zz_428_; + wire [0:0] _zz_429_; + wire [9:0] _zz_430_; + wire [31:0] _zz_431_; + wire [31:0] _zz_432_; + wire [31:0] _zz_433_; + wire [31:0] _zz_434_; + wire [31:0] _zz_435_; + wire [31:0] _zz_436_; + wire [31:0] _zz_437_; + wire [31:0] _zz_438_; + wire [31:0] _zz_439_; + wire [31:0] _zz_440_; + wire [31:0] _zz_441_; + wire [31:0] _zz_442_; + wire [31:0] _zz_443_; + wire [31:0] _zz_444_; + wire _zz_445_; + wire [0:0] _zz_446_; + wire [0:0] _zz_447_; + wire _zz_448_; + wire [0:0] _zz_449_; + wire [7:0] _zz_450_; + wire _zz_451_; + wire [0:0] _zz_452_; + wire [0:0] _zz_453_; + wire [0:0] _zz_454_; + wire [0:0] _zz_455_; + wire [0:0] _zz_456_; + wire [0:0] _zz_457_; + wire _zz_458_; + wire [0:0] _zz_459_; + wire [3:0] _zz_460_; + wire [31:0] _zz_461_; + wire [31:0] _zz_462_; + wire [31:0] _zz_463_; + wire [31:0] _zz_464_; + wire [31:0] _zz_465_; + wire _zz_466_; + wire _zz_467_; + wire [0:0] _zz_468_; + wire [1:0] _zz_469_; + wire [2:0] _zz_470_; + wire [2:0] _zz_471_; + wire _zz_472_; + wire [0:0] _zz_473_; + wire [0:0] _zz_474_; + wire [31:0] _zz_475_; + wire [31:0] _zz_476_; + wire [31:0] _zz_477_; + wire [31:0] _zz_478_; + wire [31:0] _zz_479_; + wire _zz_480_; + wire _zz_481_; + wire [31:0] _zz_482_; + wire [31:0] _zz_483_; + wire [0:0] _zz_484_; + wire [0:0] _zz_485_; + wire _zz_486_; + wire [31:0] _zz_487_; + wire [31:0] _zz_488_; + wire [31:0] _zz_489_; + wire _zz_490_; + wire [0:0] _zz_491_; + wire [10:0] _zz_492_; + wire [31:0] _zz_493_; + wire [31:0] _zz_494_; + wire [31:0] _zz_495_; + wire _zz_496_; + wire [0:0] _zz_497_; + wire [4:0] _zz_498_; + wire [31:0] _zz_499_; + wire [31:0] _zz_500_; + wire [31:0] _zz_501_; + wire [31:0] _zz_502_; + wire [31:0] _zz_503_; + wire _zz_504_; + wire _zz_505_; + wire _zz_506_; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_1_; + wire `AluCtrlEnum_defaultEncoding_type _zz_2_; + wire `AluCtrlEnum_defaultEncoding_type _zz_3_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_4_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_5_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_6_; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_7_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_8_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_9_; + wire decode_IS_RS2_SIGNED; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire decode_IS_RS1_SIGNED; + wire decode_CSR_READ_OPCODE; + wire decode_IS_DIV; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_IS_MUL; + wire [31:0] execute_BRANCH_CALC; + wire `BranchCtrlEnum_defaultEncoding_type _zz_10_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_11_; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_12_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_13_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_14_; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_SRC2_FORCE_ZERO; + wire decode_CSR_WRITE_OPCODE; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire execute_BRANCH_DO; + wire decode_SRC_LESS_UNSIGNED; + wire `EnvCtrlEnum_defaultEncoding_type _zz_15_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_16_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_17_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_18_; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_19_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_20_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_21_; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire decode_MEMORY_STORE; + wire decode_PREDICTION_HAD_BRANCHED2; + wire decode_IS_CSR; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_22_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_23_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_24_; + wire [31:0] memory_MEMORY_READ_DATA; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_MUL; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire memory_IS_MUL; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_25_; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_26_; + wire _zz_27_; + wire _zz_28_; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_29_; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] _zz_30_; + wire [31:0] execute_PC; + wire execute_PREDICTION_HAD_BRANCHED2; + wire _zz_31_; + wire [31:0] execute_RS1; + wire execute_BRANCH_COND_RESULT; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_32_; + wire _zz_33_; + wire _zz_34_; + wire decode_RS2_USE; + wire decode_RS1_USE; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + reg [31:0] _zz_35_; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + reg [31:0] _zz_36_; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_37_; + wire _zz_38_; + wire [31:0] _zz_39_; + wire [31:0] _zz_40_; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_41_; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_42_; + wire [31:0] _zz_43_; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_44_; + wire [31:0] _zz_45_; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire _zz_46_; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_47_; + wire [31:0] _zz_48_; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_49_; + wire [31:0] _zz_50_; + wire _zz_51_; + reg _zz_52_; + wire [31:0] _zz_53_; + wire [31:0] _zz_54_; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire decode_INSTRUCTION_READY; + wire _zz_55_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_56_; + wire _zz_57_; + wire _zz_58_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_59_; + wire _zz_60_; + wire _zz_61_; + wire _zz_62_; + wire _zz_63_; + wire _zz_64_; + wire _zz_65_; + wire _zz_66_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_67_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_68_; + wire _zz_69_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_70_; + wire _zz_71_; + wire `AluCtrlEnum_defaultEncoding_type _zz_72_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_73_; + wire _zz_74_; + wire _zz_75_; + wire _zz_76_; + wire _zz_77_; + wire _zz_78_; + wire writeBack_MEMORY_STORE; + reg [31:0] _zz_79_; + wire writeBack_MEMORY_ENABLE; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire [31:0] writeBack_MEMORY_READ_DATA; + wire memory_MMU_FAULT; + wire [31:0] memory_MMU_RSP_physicalAddress; + wire memory_MMU_RSP_isIoAccess; + wire memory_MMU_RSP_allowRead; + wire memory_MMU_RSP_allowWrite; + wire memory_MMU_RSP_allowExecute; + wire memory_MMU_RSP_exception; + wire memory_MMU_RSP_refilling; + wire [31:0] memory_PC; + wire memory_ALIGNEMENT_FAULT; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_STORE; + wire memory_MEMORY_ENABLE; + wire [31:0] _zz_80_; + wire [31:0] _zz_81_; + wire _zz_82_; + wire _zz_83_; + wire _zz_84_; + wire _zz_85_; + wire _zz_86_; + wire _zz_87_; + wire execute_MMU_FAULT; + wire [31:0] execute_MMU_RSP_physicalAddress; + wire execute_MMU_RSP_isIoAccess; + wire execute_MMU_RSP_allowRead; + wire execute_MMU_RSP_allowWrite; + wire execute_MMU_RSP_allowExecute; + wire execute_MMU_RSP_exception; + wire execute_MMU_RSP_refilling; + wire _zz_88_; + wire [31:0] execute_SRC_ADD; + wire [1:0] _zz_89_; + wire [31:0] execute_RS2; + wire [31:0] execute_INSTRUCTION; + wire execute_MEMORY_STORE; + wire execute_MEMORY_ENABLE; + wire execute_ALIGNEMENT_FAULT; + wire _zz_90_; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected; + reg _zz_91_; + reg _zz_92_; + reg _zz_93_; + wire [31:0] _zz_94_; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_95_; + wire [31:0] decode_INSTRUCTION; + reg [31:0] _zz_96_; + reg [31:0] _zz_97_; + wire [31:0] decode_PC; + wire [31:0] _zz_98_; + wire [31:0] _zz_99_; + wire [31:0] _zz_100_; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + wire decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + wire execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + wire execute_arbitration_flushIt; + wire execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + reg memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + wire writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + wire writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_fetcherflushIt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_predictionJumpInterface_valid; + (* syn_keep , keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; + reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + wire IBusCachedPlugin_redoBranch_valid; + wire [31:0] IBusCachedPlugin_redoBranch_payload; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_isValid; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_bypassTranslation; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire IBusCachedPlugin_mmuBus_rsp_allowRead; + wire IBusCachedPlugin_mmuBus_rsp_allowWrite; + wire IBusCachedPlugin_mmuBus_rsp_allowExecute; + wire IBusCachedPlugin_mmuBus_rsp_exception; + wire IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + reg DBusSimplePlugin_memoryExceptionPort_valid; + reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; + wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; + wire DBusSimplePlugin_mmuBus_cmd_isValid; + wire [31:0] DBusSimplePlugin_mmuBus_cmd_virtualAddress; + wire DBusSimplePlugin_mmuBus_cmd_bypassTranslation; + wire [31:0] DBusSimplePlugin_mmuBus_rsp_physicalAddress; + wire DBusSimplePlugin_mmuBus_rsp_isIoAccess; + wire DBusSimplePlugin_mmuBus_rsp_allowRead; + wire DBusSimplePlugin_mmuBus_rsp_allowWrite; + wire DBusSimplePlugin_mmuBus_rsp_allowExecute; + wire DBusSimplePlugin_mmuBus_rsp_exception; + wire DBusSimplePlugin_mmuBus_rsp_refilling; + wire DBusSimplePlugin_mmuBus_end; + wire DBusSimplePlugin_mmuBus_busy; + reg DBusSimplePlugin_redoBranch_valid; + wire [31:0] DBusSimplePlugin_redoBranch_payload; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + wire CsrPlugin_forceMachineWire; + wire CsrPlugin_allowInterrupts; + wire CsrPlugin_allowException; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [4:0] _zz_101_; + wire [4:0] _zz_102_; + wire _zz_103_; + wire _zz_104_; + wire _zz_105_; + wire _zz_106_; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_0_inputSample; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_inputSample; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; + reg IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample; + wire _zz_107_; + wire _zz_108_; + wire _zz_109_; + wire _zz_110_; + wire _zz_111_; + reg _zz_112_; + wire _zz_113_; + reg _zz_114_; + reg [31:0] _zz_115_; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_decodeInput_valid; + wire IBusCachedPlugin_iBusRsp_decodeInput_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; + wire IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_decodeInput_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + reg IBusCachedPlugin_injector_decodeRemoved; + wire _zz_116_; + reg [18:0] _zz_117_; + wire _zz_118_; + reg [10:0] _zz_119_; + wire _zz_120_; + reg [18:0] _zz_121_; + reg _zz_122_; + wire _zz_123_; + reg [10:0] _zz_124_; + wire _zz_125_; + reg [18:0] _zz_126_; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire [31:0] _zz_127_; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + reg IBusCachedPlugin_rsp_redoFetch; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [1:0] dBus_cmd_payload_size; + wire dBus_rsp_ready; + wire dBus_rsp_error; + wire [31:0] dBus_rsp_data; + wire _zz_128_; + reg execute_DBusSimplePlugin_skipCmd; + reg [31:0] _zz_129_; + reg [3:0] _zz_130_; + wire [3:0] execute_DBusSimplePlugin_formalMask; + reg [31:0] writeBack_DBusSimplePlugin_rspShifted; + wire _zz_131_; + reg [31:0] _zz_132_; + wire _zz_133_; + reg [31:0] _zz_134_; + reg [31:0] writeBack_DBusSimplePlugin_rspFormated; + wire [29:0] _zz_135_; + wire _zz_136_; + wire _zz_137_; + wire _zz_138_; + wire _zz_139_; + wire _zz_140_; + wire _zz_141_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_142_; + wire `AluCtrlEnum_defaultEncoding_type _zz_143_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_144_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_145_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_146_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_147_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_148_; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_149_; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_150_; + reg [31:0] _zz_151_; + wire _zz_152_; + reg [19:0] _zz_153_; + wire _zz_154_; + reg [19:0] _zz_155_; + reg [31:0] _zz_156_; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + reg execute_LightShifterPlugin_isActive; + wire execute_LightShifterPlugin_isShift; + reg [4:0] execute_LightShifterPlugin_amplitudeReg; + wire [4:0] execute_LightShifterPlugin_amplitude; + wire [31:0] execute_LightShifterPlugin_shiftInput; + wire execute_LightShifterPlugin_done; + reg [31:0] _zz_157_; + reg _zz_158_; + reg _zz_159_; + wire _zz_160_; + reg _zz_161_; + reg [4:0] _zz_162_; + reg [31:0] _zz_163_; + wire _zz_164_; + wire _zz_165_; + wire _zz_166_; + wire _zz_167_; + wire _zz_168_; + wire _zz_169_; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_170_; + reg _zz_171_; + reg _zz_172_; + wire _zz_173_; + reg [19:0] _zz_174_; + wire _zz_175_; + reg [10:0] _zz_176_; + wire _zz_177_; + reg [18:0] _zz_178_; + reg _zz_179_; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_180_; + reg [19:0] _zz_181_; + wire _zz_182_; + reg [10:0] _zz_183_; + wire _zz_184_; + reg [18:0] _zz_185_; + wire [31:0] execute_BranchPlugin_branchAdder; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_186_; + wire _zz_187_; + wire _zz_188_; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_189_; + wire _zz_190_; + wire [1:0] _zz_191_; + wire _zz_192_; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + wire CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + wire execute_CsrPlugin_inWfi /* verilator public */ ; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + reg [31:0] execute_CsrPlugin_readData; + wire execute_CsrPlugin_writeInstruction; + wire execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg [32:0] memory_MulDivIterativePlugin_rs1; + reg [31:0] memory_MulDivIterativePlugin_rs2; + reg [64:0] memory_MulDivIterativePlugin_accumulator; + reg memory_MulDivIterativePlugin_mul_counter_willIncrement; + reg memory_MulDivIterativePlugin_mul_counter_willClear; + reg [5:0] memory_MulDivIterativePlugin_mul_counter_valueNext; + reg [5:0] memory_MulDivIterativePlugin_mul_counter_value; + wire memory_MulDivIterativePlugin_mul_willOverflowIfInc; + wire memory_MulDivIterativePlugin_mul_counter_willOverflow; + reg memory_MulDivIterativePlugin_div_needRevert; + reg memory_MulDivIterativePlugin_div_counter_willIncrement; + reg memory_MulDivIterativePlugin_div_counter_willClear; + reg [5:0] memory_MulDivIterativePlugin_div_counter_valueNext; + reg [5:0] memory_MulDivIterativePlugin_div_counter_value; + wire memory_MulDivIterativePlugin_div_counter_willOverflowIfInc; + wire memory_MulDivIterativePlugin_div_counter_willOverflow; + reg memory_MulDivIterativePlugin_div_done; + reg [31:0] memory_MulDivIterativePlugin_div_result; + wire [31:0] _zz_193_; + wire [32:0] _zz_194_; + wire [32:0] _zz_195_; + wire [31:0] _zz_196_; + wire _zz_197_; + wire _zz_198_; + reg [32:0] _zz_199_; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_200_; + wire [31:0] _zz_201_; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg execute_to_memory_ALIGNEMENT_FAULT; + reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg decode_to_execute_IS_CSR; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + reg decode_to_execute_MEMORY_STORE; + reg execute_to_memory_MEMORY_STORE; + reg memory_to_writeBack_MEMORY_STORE; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg execute_to_memory_BRANCH_DO; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg [31:0] decode_to_execute_RS1; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg execute_to_memory_MMU_FAULT; + reg [31:0] execute_to_memory_BRANCH_CALC; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_IS_MUL; + reg execute_to_memory_IS_MUL; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg decode_to_execute_IS_DIV; + reg execute_to_memory_IS_DIV; + reg decode_to_execute_CSR_READ_OPCODE; + reg decode_to_execute_IS_RS1_SIGNED; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg [31:0] execute_to_memory_MMU_RSP_physicalAddress; + reg execute_to_memory_MMU_RSP_isIoAccess; + reg execute_to_memory_MMU_RSP_allowRead; + reg execute_to_memory_MMU_RSP_allowWrite; + reg execute_to_memory_MMU_RSP_allowExecute; + reg execute_to_memory_MMU_RSP_exception; + reg execute_to_memory_MMU_RSP_refilling; + reg decode_to_execute_IS_RS2_SIGNED; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg [2:0] _zz_202_; + reg _zz_203_; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + wire dBus_cmd_halfPipe_valid; + wire dBus_cmd_halfPipe_ready; + wire dBus_cmd_halfPipe_payload_wr; + wire [31:0] dBus_cmd_halfPipe_payload_address; + wire [31:0] dBus_cmd_halfPipe_payload_data; + wire [1:0] dBus_cmd_halfPipe_payload_size; + reg dBus_cmd_halfPipe_regs_valid; + reg dBus_cmd_halfPipe_regs_ready; + reg dBus_cmd_halfPipe_regs_payload_wr; + reg [31:0] dBus_cmd_halfPipe_regs_payload_address; + reg [31:0] dBus_cmd_halfPipe_regs_payload_data; + reg [1:0] dBus_cmd_halfPipe_regs_payload_size; + reg [3:0] _zz_204_; + `ifndef SYNTHESIS + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_1__string; + reg [63:0] _zz_2__string; + reg [63:0] _zz_3__string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_4__string; + reg [39:0] _zz_5__string; + reg [39:0] _zz_6__string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_7__string; + reg [23:0] _zz_8__string; + reg [23:0] _zz_9__string; + reg [31:0] _zz_10__string; + reg [31:0] _zz_11__string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_12__string; + reg [95:0] _zz_13__string; + reg [95:0] _zz_14__string; + reg [31:0] _zz_15__string; + reg [31:0] _zz_16__string; + reg [31:0] _zz_17__string; + reg [31:0] _zz_18__string; + reg [31:0] decode_ENV_CTRL_string; + reg [31:0] _zz_19__string; + reg [31:0] _zz_20__string; + reg [31:0] _zz_21__string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_22__string; + reg [71:0] _zz_23__string; + reg [71:0] _zz_24__string; + reg [31:0] memory_ENV_CTRL_string; + reg [31:0] _zz_25__string; + reg [31:0] execute_ENV_CTRL_string; + reg [31:0] _zz_26__string; + reg [31:0] writeBack_ENV_CTRL_string; + reg [31:0] _zz_29__string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_32__string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_37__string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_42__string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_44__string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_47__string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_49__string; + reg [95:0] _zz_56__string; + reg [23:0] _zz_59__string; + reg [31:0] _zz_67__string; + reg [31:0] _zz_68__string; + reg [39:0] _zz_70__string; + reg [63:0] _zz_72__string; + reg [71:0] _zz_73__string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_95__string; + reg [71:0] _zz_142__string; + reg [63:0] _zz_143__string; + reg [39:0] _zz_144__string; + reg [31:0] _zz_145__string; + reg [31:0] _zz_146__string; + reg [23:0] _zz_147__string; + reg [95:0] _zz_148__string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_ENV_CTRL_string; + reg [31:0] execute_to_memory_ENV_CTRL_string; + reg [31:0] memory_to_writeBack_ENV_CTRL_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + `endif + + (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + assign _zz_217_ = (memory_arbitration_isValid && memory_IS_MUL); + assign _zz_218_ = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_219_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_220_ = 1'b1; + assign _zz_221_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_222_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_223_ = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != (5'b00000))); + assign _zz_224_ = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_225_ = ((_zz_210_ && IBusCachedPlugin_cache_io_cpu_decode_error) && (! _zz_91_)); + assign _zz_226_ = ((_zz_210_ && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! _zz_92_)); + assign _zz_227_ = ((_zz_210_ && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! _zz_93_)); + assign _zz_228_ = ((_zz_210_ && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! 1'b0)); + assign _zz_229_ = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != (2'b00)); + assign _zz_230_ = (! execute_arbitration_isStuckByOthers); + assign _zz_231_ = (! memory_MulDivIterativePlugin_mul_willOverflowIfInc); + assign _zz_232_ = (! memory_MulDivIterativePlugin_div_done); + assign _zz_233_ = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != (2'b00)); + assign _zz_234_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_235_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_236_ = writeBack_INSTRUCTION[29 : 28]; + assign _zz_237_ = (! IBusCachedPlugin_iBusRsp_readyForError); + assign _zz_238_ = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); + assign _zz_239_ = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); + assign _zz_240_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_241_ = (1'b0 || (! 1'b1)); + assign _zz_242_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_243_ = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_244_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_245_ = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_246_ = (! memory_arbitration_isStuck); + assign _zz_247_ = (iBus_cmd_valid || (_zz_202_ != (3'b000))); + assign _zz_248_ = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11))); + assign _zz_249_ = ((_zz_186_ && 1'b1) && (! 1'b0)); + assign _zz_250_ = ((_zz_187_ && 1'b1) && (! 1'b0)); + assign _zz_251_ = ((_zz_188_ && 1'b1) && (! 1'b0)); + assign _zz_252_ = (! dBus_cmd_halfPipe_regs_valid); + assign _zz_253_ = writeBack_INSTRUCTION[13 : 12]; + assign _zz_254_ = execute_INSTRUCTION[13]; + assign _zz_255_ = (_zz_101_ - (5'b00001)); + assign _zz_256_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)}; + assign _zz_257_ = {29'd0, _zz_256_}; + assign _zz_258_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_259_ = {{_zz_117_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_260_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_261_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_262_ = {{_zz_119_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_263_ = {{_zz_121_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_264_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_265_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_266_ = (memory_MEMORY_STORE ? (3'b110) : (3'b100)); + assign _zz_267_ = _zz_135_[0 : 0]; + assign _zz_268_ = _zz_135_[1 : 1]; + assign _zz_269_ = _zz_135_[2 : 2]; + assign _zz_270_ = _zz_135_[3 : 3]; + assign _zz_271_ = _zz_135_[8 : 8]; + assign _zz_272_ = _zz_135_[11 : 11]; + assign _zz_273_ = _zz_135_[15 : 15]; + assign _zz_274_ = _zz_135_[16 : 16]; + assign _zz_275_ = _zz_135_[17 : 17]; + assign _zz_276_ = _zz_135_[18 : 18]; + assign _zz_277_ = _zz_135_[19 : 19]; + assign _zz_278_ = _zz_135_[20 : 20]; + assign _zz_279_ = _zz_135_[21 : 21]; + assign _zz_280_ = _zz_135_[24 : 24]; + assign _zz_281_ = _zz_135_[26 : 26]; + assign _zz_282_ = _zz_135_[29 : 29]; + assign _zz_283_ = execute_SRC_LESS; + assign _zz_284_ = (3'b100); + assign _zz_285_ = execute_INSTRUCTION[19 : 15]; + assign _zz_286_ = execute_INSTRUCTION[31 : 20]; + assign _zz_287_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_288_ = ($signed(_zz_289_) + $signed(_zz_292_)); + assign _zz_289_ = ($signed(_zz_290_) + $signed(_zz_291_)); + assign _zz_290_ = execute_SRC1; + assign _zz_291_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_292_ = (execute_SRC_USE_SUB_LESS ? _zz_293_ : _zz_294_); + assign _zz_293_ = (32'b00000000000000000000000000000001); + assign _zz_294_ = (32'b00000000000000000000000000000000); + assign _zz_295_ = (_zz_296_ >>> 1); + assign _zz_296_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz_297_ = execute_INSTRUCTION[31 : 20]; + assign _zz_298_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_299_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_300_ = {_zz_174_,execute_INSTRUCTION[31 : 20]}; + assign _zz_301_ = {{_zz_176_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_302_ = {{_zz_178_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_303_ = execute_INSTRUCTION[31 : 20]; + assign _zz_304_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_305_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_306_ = (3'b100); + assign _zz_307_ = (_zz_189_ & (~ _zz_308_)); + assign _zz_308_ = (_zz_189_ - (2'b01)); + assign _zz_309_ = (_zz_191_ & (~ _zz_310_)); + assign _zz_310_ = (_zz_191_ - (2'b01)); + assign _zz_311_ = memory_MulDivIterativePlugin_mul_counter_willIncrement; + assign _zz_312_ = {5'd0, _zz_311_}; + assign _zz_313_ = (_zz_315_ + _zz_317_); + assign _zz_314_ = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : (33'b000000000000000000000000000000000)); + assign _zz_315_ = {{1{_zz_314_[32]}}, _zz_314_}; + assign _zz_316_ = _zz_318_; + assign _zz_317_ = {{1{_zz_316_[32]}}, _zz_316_}; + assign _zz_318_ = (memory_MulDivIterativePlugin_accumulator >>> 32); + assign _zz_319_ = memory_MulDivIterativePlugin_div_counter_willIncrement; + assign _zz_320_ = {5'd0, _zz_319_}; + assign _zz_321_ = {1'd0, memory_MulDivIterativePlugin_rs2}; + assign _zz_322_ = {_zz_193_,(! _zz_195_[32])}; + assign _zz_323_ = _zz_195_[31:0]; + assign _zz_324_ = _zz_194_[31:0]; + assign _zz_325_ = _zz_326_; + assign _zz_326_ = _zz_327_; + assign _zz_327_ = ({1'b0,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_196_) : _zz_196_)} + _zz_329_); + assign _zz_328_ = memory_MulDivIterativePlugin_div_needRevert; + assign _zz_329_ = {32'd0, _zz_328_}; + assign _zz_330_ = _zz_198_; + assign _zz_331_ = {32'd0, _zz_330_}; + assign _zz_332_ = _zz_197_; + assign _zz_333_ = {31'd0, _zz_332_}; + assign _zz_334_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_335_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_336_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_337_ = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_338_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_339_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_340_ = (iBus_cmd_payload_address >>> 5); + assign _zz_341_ = ({3'd0,_zz_204_} <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + assign _zz_342_ = 1'b1; + assign _zz_343_ = 1'b1; + assign _zz_344_ = {_zz_104_,{_zz_106_,_zz_105_}}; + assign _zz_345_ = decode_INSTRUCTION[31]; + assign _zz_346_ = decode_INSTRUCTION[31]; + assign _zz_347_ = decode_INSTRUCTION[7]; + assign _zz_348_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000010100)) == (32'b00000000000000000000000000000100)); + assign _zz_349_ = ((decode_INSTRUCTION & _zz_356_) == (32'b00000000000000000000000000000100)); + assign _zz_350_ = _zz_141_; + assign _zz_351_ = ((decode_INSTRUCTION & _zz_357_) == (32'b00000010000000000100000000100000)); + assign _zz_352_ = (1'b0); + assign _zz_353_ = ({_zz_358_,{_zz_359_,_zz_360_}} != (3'b000)); + assign _zz_354_ = ({_zz_361_,_zz_362_} != (2'b00)); + assign _zz_355_ = {(_zz_363_ != _zz_364_),{_zz_365_,{_zz_366_,_zz_367_}}}; + assign _zz_356_ = (32'b00000000000000000000000001000100); + assign _zz_357_ = (32'b00000010000000000100000001100100); + assign _zz_358_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000001000000)); + assign _zz_359_ = ((decode_INSTRUCTION & _zz_368_) == (32'b00000000000000000000000001000000)); + assign _zz_360_ = ((decode_INSTRUCTION & _zz_369_) == (32'b00000000000000000000000000000000)); + assign _zz_361_ = _zz_140_; + assign _zz_362_ = _zz_139_; + assign _zz_363_ = {_zz_136_,(_zz_370_ == _zz_371_)}; + assign _zz_364_ = (2'b00); + assign _zz_365_ = ({_zz_136_,_zz_372_} != (2'b00)); + assign _zz_366_ = ({_zz_373_,_zz_374_} != (3'b000)); + assign _zz_367_ = {(_zz_375_ != _zz_376_),{_zz_377_,{_zz_378_,_zz_379_}}}; + assign _zz_368_ = (32'b00000000000000000011000001000000); + assign _zz_369_ = (32'b00000000000000000000000000111000); + assign _zz_370_ = (decode_INSTRUCTION & (32'b00000000000000000000000001110000)); + assign _zz_371_ = (32'b00000000000000000000000000100000); + assign _zz_372_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000000000)); + assign _zz_373_ = ((decode_INSTRUCTION & _zz_380_) == (32'b00000000000000000000000001000000)); + assign _zz_374_ = {(_zz_381_ == _zz_382_),(_zz_383_ == _zz_384_)}; + assign _zz_375_ = ((decode_INSTRUCTION & _zz_385_) == (32'b00000000000000000000000000100000)); + assign _zz_376_ = (1'b0); + assign _zz_377_ = ((_zz_386_ == _zz_387_) != (1'b0)); + assign _zz_378_ = ({_zz_388_,_zz_389_} != (2'b00)); + assign _zz_379_ = {(_zz_390_ != _zz_391_),{_zz_392_,{_zz_393_,_zz_394_}}}; + assign _zz_380_ = (32'b00000000000000000000000001000100); + assign _zz_381_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010100)); + assign _zz_382_ = (32'b00000000000000000010000000010000); + assign _zz_383_ = (decode_INSTRUCTION & (32'b01000000000000000100000000110100)); + assign _zz_384_ = (32'b01000000000000000000000000110000); + assign _zz_385_ = (32'b00000000000000000000000000100000); + assign _zz_386_ = (decode_INSTRUCTION & (32'b00000000000000000001000001001000)); + assign _zz_387_ = (32'b00000000000000000001000000001000); + assign _zz_388_ = ((decode_INSTRUCTION & _zz_395_) == (32'b00000000000000000000000000100000)); + assign _zz_389_ = ((decode_INSTRUCTION & _zz_396_) == (32'b00000000000000000000000000100000)); + assign _zz_390_ = {_zz_138_,{_zz_397_,{_zz_398_,_zz_399_}}}; + assign _zz_391_ = (6'b000000); + assign _zz_392_ = ({_zz_400_,_zz_401_} != (2'b00)); + assign _zz_393_ = ({_zz_402_,_zz_403_} != (4'b0000)); + assign _zz_394_ = {(_zz_404_ != _zz_405_),{_zz_406_,{_zz_407_,_zz_408_}}}; + assign _zz_395_ = (32'b00000000000000000000000000110100); + assign _zz_396_ = (32'b00000000000000000000000001100100); + assign _zz_397_ = ((decode_INSTRUCTION & _zz_409_) == (32'b00000000000000000001000000010000)); + assign _zz_398_ = (_zz_410_ == _zz_411_); + assign _zz_399_ = {_zz_412_,{_zz_413_,_zz_414_}}; + assign _zz_400_ = ((decode_INSTRUCTION & _zz_415_) == (32'b00000000000000000010000000000000)); + assign _zz_401_ = ((decode_INSTRUCTION & _zz_416_) == (32'b00000000000000000001000000000000)); + assign _zz_402_ = (_zz_417_ == _zz_418_); + assign _zz_403_ = {_zz_419_,{_zz_420_,_zz_421_}}; + assign _zz_404_ = (_zz_422_ == _zz_423_); + assign _zz_405_ = (1'b0); + assign _zz_406_ = ({_zz_424_,_zz_425_} != (2'b00)); + assign _zz_407_ = (_zz_426_ != _zz_427_); + assign _zz_408_ = {_zz_428_,{_zz_429_,_zz_430_}}; + assign _zz_409_ = (32'b00000000000000000001000000010000); + assign _zz_410_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010000)); + assign _zz_411_ = (32'b00000000000000000010000000010000); + assign _zz_412_ = ((decode_INSTRUCTION & _zz_431_) == (32'b00000000000000000000000000010000)); + assign _zz_413_ = (_zz_432_ == _zz_433_); + assign _zz_414_ = (_zz_434_ == _zz_435_); + assign _zz_415_ = (32'b00000000000000000010000000010000); + assign _zz_416_ = (32'b00000000000000000101000000000000); + assign _zz_417_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); + assign _zz_418_ = (32'b00000000000000000000000000000000); + assign _zz_419_ = ((decode_INSTRUCTION & _zz_436_) == (32'b00000000000000000000000000000000)); + assign _zz_420_ = (_zz_437_ == _zz_438_); + assign _zz_421_ = (_zz_439_ == _zz_440_); + assign _zz_422_ = (decode_INSTRUCTION & (32'b00000000000000000011000001010000)); + assign _zz_423_ = (32'b00000000000000000000000001010000); + assign _zz_424_ = _zz_138_; + assign _zz_425_ = (_zz_441_ == _zz_442_); + assign _zz_426_ = (_zz_443_ == _zz_444_); + assign _zz_427_ = (1'b0); + assign _zz_428_ = (_zz_445_ != (1'b0)); + assign _zz_429_ = (_zz_446_ != _zz_447_); + assign _zz_430_ = {_zz_448_,{_zz_449_,_zz_450_}}; + assign _zz_431_ = (32'b00000000000000000000000001010000); + assign _zz_432_ = (decode_INSTRUCTION & (32'b00000000000000000000000000001100)); + assign _zz_433_ = (32'b00000000000000000000000000000100); + assign _zz_434_ = (decode_INSTRUCTION & (32'b00000000000000000000000000101000)); + assign _zz_435_ = (32'b00000000000000000000000000000000); + assign _zz_436_ = (32'b00000000000000000000000000011000); + assign _zz_437_ = (decode_INSTRUCTION & (32'b00000000000000000110000000000100)); + assign _zz_438_ = (32'b00000000000000000010000000000000); + assign _zz_439_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000100)); + assign _zz_440_ = (32'b00000000000000000001000000000000); + assign _zz_441_ = (decode_INSTRUCTION & (32'b00000000000000000000000000011100)); + assign _zz_442_ = (32'b00000000000000000000000000000100); + assign _zz_443_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000)); + assign _zz_444_ = (32'b00000000000000000000000001000000); + assign _zz_445_ = ((decode_INSTRUCTION & (32'b00000010000000000100000001110100)) == (32'b00000010000000000000000000110000)); + assign _zz_446_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000000000)) == (32'b00000000000000000001000000000000)); + assign _zz_447_ = (1'b0); + assign _zz_448_ = (_zz_137_ != (1'b0)); + assign _zz_449_ = ({_zz_451_,{_zz_452_,_zz_453_}} != (3'b000)); + assign _zz_450_ = {({_zz_454_,_zz_455_} != (2'b00)),{(_zz_456_ != _zz_457_),{_zz_458_,{_zz_459_,_zz_460_}}}}; + assign _zz_451_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001100100)) == (32'b00000000000000000000000000100100)); + assign _zz_452_ = ((decode_INSTRUCTION & _zz_461_) == (32'b00000000000000000001000000010000)); + assign _zz_453_ = ((decode_INSTRUCTION & _zz_462_) == (32'b00000000000000000001000000010000)); + assign _zz_454_ = ((decode_INSTRUCTION & _zz_463_) == (32'b00000000000000000110000000010000)); + assign _zz_455_ = ((decode_INSTRUCTION & _zz_464_) == (32'b00000000000000000100000000010000)); + assign _zz_456_ = ((decode_INSTRUCTION & _zz_465_) == (32'b00000000000000000010000000010000)); + assign _zz_457_ = (1'b0); + assign _zz_458_ = ({_zz_466_,_zz_467_} != (2'b00)); + assign _zz_459_ = ({_zz_468_,_zz_469_} != (3'b000)); + assign _zz_460_ = {(_zz_470_ != _zz_471_),{_zz_472_,{_zz_473_,_zz_474_}}}; + assign _zz_461_ = (32'b00000000000000000011000000110100); + assign _zz_462_ = (32'b00000010000000000011000001010100); + assign _zz_463_ = (32'b00000000000000000110000000010100); + assign _zz_464_ = (32'b00000000000000000101000000010100); + assign _zz_465_ = (32'b00000000000000000110000000010100); + assign _zz_466_ = ((decode_INSTRUCTION & (32'b00000000000000000111000000110100)) == (32'b00000000000000000101000000010000)); + assign _zz_467_ = ((decode_INSTRUCTION & (32'b00000010000000000111000001100100)) == (32'b00000000000000000101000000100000)); + assign _zz_468_ = ((decode_INSTRUCTION & _zz_475_) == (32'b01000000000000000001000000010000)); + assign _zz_469_ = {(_zz_476_ == _zz_477_),(_zz_478_ == _zz_479_)}; + assign _zz_470_ = {_zz_136_,{_zz_480_,_zz_481_}}; + assign _zz_471_ = (3'b000); + assign _zz_472_ = ((_zz_482_ == _zz_483_) != (1'b0)); + assign _zz_473_ = ({_zz_484_,_zz_485_} != (2'b00)); + assign _zz_474_ = (_zz_486_ != (1'b0)); + assign _zz_475_ = (32'b01000000000000000011000001010100); + assign _zz_476_ = (decode_INSTRUCTION & (32'b00000000000000000111000000110100)); + assign _zz_477_ = (32'b00000000000000000001000000010000); + assign _zz_478_ = (decode_INSTRUCTION & (32'b00000010000000000111000001010100)); + assign _zz_479_ = (32'b00000000000000000001000000010000); + assign _zz_480_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000110000)) == (32'b00000000000000000000000000010000)); + assign _zz_481_ = ((decode_INSTRUCTION & (32'b00000010000000000000000001100000)) == (32'b00000000000000000000000000100000)); + assign _zz_482_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000)); + assign _zz_483_ = (32'b00000000000000000000000000000000); + assign _zz_484_ = ((decode_INSTRUCTION & (32'b00000000000000000001000001010000)) == (32'b00000000000000000001000001010000)); + assign _zz_485_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001010000)) == (32'b00000000000000000010000001010000)); + assign _zz_486_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000010000)) == (32'b00000000000000000000000000010000)); + assign _zz_487_ = (32'b00000000000000000001000001111111); + assign _zz_488_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111)); + assign _zz_489_ = (32'b00000000000000000010000001110011); + assign _zz_490_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011)); + assign _zz_491_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011)); + assign _zz_492_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_493_) == (32'b00000000000000000000000000000011)),{(_zz_494_ == _zz_495_),{_zz_496_,{_zz_497_,_zz_498_}}}}}}; + assign _zz_493_ = (32'b00000000000000000101000001011111); + assign _zz_494_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011)); + assign _zz_495_ = (32'b00000000000000000000000001100011); + assign _zz_496_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111)); + assign _zz_497_ = ((decode_INSTRUCTION & (32'b11111100000000000000000001111111)) == (32'b00000000000000000000000000110011)); + assign _zz_498_ = {((decode_INSTRUCTION & (32'b11111100000000000011000001011111)) == (32'b00000000000000000001000000010011)),{((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & _zz_499_) == (32'b00000000000000000101000000110011)),{(_zz_500_ == _zz_501_),(_zz_502_ == _zz_503_)}}}}; + assign _zz_499_ = (32'b10111110000000000111000001111111); + assign _zz_500_ = (decode_INSTRUCTION & (32'b10111110000000000111000001111111)); + assign _zz_501_ = (32'b00000000000000000000000000110011); + assign _zz_502_ = (decode_INSTRUCTION & (32'b11011111111111111111111111111111)); + assign _zz_503_ = (32'b00010000001000000000000001110011); + assign _zz_504_ = execute_INSTRUCTION[31]; + assign _zz_505_ = execute_INSTRUCTION[31]; + assign _zz_506_ = execute_INSTRUCTION[7]; + always @ (posedge clk) begin + if(_zz_52_) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_342_) begin + _zz_214_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge clk) begin + if(_zz_343_) begin + _zz_215_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + InstructionCache IBusCachedPlugin_cache ( + .io_flush(_zz_205_), + .io_cpu_prefetch_isValid(_zz_206_), + .io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt), + .io_cpu_prefetch_pc(IBusCachedPlugin_iBusRsp_stages_0_input_payload), + .io_cpu_fetch_isValid(_zz_207_), + .io_cpu_fetch_isStuck(_zz_208_), + .io_cpu_fetch_isRemoved(IBusCachedPlugin_fetcherflushIt), + .io_cpu_fetch_pc(IBusCachedPlugin_iBusRsp_stages_1_input_payload), + .io_cpu_fetch_data(IBusCachedPlugin_cache_io_cpu_fetch_data), + .io_cpu_fetch_dataBypassValid(IBusCachedPlugin_s1_tightlyCoupledHit), + .io_cpu_fetch_dataBypass(_zz_209_), + .io_cpu_fetch_mmuBus_cmd_isValid(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid), + .io_cpu_fetch_mmuBus_cmd_virtualAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress), + .io_cpu_fetch_mmuBus_cmd_bypassTranslation(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation), + .io_cpu_fetch_mmuBus_rsp_physicalAddress(IBusCachedPlugin_mmuBus_rsp_physicalAddress), + .io_cpu_fetch_mmuBus_rsp_isIoAccess(IBusCachedPlugin_mmuBus_rsp_isIoAccess), + .io_cpu_fetch_mmuBus_rsp_allowRead(IBusCachedPlugin_mmuBus_rsp_allowRead), + .io_cpu_fetch_mmuBus_rsp_allowWrite(IBusCachedPlugin_mmuBus_rsp_allowWrite), + .io_cpu_fetch_mmuBus_rsp_allowExecute(IBusCachedPlugin_mmuBus_rsp_allowExecute), + .io_cpu_fetch_mmuBus_rsp_exception(IBusCachedPlugin_mmuBus_rsp_exception), + .io_cpu_fetch_mmuBus_rsp_refilling(IBusCachedPlugin_mmuBus_rsp_refilling), + .io_cpu_fetch_mmuBus_end(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end), + .io_cpu_fetch_mmuBus_busy(IBusCachedPlugin_mmuBus_busy), + .io_cpu_fetch_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), + .io_cpu_fetch_haltIt(IBusCachedPlugin_cache_io_cpu_fetch_haltIt), + .io_cpu_decode_isValid(_zz_210_), + .io_cpu_decode_isStuck(_zz_211_), + .io_cpu_decode_pc(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload), + .io_cpu_decode_physicalAddress(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), + .io_cpu_decode_data(IBusCachedPlugin_cache_io_cpu_decode_data), + .io_cpu_decode_cacheMiss(IBusCachedPlugin_cache_io_cpu_decode_cacheMiss), + .io_cpu_decode_error(IBusCachedPlugin_cache_io_cpu_decode_error), + .io_cpu_decode_mmuRefilling(IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling), + .io_cpu_decode_mmuException(IBusCachedPlugin_cache_io_cpu_decode_mmuException), + .io_cpu_decode_isUser(_zz_212_), + .io_cpu_fill_valid(_zz_213_), + .io_cpu_fill_payload(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), + .io_mem_cmd_valid(IBusCachedPlugin_cache_io_mem_cmd_valid), + .io_mem_cmd_ready(iBus_cmd_ready), + .io_mem_cmd_payload_address(IBusCachedPlugin_cache_io_mem_cmd_payload_address), + .io_mem_cmd_payload_size(IBusCachedPlugin_cache_io_mem_cmd_payload_size), + .io_mem_rsp_valid(iBus_rsp_valid), + .io_mem_rsp_payload_data(iBus_rsp_payload_data), + .io_mem_rsp_payload_error(iBus_rsp_payload_error), + .clk(clk), + .reset(reset) + ); + always @(*) begin + case(_zz_344_) + 3'b000 : begin + _zz_216_ = CsrPlugin_jumpInterface_payload; + end + 3'b001 : begin + _zz_216_ = DBusSimplePlugin_redoBranch_payload; + end + 3'b010 : begin + _zz_216_ = BranchPlugin_jumpInterface_payload; + end + 3'b011 : begin + _zz_216_ = IBusCachedPlugin_redoBranch_payload; + end + default : begin + _zz_216_ = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_1_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_1__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_1__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_1__string = "BITWISE "; + default : _zz_1__string = "????????"; + endcase + end + always @(*) begin + case(_zz_2_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_2__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_2__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_2__string = "BITWISE "; + default : _zz_2__string = "????????"; + endcase + end + always @(*) begin + case(_zz_3_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_3__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_3__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_3__string = "BITWISE "; + default : _zz_3__string = "????????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_4_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_4__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_4__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_4__string = "AND_1"; + default : _zz_4__string = "?????"; + endcase + end + always @(*) begin + case(_zz_5_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_5__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_5__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_5__string = "AND_1"; + default : _zz_5__string = "?????"; + endcase + end + always @(*) begin + case(_zz_6_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_6__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_6__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_6__string = "AND_1"; + default : _zz_6__string = "?????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_7_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_7__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_7__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_7__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_7__string = "PC "; + default : _zz_7__string = "???"; + endcase + end + always @(*) begin + case(_zz_8_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_8__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_8__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_8__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_8__string = "PC "; + default : _zz_8__string = "???"; + endcase + end + always @(*) begin + case(_zz_9_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_9__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_9__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_9__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_9__string = "PC "; + default : _zz_9__string = "???"; + endcase + end + always @(*) begin + case(_zz_10_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_10__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_10__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_10__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_10__string = "JALR"; + default : _zz_10__string = "????"; + endcase + end + always @(*) begin + case(_zz_11_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_11__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_11__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_11__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_11__string = "JALR"; + default : _zz_11__string = "????"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_12_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_12__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_12__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_12__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_12__string = "URS1 "; + default : _zz_12__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_13_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_13__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_13__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_13__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_13__string = "URS1 "; + default : _zz_13__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_14_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_14__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_14__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_14__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_14__string = "URS1 "; + default : _zz_14__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_15_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_15__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_15__string = "XRET"; + default : _zz_15__string = "????"; + endcase + end + always @(*) begin + case(_zz_16_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_16__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_16__string = "XRET"; + default : _zz_16__string = "????"; + endcase + end + always @(*) begin + case(_zz_17_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_17__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_17__string = "XRET"; + default : _zz_17__string = "????"; + endcase + end + always @(*) begin + case(_zz_18_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_18__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_18__string = "XRET"; + default : _zz_18__string = "????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET"; + default : decode_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_19_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_19__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_19__string = "XRET"; + default : _zz_19__string = "????"; + endcase + end + always @(*) begin + case(_zz_20_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_20__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_20__string = "XRET"; + default : _zz_20__string = "????"; + endcase + end + always @(*) begin + case(_zz_21_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_21__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_21__string = "XRET"; + default : _zz_21__string = "????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_22_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_22__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_22__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_22__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_22__string = "SRA_1 "; + default : _zz_22__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_23_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_23__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_23__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_23__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_23__string = "SRA_1 "; + default : _zz_23__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_24_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_24__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_24__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_24__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_24__string = "SRA_1 "; + default : _zz_24__string = "?????????"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET"; + default : memory_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_25_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_25__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_25__string = "XRET"; + default : _zz_25__string = "????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET"; + default : execute_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_26_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_26__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_26__string = "XRET"; + default : _zz_26__string = "????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET"; + default : writeBack_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_29_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_29__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_29__string = "XRET"; + default : _zz_29__string = "????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_32_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_32__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_32__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_32__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_32__string = "JALR"; + default : _zz_32__string = "????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_37_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_37__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_37__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_37__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_37__string = "SRA_1 "; + default : _zz_37__string = "?????????"; + endcase + end + always @(*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_42_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_42__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_42__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_42__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_42__string = "PC "; + default : _zz_42__string = "???"; + endcase + end + always @(*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_44_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_44__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_44__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_44__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_44__string = "URS1 "; + default : _zz_44__string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_47_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_47__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_47__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_47__string = "BITWISE "; + default : _zz_47__string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_49_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_49__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_49__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_49__string = "AND_1"; + default : _zz_49__string = "?????"; + endcase + end + always @(*) begin + case(_zz_56_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_56__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_56__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_56__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_56__string = "URS1 "; + default : _zz_56__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_59_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_59__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_59__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_59__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_59__string = "PC "; + default : _zz_59__string = "???"; + endcase + end + always @(*) begin + case(_zz_67_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_67__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_67__string = "XRET"; + default : _zz_67__string = "????"; + endcase + end + always @(*) begin + case(_zz_68_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_68__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_68__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_68__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_68__string = "JALR"; + default : _zz_68__string = "????"; + endcase + end + always @(*) begin + case(_zz_70_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_70__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_70__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_70__string = "AND_1"; + default : _zz_70__string = "?????"; + endcase + end + always @(*) begin + case(_zz_72_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_72__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_72__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_72__string = "BITWISE "; + default : _zz_72__string = "????????"; + endcase + end + always @(*) begin + case(_zz_73_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_73__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_73__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_73__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_73__string = "SRA_1 "; + default : _zz_73__string = "?????????"; + endcase + end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_95_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_95__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_95__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_95__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_95__string = "JALR"; + default : _zz_95__string = "????"; + endcase + end + always @(*) begin + case(_zz_142_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_142__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_142__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_142__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_142__string = "SRA_1 "; + default : _zz_142__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_143_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_143__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_143__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_143__string = "BITWISE "; + default : _zz_143__string = "????????"; + endcase + end + always @(*) begin + case(_zz_144_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_144__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_144__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_144__string = "AND_1"; + default : _zz_144__string = "?????"; + endcase + end + always @(*) begin + case(_zz_145_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_145__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_145__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_145__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_145__string = "JALR"; + default : _zz_145__string = "????"; + endcase + end + always @(*) begin + case(_zz_146_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_146__string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_146__string = "XRET"; + default : _zz_146__string = "????"; + endcase + end + always @(*) begin + case(_zz_147_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_147__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_147__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_147__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_147__string = "PC "; + default : _zz_147__string = "???"; + endcase + end + always @(*) begin + case(_zz_148_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_148__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_148__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_148__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_148__string = "URS1 "; + default : _zz_148__string = "????????????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET"; + default : decode_to_execute_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET"; + default : execute_to_memory_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE"; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET"; + default : memory_to_writeBack_ENV_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + `endif + + assign decode_ALU_CTRL = _zz_1_; + assign _zz_2_ = _zz_3_; + assign decode_ALU_BITWISE_CTRL = _zz_4_; + assign _zz_5_ = _zz_6_; + assign decode_SRC2_CTRL = _zz_7_; + assign _zz_8_ = _zz_9_; + assign decode_IS_RS2_SIGNED = _zz_58_; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_74_; + assign decode_IS_RS1_SIGNED = _zz_55_; + assign decode_CSR_READ_OPCODE = _zz_27_; + assign decode_IS_DIV = _zz_57_; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = _zz_89_; + assign decode_IS_MUL = _zz_69_; + assign execute_BRANCH_CALC = _zz_30_; + assign _zz_10_ = _zz_11_; + assign decode_SRC1_CTRL = _zz_12_; + assign _zz_13_ = _zz_14_; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_77_; + assign decode_SRC2_FORCE_ZERO = _zz_46_; + assign decode_CSR_WRITE_OPCODE = _zz_28_; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign execute_REGFILE_WRITE_DATA = _zz_48_; + assign execute_BRANCH_DO = _zz_31_; + assign decode_SRC_LESS_UNSIGNED = _zz_65_; + assign _zz_15_ = _zz_16_; + assign _zz_17_ = _zz_18_; + assign decode_ENV_CTRL = _zz_19_; + assign _zz_20_ = _zz_21_; + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = _zz_98_; + assign decode_MEMORY_STORE = _zz_61_; + assign decode_PREDICTION_HAD_BRANCHED2 = _zz_34_; + assign decode_IS_CSR = _zz_76_; + assign decode_SHIFT_CTRL = _zz_22_; + assign _zz_23_ = _zz_24_; + assign memory_MEMORY_READ_DATA = _zz_80_; + assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; + assign execute_IS_DIV = decode_to_execute_IS_DIV; + assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; + assign memory_IS_DIV = execute_to_memory_IS_DIV; + assign memory_IS_MUL = execute_to_memory_IS_MUL; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_25_; + assign execute_ENV_CTRL = _zz_26_; + assign writeBack_ENV_CTRL = _zz_29_; + assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; + assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; + assign execute_PC = decode_to_execute_PC; + assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; + assign execute_RS1 = decode_to_execute_RS1; + assign execute_BRANCH_COND_RESULT = _zz_33_; + assign execute_BRANCH_CTRL = _zz_32_; + assign decode_RS2_USE = _zz_63_; + assign decode_RS1_USE = _zz_66_; + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + always @ (*) begin + _zz_35_ = memory_REGFILE_WRITE_DATA; + if(_zz_217_)begin + _zz_35_ = ((memory_INSTRUCTION[13 : 12] == (2'b00)) ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_accumulator[63 : 32]); + end + if(_zz_218_)begin + _zz_35_ = memory_MulDivIterativePlugin_div_result; + end + end + + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + decode_RS2 = _zz_53_; + if(_zz_161_)begin + if((_zz_162_ == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_163_; + end + end + if(_zz_219_)begin + if(_zz_220_)begin + if(_zz_165_)begin + decode_RS2 = _zz_79_; + end + end + end + if(_zz_221_)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_167_)begin + decode_RS2 = _zz_35_; + end + end + end + if(_zz_222_)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_169_)begin + decode_RS2 = _zz_36_; + end + end + end + end + + always @ (*) begin + decode_RS1 = _zz_54_; + if(_zz_161_)begin + if((_zz_162_ == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_163_; + end + end + if(_zz_219_)begin + if(_zz_220_)begin + if(_zz_164_)begin + decode_RS1 = _zz_79_; + end + end + end + if(_zz_221_)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_166_)begin + decode_RS1 = _zz_35_; + end + end + end + if(_zz_222_)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_168_)begin + decode_RS1 = _zz_36_; + end + end + end + end + + always @ (*) begin + _zz_36_ = execute_REGFILE_WRITE_DATA; + if(_zz_223_)begin + _zz_36_ = _zz_157_; + end + if(_zz_224_)begin + _zz_36_ = execute_CsrPlugin_readData; + end + end + + assign execute_SHIFT_CTRL = _zz_37_; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_41_ = execute_PC; + assign execute_SRC2_CTRL = _zz_42_; + assign execute_SRC1_CTRL = _zz_44_; + assign decode_SRC_USE_SUB_LESS = _zz_60_; + assign decode_SRC_ADD_ZERO = _zz_71_; + assign execute_SRC_ADD_SUB = _zz_40_; + assign execute_SRC_LESS = _zz_38_; + assign execute_ALU_CTRL = _zz_47_; + assign execute_SRC2 = _zz_43_; + assign execute_SRC1 = _zz_45_; + assign execute_ALU_BITWISE_CTRL = _zz_49_; + assign _zz_50_ = writeBack_INSTRUCTION; + assign _zz_51_ = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_52_ = 1'b0; + if(lastStageRegFileWrite_valid)begin + _zz_52_ = 1'b1; + end + end + + assign decode_INSTRUCTION_ANTICIPATED = _zz_94_; + always @ (*) begin + decode_REGFILE_WRITE_VALID = _zz_64_; + if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + assign decode_LEGAL_INSTRUCTION = _zz_78_; + assign decode_INSTRUCTION_READY = 1'b1; + assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; + always @ (*) begin + _zz_79_ = writeBack_REGFILE_WRITE_DATA; + if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin + _zz_79_ = writeBack_DBusSimplePlugin_rspFormated; + end + end + + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; + assign memory_MMU_FAULT = execute_to_memory_MMU_FAULT; + assign memory_MMU_RSP_physicalAddress = execute_to_memory_MMU_RSP_physicalAddress; + assign memory_MMU_RSP_isIoAccess = execute_to_memory_MMU_RSP_isIoAccess; + assign memory_MMU_RSP_allowRead = execute_to_memory_MMU_RSP_allowRead; + assign memory_MMU_RSP_allowWrite = execute_to_memory_MMU_RSP_allowWrite; + assign memory_MMU_RSP_allowExecute = execute_to_memory_MMU_RSP_allowExecute; + assign memory_MMU_RSP_exception = execute_to_memory_MMU_RSP_exception; + assign memory_MMU_RSP_refilling = execute_to_memory_MMU_RSP_refilling; + assign memory_PC = execute_to_memory_PC; + assign memory_ALIGNEMENT_FAULT = execute_to_memory_ALIGNEMENT_FAULT; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_MMU_FAULT = _zz_88_; + assign execute_MMU_RSP_physicalAddress = _zz_81_; + assign execute_MMU_RSP_isIoAccess = _zz_82_; + assign execute_MMU_RSP_allowRead = _zz_83_; + assign execute_MMU_RSP_allowWrite = _zz_84_; + assign execute_MMU_RSP_allowExecute = _zz_85_; + assign execute_MMU_RSP_exception = _zz_86_; + assign execute_MMU_RSP_refilling = _zz_87_; + assign execute_SRC_ADD = _zz_39_; + assign execute_RS2 = decode_to_execute_RS2; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_ALIGNEMENT_FAULT = _zz_90_; + assign decode_MEMORY_ENABLE = _zz_75_; + assign decode_FLUSH_ALL = _zz_62_; + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected = _zz_91_; + if(_zz_225_)begin + IBusCachedPlugin_rsp_issueDetected = 1'b1; + end + end + + always @ (*) begin + _zz_91_ = _zz_92_; + if(_zz_226_)begin + _zz_91_ = 1'b1; + end + end + + always @ (*) begin + _zz_92_ = _zz_93_; + if(_zz_227_)begin + _zz_92_ = 1'b1; + end + end + + always @ (*) begin + _zz_93_ = 1'b0; + if(_zz_228_)begin + _zz_93_ = 1'b1; + end + end + + assign decode_BRANCH_CTRL = _zz_95_; + assign decode_INSTRUCTION = _zz_99_; + always @ (*) begin + _zz_96_ = memory_FORMAL_PC_NEXT; + if(DBusSimplePlugin_redoBranch_valid)begin + _zz_96_ = DBusSimplePlugin_redoBranch_payload; + end + if(BranchPlugin_jumpInterface_valid)begin + _zz_96_ = BranchPlugin_jumpInterface_payload; + end + end + + always @ (*) begin + _zz_97_ = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid)begin + _zz_97_ = IBusCachedPlugin_predictionJumpInterface_payload; + end + if(IBusCachedPlugin_redoBranch_valid)begin + _zz_97_ = IBusCachedPlugin_redoBranch_payload; + end + end + + assign decode_PC = _zz_100_; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + always @ (*) begin + decode_arbitration_haltItself = 1'b0; + if(((DBusSimplePlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + decode_arbitration_haltItself = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if((decode_arbitration_isValid && (_zz_158_ || _zz_159_)))begin + decode_arbitration_haltByOther = 1'b1; + end + if((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts))begin + decode_arbitration_haltByOther = decode_arbitration_isValid; + end + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != (3'b000)))begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(_zz_229_)begin + decode_arbitration_removeIt = 1'b1; + end + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_flushIt = 1'b0; + always @ (*) begin + decode_arbitration_flushNext = 1'b0; + if(IBusCachedPlugin_redoBranch_valid)begin + decode_arbitration_flushNext = 1'b1; + end + if(_zz_229_)begin + decode_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_haltItself = 1'b0; + if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_128_)))begin + execute_arbitration_haltItself = 1'b1; + end + if(_zz_223_)begin + if(_zz_230_)begin + if(! execute_LightShifterPlugin_done) begin + execute_arbitration_haltItself = 1'b1; + end + end + end + if(_zz_224_)begin + if(execute_CsrPlugin_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + end + + assign execute_arbitration_haltByOther = 1'b0; + always @ (*) begin + execute_arbitration_removeIt = 1'b0; + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + assign execute_arbitration_flushIt = 1'b0; + assign execute_arbitration_flushNext = 1'b0; + always @ (*) begin + memory_arbitration_haltItself = 1'b0; + if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin + memory_arbitration_haltItself = 1'b1; + end + if(_zz_217_)begin + if(_zz_231_)begin + memory_arbitration_haltItself = 1'b1; + end + end + if(_zz_218_)begin + if(_zz_232_)begin + memory_arbitration_haltItself = 1'b1; + end + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @ (*) begin + memory_arbitration_removeIt = 1'b0; + if(_zz_233_)begin + memory_arbitration_removeIt = 1'b1; + end + if(memory_arbitration_isFlushed)begin + memory_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + memory_arbitration_flushIt = 1'b0; + if(DBusSimplePlugin_redoBranch_valid)begin + memory_arbitration_flushIt = 1'b1; + end + end + + always @ (*) begin + memory_arbitration_flushNext = 1'b0; + if(DBusSimplePlugin_redoBranch_valid)begin + memory_arbitration_flushNext = 1'b1; + end + if(BranchPlugin_jumpInterface_valid)begin + memory_arbitration_flushNext = 1'b1; + end + if(_zz_233_)begin + memory_arbitration_flushNext = 1'b1; + end + end + + assign writeBack_arbitration_haltItself = 1'b0; + assign writeBack_arbitration_haltByOther = 1'b0; + always @ (*) begin + writeBack_arbitration_removeIt = 1'b0; + if(writeBack_arbitration_isFlushed)begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + assign writeBack_arbitration_flushIt = 1'b0; + always @ (*) begin + writeBack_arbitration_flushNext = 1'b0; + if(_zz_234_)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_235_)begin + writeBack_arbitration_flushNext = 1'b1; + end + end + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @ (*) begin + IBusCachedPlugin_fetcherHalt = 1'b0; + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != (4'b0000)))begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_234_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_235_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_fetcherflushIt = 1'b0; + if(({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != (4'b0000)))begin + IBusCachedPlugin_fetcherflushIt = 1'b1; + end + if((IBusCachedPlugin_predictionJumpInterface_valid && decode_arbitration_isFiring))begin + IBusCachedPlugin_fetcherflushIt = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_incomingInstruction = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid))begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_valid = 1'b0; + if(_zz_234_)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_235_)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + if(_zz_234_)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)}; + end + if(_zz_235_)begin + case(_zz_236_) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end + end + + assign CsrPlugin_forceMachineWire = 1'b0; + assign CsrPlugin_allowInterrupts = 1'b1; + assign CsrPlugin_allowException = 1'b1; + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,{IBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}}} != (5'b00000)); + assign _zz_101_ = {IBusCachedPlugin_predictionJumpInterface_valid,{IBusCachedPlugin_redoBranch_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}}}; + assign _zz_102_ = (_zz_101_ & (~ _zz_255_)); + assign _zz_103_ = _zz_102_[3]; + assign _zz_104_ = _zz_102_[4]; + assign _zz_105_ = (_zz_102_[1] || _zz_103_); + assign _zz_106_ = (_zz_102_[2] || _zz_103_); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_216_; + always @ (*) begin + IBusCachedPlugin_fetchPc_corrected = 1'b0; + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_corrected = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_257_); + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; + end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + IBusCachedPlugin_fetchPc_pc[1] = 1'b0; + end + + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; + assign IBusCachedPlugin_iBusRsp_stages_0_inputSample = 1'b1; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_107_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_107_); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_107_); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_fetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; + end + end + + assign _zz_108_ = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_108_); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_108_); + assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b0; + if((IBusCachedPlugin_rsp_issueDetected || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; + end + end + + assign _zz_109_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready && _zz_109_); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && _zz_109_); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_110_; + assign _zz_110_ = ((1'b0 && (! _zz_111_)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_111_ = _zz_112_; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_111_; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_113_)) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); + assign _zz_113_ = _zz_114_; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid = _zz_113_; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload = _zz_115_; + always @ (*) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + if((! IBusCachedPlugin_pcValids_0))begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; + assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; + assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; + assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; + assign IBusCachedPlugin_iBusRsp_decodeInput_ready = (! decode_arbitration_isStuck); + assign decode_arbitration_isValid = (IBusCachedPlugin_iBusRsp_decodeInput_valid && (! IBusCachedPlugin_injector_decodeRemoved)); + assign _zz_100_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; + assign _zz_99_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; + assign _zz_98_ = (decode_PC + (32'b00000000000000000000000000000100)); + assign _zz_116_ = _zz_258_[11]; + always @ (*) begin + _zz_117_[18] = _zz_116_; + _zz_117_[17] = _zz_116_; + _zz_117_[16] = _zz_116_; + _zz_117_[15] = _zz_116_; + _zz_117_[14] = _zz_116_; + _zz_117_[13] = _zz_116_; + _zz_117_[12] = _zz_116_; + _zz_117_[11] = _zz_116_; + _zz_117_[10] = _zz_116_; + _zz_117_[9] = _zz_116_; + _zz_117_[8] = _zz_116_; + _zz_117_[7] = _zz_116_; + _zz_117_[6] = _zz_116_; + _zz_117_[5] = _zz_116_; + _zz_117_[4] = _zz_116_; + _zz_117_[3] = _zz_116_; + _zz_117_[2] = _zz_116_; + _zz_117_[1] = _zz_116_; + _zz_117_[0] = _zz_116_; + end + + always @ (*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_259_[31])); + if(_zz_122_)begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; + end + end + + assign _zz_118_ = _zz_260_[19]; + always @ (*) begin + _zz_119_[10] = _zz_118_; + _zz_119_[9] = _zz_118_; + _zz_119_[8] = _zz_118_; + _zz_119_[7] = _zz_118_; + _zz_119_[6] = _zz_118_; + _zz_119_[5] = _zz_118_; + _zz_119_[4] = _zz_118_; + _zz_119_[3] = _zz_118_; + _zz_119_[2] = _zz_118_; + _zz_119_[1] = _zz_118_; + _zz_119_[0] = _zz_118_; + end + + assign _zz_120_ = _zz_261_[11]; + always @ (*) begin + _zz_121_[18] = _zz_120_; + _zz_121_[17] = _zz_120_; + _zz_121_[16] = _zz_120_; + _zz_121_[15] = _zz_120_; + _zz_121_[14] = _zz_120_; + _zz_121_[13] = _zz_120_; + _zz_121_[12] = _zz_120_; + _zz_121_[11] = _zz_120_; + _zz_121_[10] = _zz_120_; + _zz_121_[9] = _zz_120_; + _zz_121_[8] = _zz_120_; + _zz_121_[7] = _zz_120_; + _zz_121_[6] = _zz_120_; + _zz_121_[5] = _zz_120_; + _zz_121_[4] = _zz_120_; + _zz_121_[3] = _zz_120_; + _zz_121_[2] = _zz_120_; + _zz_121_[1] = _zz_120_; + _zz_121_[0] = _zz_120_; + end + + always @ (*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_122_ = _zz_262_[1]; + end + default : begin + _zz_122_ = _zz_263_[1]; + end + endcase + end + + assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); + assign _zz_123_ = _zz_264_[19]; + always @ (*) begin + _zz_124_[10] = _zz_123_; + _zz_124_[9] = _zz_123_; + _zz_124_[8] = _zz_123_; + _zz_124_[7] = _zz_123_; + _zz_124_[6] = _zz_123_; + _zz_124_[5] = _zz_123_; + _zz_124_[4] = _zz_123_; + _zz_124_[3] = _zz_123_; + _zz_124_[2] = _zz_123_; + _zz_124_[1] = _zz_123_; + _zz_124_[0] = _zz_123_; + end + + assign _zz_125_ = _zz_265_[11]; + always @ (*) begin + _zz_126_[18] = _zz_125_; + _zz_126_[17] = _zz_125_; + _zz_126_[16] = _zz_125_; + _zz_126_[15] = _zz_125_; + _zz_126_[14] = _zz_125_; + _zz_126_[13] = _zz_125_; + _zz_126_[12] = _zz_125_; + _zz_126_[11] = _zz_125_; + _zz_126_[10] = _zz_125_; + _zz_126_[9] = _zz_125_; + _zz_126_[8] = _zz_125_; + _zz_126_[7] = _zz_125_; + _zz_126_[6] = _zz_125_; + _zz_126_[5] = _zz_125_; + _zz_126_[4] = _zz_125_; + _zz_126_[3] = _zz_125_; + _zz_126_[2] = _zz_125_; + _zz_126_[1] = _zz_125_; + _zz_126_[0] = _zz_125_; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_124_,{{{_zz_345_,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_126_,{{{_zz_346_,_zz_347_},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @ (*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign _zz_206_ = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_209_ = (32'b00000000000000000000000000000000); + assign _zz_207_ = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_208_ = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_210_ = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_211_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); + assign _zz_212_ = (CsrPlugin_privilege == (2'b00)); + assign _zz_94_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + always @ (*) begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + if(_zz_228_)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(_zz_226_)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(_zz_237_)begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + end + end + + always @ (*) begin + _zz_213_ = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_226_)begin + _zz_213_ = 1'b1; + end + if(_zz_237_)begin + _zz_213_ = 1'b0; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + if(_zz_227_)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + if(_zz_225_)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'bxxxx); + if(_zz_227_)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b1100); + end + if(_zz_225_)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b0001); + end + end + + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload[31 : 2],(2'b00)}; + assign IBusCachedPlugin_redoBranch_valid = IBusCachedPlugin_rsp_redoFetch; + assign IBusCachedPlugin_redoBranch_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + assign IBusCachedPlugin_iBusRsp_decodeInput_valid = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready = IBusCachedPlugin_iBusRsp_decodeInput_ready; + assign IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_decodeInput_payload_pc = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; + assign IBusCachedPlugin_mmuBus_cmd_isValid = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; + assign IBusCachedPlugin_mmuBus_cmd_virtualAddress = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; + assign IBusCachedPlugin_mmuBus_cmd_bypassTranslation = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; + assign IBusCachedPlugin_mmuBus_end = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; + assign _zz_205_ = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_128_ = 1'b0; + assign _zz_90_ = (((dBus_cmd_payload_size == (2'b10)) && (dBus_cmd_payload_address[1 : 0] != (2'b00))) || ((dBus_cmd_payload_size == (2'b01)) && (dBus_cmd_payload_address[0 : 0] != (1'b0)))); + always @ (*) begin + execute_DBusSimplePlugin_skipCmd = 1'b0; + if(execute_ALIGNEMENT_FAULT)begin + execute_DBusSimplePlugin_skipCmd = 1'b1; + end + if((execute_MMU_FAULT || execute_MMU_RSP_refilling))begin + execute_DBusSimplePlugin_skipCmd = 1'b1; + end + end + + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_128_)); + assign dBus_cmd_payload_wr = execute_MEMORY_STORE; + assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_129_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_129_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_129_ = execute_RS2[31 : 0]; + end + endcase + end + + assign dBus_cmd_payload_data = _zz_129_; + assign _zz_89_ = dBus_cmd_payload_address[1 : 0]; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_130_ = (4'b0001); + end + 2'b01 : begin + _zz_130_ = (4'b0011); + end + default : begin + _zz_130_ = (4'b1111); + end + endcase + end + + assign execute_DBusSimplePlugin_formalMask = (_zz_130_ <<< dBus_cmd_payload_address[1 : 0]); + assign DBusSimplePlugin_mmuBus_cmd_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign DBusSimplePlugin_mmuBus_cmd_virtualAddress = execute_SRC_ADD; + assign DBusSimplePlugin_mmuBus_cmd_bypassTranslation = 1'b0; + assign DBusSimplePlugin_mmuBus_end = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress; + assign _zz_88_ = ((execute_MMU_RSP_exception || ((! execute_MMU_RSP_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP_allowRead) && (! execute_MEMORY_STORE))); + assign _zz_81_ = DBusSimplePlugin_mmuBus_rsp_physicalAddress; + assign _zz_82_ = DBusSimplePlugin_mmuBus_rsp_isIoAccess; + assign _zz_83_ = DBusSimplePlugin_mmuBus_rsp_allowRead; + assign _zz_84_ = DBusSimplePlugin_mmuBus_rsp_allowWrite; + assign _zz_85_ = DBusSimplePlugin_mmuBus_rsp_allowExecute; + assign _zz_86_ = DBusSimplePlugin_mmuBus_rsp_exception; + assign _zz_87_ = DBusSimplePlugin_mmuBus_rsp_refilling; + assign _zz_80_ = dBus_rsp_data; + always @ (*) begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; + if(_zz_238_)begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; + end + if(memory_ALIGNEMENT_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; + end + if(memory_MMU_RSP_refilling)begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; + end else begin + if(memory_MMU_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; + end + end + if(_zz_239_)begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; + end + end + + always @ (*) begin + DBusSimplePlugin_memoryExceptionPort_payload_code = (4'bxxxx); + if(_zz_238_)begin + DBusSimplePlugin_memoryExceptionPort_payload_code = (4'b0101); + end + if(memory_ALIGNEMENT_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_266_}; + end + if(! memory_MMU_RSP_refilling) begin + if(memory_MMU_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? (4'b1111) : (4'b1101)); + end + end + end + + assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = memory_REGFILE_WRITE_DATA; + always @ (*) begin + DBusSimplePlugin_redoBranch_valid = 1'b0; + if(memory_MMU_RSP_refilling)begin + DBusSimplePlugin_redoBranch_valid = 1'b1; + end + if(_zz_239_)begin + DBusSimplePlugin_redoBranch_valid = 1'b0; + end + end + + assign DBusSimplePlugin_redoBranch_payload = memory_PC; + always @ (*) begin + writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; + case(writeBack_MEMORY_ADDRESS_LOW) + 2'b01 : begin + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8]; + end + 2'b10 : begin + writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16]; + end + 2'b11 : begin + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24]; + end + default : begin + end + endcase + end + + assign _zz_131_ = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_132_[31] = _zz_131_; + _zz_132_[30] = _zz_131_; + _zz_132_[29] = _zz_131_; + _zz_132_[28] = _zz_131_; + _zz_132_[27] = _zz_131_; + _zz_132_[26] = _zz_131_; + _zz_132_[25] = _zz_131_; + _zz_132_[24] = _zz_131_; + _zz_132_[23] = _zz_131_; + _zz_132_[22] = _zz_131_; + _zz_132_[21] = _zz_131_; + _zz_132_[20] = _zz_131_; + _zz_132_[19] = _zz_131_; + _zz_132_[18] = _zz_131_; + _zz_132_[17] = _zz_131_; + _zz_132_[16] = _zz_131_; + _zz_132_[15] = _zz_131_; + _zz_132_[14] = _zz_131_; + _zz_132_[13] = _zz_131_; + _zz_132_[12] = _zz_131_; + _zz_132_[11] = _zz_131_; + _zz_132_[10] = _zz_131_; + _zz_132_[9] = _zz_131_; + _zz_132_[8] = _zz_131_; + _zz_132_[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_133_ = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_134_[31] = _zz_133_; + _zz_134_[30] = _zz_133_; + _zz_134_[29] = _zz_133_; + _zz_134_[28] = _zz_133_; + _zz_134_[27] = _zz_133_; + _zz_134_[26] = _zz_133_; + _zz_134_[25] = _zz_133_; + _zz_134_[24] = _zz_133_; + _zz_134_[23] = _zz_133_; + _zz_134_[22] = _zz_133_; + _zz_134_[21] = _zz_133_; + _zz_134_[20] = _zz_133_; + _zz_134_[19] = _zz_133_; + _zz_134_[18] = _zz_133_; + _zz_134_[17] = _zz_133_; + _zz_134_[16] = _zz_133_; + _zz_134_[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_253_) + 2'b00 : begin + writeBack_DBusSimplePlugin_rspFormated = _zz_132_; + end + 2'b01 : begin + writeBack_DBusSimplePlugin_rspFormated = _zz_134_; + end + default : begin + writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; + end + endcase + end + + assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_virtualAddress; + assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign IBusCachedPlugin_mmuBus_busy = 1'b0; + assign DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_virtualAddress; + assign DBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; + assign DBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; + assign DBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1; + assign DBusSimplePlugin_mmuBus_rsp_isIoAccess = DBusSimplePlugin_mmuBus_rsp_physicalAddress[31]; + assign DBusSimplePlugin_mmuBus_rsp_exception = 1'b0; + assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; + assign DBusSimplePlugin_mmuBus_busy = 1'b0; + assign _zz_136_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); + assign _zz_137_ = ((decode_INSTRUCTION & (32'b00000000000000000011000000000000)) == (32'b00000000000000000010000000000000)); + assign _zz_138_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000)); + assign _zz_139_ = ((decode_INSTRUCTION & (32'b00000000000000000111000000000000)) == (32'b00000000000000000001000000000000)); + assign _zz_140_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000000)) == (32'b00000000000000000100000000000000)); + assign _zz_141_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); + assign _zz_135_ = {({_zz_140_,{_zz_137_,_zz_139_}} != (3'b000)),{({_zz_348_,_zz_141_} != (2'b00)),{({_zz_349_,_zz_350_} != (2'b00)),{(_zz_351_ != _zz_352_),{_zz_353_,{_zz_354_,_zz_355_}}}}}}; + assign _zz_78_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_487_) == (32'b00000000000000000001000001110011)),{(_zz_488_ == _zz_489_),{_zz_490_,{_zz_491_,_zz_492_}}}}}}} != (18'b000000000000000000)); + assign _zz_77_ = _zz_267_[0]; + assign _zz_76_ = _zz_268_[0]; + assign _zz_75_ = _zz_269_[0]; + assign _zz_74_ = _zz_270_[0]; + assign _zz_142_ = _zz_135_[5 : 4]; + assign _zz_73_ = _zz_142_; + assign _zz_143_ = _zz_135_[7 : 6]; + assign _zz_72_ = _zz_143_; + assign _zz_71_ = _zz_271_[0]; + assign _zz_144_ = _zz_135_[10 : 9]; + assign _zz_70_ = _zz_144_; + assign _zz_69_ = _zz_272_[0]; + assign _zz_145_ = _zz_135_[13 : 12]; + assign _zz_68_ = _zz_145_; + assign _zz_146_ = _zz_135_[14 : 14]; + assign _zz_67_ = _zz_146_; + assign _zz_66_ = _zz_273_[0]; + assign _zz_65_ = _zz_274_[0]; + assign _zz_64_ = _zz_275_[0]; + assign _zz_63_ = _zz_276_[0]; + assign _zz_62_ = _zz_277_[0]; + assign _zz_61_ = _zz_278_[0]; + assign _zz_60_ = _zz_279_[0]; + assign _zz_147_ = _zz_135_[23 : 22]; + assign _zz_59_ = _zz_147_; + assign _zz_58_ = _zz_280_[0]; + assign _zz_57_ = _zz_281_[0]; + assign _zz_148_ = _zz_135_[28 : 27]; + assign _zz_56_ = _zz_148_; + assign _zz_55_ = _zz_282_[0]; + assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = (4'b0010); + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; + assign decode_RegFilePlugin_rs1Data = _zz_214_; + assign decode_RegFilePlugin_rs2Data = _zz_215_; + assign _zz_54_ = decode_RegFilePlugin_rs1Data; + assign _zz_53_ = decode_RegFilePlugin_rs2Data; + always @ (*) begin + lastStageRegFileWrite_valid = (_zz_51_ && writeBack_arbitration_isFiring); + if(_zz_149_)begin + lastStageRegFileWrite_valid = 1'b1; + end + end + + assign lastStageRegFileWrite_payload_address = _zz_50_[11 : 7]; + assign lastStageRegFileWrite_payload_data = _zz_79_; + always @ (*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @ (*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_150_ = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_150_ = {31'd0, _zz_283_}; + end + default : begin + _zz_150_ = execute_SRC_ADD_SUB; + end + endcase + end + + assign _zz_48_ = _zz_150_; + assign _zz_46_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + always @ (*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_151_ = execute_RS1; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_151_ = {29'd0, _zz_284_}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_151_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)}; + end + default : begin + _zz_151_ = {27'd0, _zz_285_}; + end + endcase + end + + assign _zz_45_ = _zz_151_; + assign _zz_152_ = _zz_286_[11]; + always @ (*) begin + _zz_153_[19] = _zz_152_; + _zz_153_[18] = _zz_152_; + _zz_153_[17] = _zz_152_; + _zz_153_[16] = _zz_152_; + _zz_153_[15] = _zz_152_; + _zz_153_[14] = _zz_152_; + _zz_153_[13] = _zz_152_; + _zz_153_[12] = _zz_152_; + _zz_153_[11] = _zz_152_; + _zz_153_[10] = _zz_152_; + _zz_153_[9] = _zz_152_; + _zz_153_[8] = _zz_152_; + _zz_153_[7] = _zz_152_; + _zz_153_[6] = _zz_152_; + _zz_153_[5] = _zz_152_; + _zz_153_[4] = _zz_152_; + _zz_153_[3] = _zz_152_; + _zz_153_[2] = _zz_152_; + _zz_153_[1] = _zz_152_; + _zz_153_[0] = _zz_152_; + end + + assign _zz_154_ = _zz_287_[11]; + always @ (*) begin + _zz_155_[19] = _zz_154_; + _zz_155_[18] = _zz_154_; + _zz_155_[17] = _zz_154_; + _zz_155_[16] = _zz_154_; + _zz_155_[15] = _zz_154_; + _zz_155_[14] = _zz_154_; + _zz_155_[13] = _zz_154_; + _zz_155_[12] = _zz_154_; + _zz_155_[11] = _zz_154_; + _zz_155_[10] = _zz_154_; + _zz_155_[9] = _zz_154_; + _zz_155_[8] = _zz_154_; + _zz_155_[7] = _zz_154_; + _zz_155_[6] = _zz_154_; + _zz_155_[5] = _zz_154_; + _zz_155_[4] = _zz_154_; + _zz_155_[3] = _zz_154_; + _zz_155_[2] = _zz_154_; + _zz_155_[1] = _zz_154_; + _zz_155_[0] = _zz_154_; + end + + always @ (*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_156_ = execute_RS2; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_156_ = {_zz_153_,execute_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_156_ = {_zz_155_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_156_ = _zz_41_; + end + endcase + end + + assign _zz_43_ = _zz_156_; + always @ (*) begin + execute_SrcPlugin_addSub = _zz_288_; + if(execute_SRC2_FORCE_ZERO)begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign _zz_40_ = execute_SrcPlugin_addSub; + assign _zz_39_ = execute_SrcPlugin_addSub; + assign _zz_38_ = execute_SrcPlugin_less; + assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); + assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); + assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1); + assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == (4'b0000)); + always @ (*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_157_ = (execute_LightShifterPlugin_shiftInput <<< 1); + end + default : begin + _zz_157_ = _zz_295_; + end + endcase + end + + always @ (*) begin + _zz_158_ = 1'b0; + if(_zz_240_)begin + if(_zz_241_)begin + if(_zz_164_)begin + _zz_158_ = 1'b1; + end + end + end + if(_zz_242_)begin + if(_zz_243_)begin + if(_zz_166_)begin + _zz_158_ = 1'b1; + end + end + end + if(_zz_244_)begin + if(_zz_245_)begin + if(_zz_168_)begin + _zz_158_ = 1'b1; + end + end + end + if((! decode_RS1_USE))begin + _zz_158_ = 1'b0; + end + end + + always @ (*) begin + _zz_159_ = 1'b0; + if(_zz_240_)begin + if(_zz_241_)begin + if(_zz_165_)begin + _zz_159_ = 1'b1; + end + end + end + if(_zz_242_)begin + if(_zz_243_)begin + if(_zz_167_)begin + _zz_159_ = 1'b1; + end + end + end + if(_zz_244_)begin + if(_zz_245_)begin + if(_zz_169_)begin + _zz_159_ = 1'b1; + end + end + end + if((! decode_RS2_USE))begin + _zz_159_ = 1'b0; + end + end + + assign _zz_160_ = (_zz_51_ && writeBack_arbitration_isFiring); + assign _zz_164_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_165_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_166_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_167_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_168_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_169_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_34_ = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign _zz_170_ = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_170_ == (3'b000))) begin + _zz_171_ = execute_BranchPlugin_eq; + end else if((_zz_170_ == (3'b001))) begin + _zz_171_ = (! execute_BranchPlugin_eq); + end else if((((_zz_170_ & (3'b101)) == (3'b101)))) begin + _zz_171_ = (! execute_SRC_LESS); + end else begin + _zz_171_ = execute_SRC_LESS; + end + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_172_ = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_172_ = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_172_ = 1'b1; + end + default : begin + _zz_172_ = _zz_171_; + end + endcase + end + + assign _zz_33_ = _zz_172_; + assign _zz_173_ = _zz_297_[11]; + always @ (*) begin + _zz_174_[19] = _zz_173_; + _zz_174_[18] = _zz_173_; + _zz_174_[17] = _zz_173_; + _zz_174_[16] = _zz_173_; + _zz_174_[15] = _zz_173_; + _zz_174_[14] = _zz_173_; + _zz_174_[13] = _zz_173_; + _zz_174_[12] = _zz_173_; + _zz_174_[11] = _zz_173_; + _zz_174_[10] = _zz_173_; + _zz_174_[9] = _zz_173_; + _zz_174_[8] = _zz_173_; + _zz_174_[7] = _zz_173_; + _zz_174_[6] = _zz_173_; + _zz_174_[5] = _zz_173_; + _zz_174_[4] = _zz_173_; + _zz_174_[3] = _zz_173_; + _zz_174_[2] = _zz_173_; + _zz_174_[1] = _zz_173_; + _zz_174_[0] = _zz_173_; + end + + assign _zz_175_ = _zz_298_[19]; + always @ (*) begin + _zz_176_[10] = _zz_175_; + _zz_176_[9] = _zz_175_; + _zz_176_[8] = _zz_175_; + _zz_176_[7] = _zz_175_; + _zz_176_[6] = _zz_175_; + _zz_176_[5] = _zz_175_; + _zz_176_[4] = _zz_175_; + _zz_176_[3] = _zz_175_; + _zz_176_[2] = _zz_175_; + _zz_176_[1] = _zz_175_; + _zz_176_[0] = _zz_175_; + end + + assign _zz_177_ = _zz_299_[11]; + always @ (*) begin + _zz_178_[18] = _zz_177_; + _zz_178_[17] = _zz_177_; + _zz_178_[16] = _zz_177_; + _zz_178_[15] = _zz_177_; + _zz_178_[14] = _zz_177_; + _zz_178_[13] = _zz_177_; + _zz_178_[12] = _zz_177_; + _zz_178_[11] = _zz_177_; + _zz_178_[10] = _zz_177_; + _zz_178_[9] = _zz_177_; + _zz_178_[8] = _zz_177_; + _zz_178_[7] = _zz_177_; + _zz_178_[6] = _zz_177_; + _zz_178_[5] = _zz_177_; + _zz_178_[4] = _zz_177_; + _zz_178_[3] = _zz_177_; + _zz_178_[2] = _zz_177_; + _zz_178_[1] = _zz_177_; + _zz_178_[0] = _zz_177_; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_179_ = (_zz_300_[1] ^ execute_RS1[1]); + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_179_ = _zz_301_[1]; + end + default : begin + _zz_179_ = _zz_302_[1]; + end + endcase + end + + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_179_); + assign _zz_31_ = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src1 = execute_RS1; + end + default : begin + execute_BranchPlugin_branch_src1 = execute_PC; + end + endcase + end + + assign _zz_180_ = _zz_303_[11]; + always @ (*) begin + _zz_181_[19] = _zz_180_; + _zz_181_[18] = _zz_180_; + _zz_181_[17] = _zz_180_; + _zz_181_[16] = _zz_180_; + _zz_181_[15] = _zz_180_; + _zz_181_[14] = _zz_180_; + _zz_181_[13] = _zz_180_; + _zz_181_[12] = _zz_180_; + _zz_181_[11] = _zz_180_; + _zz_181_[10] = _zz_180_; + _zz_181_[9] = _zz_180_; + _zz_181_[8] = _zz_180_; + _zz_181_[7] = _zz_180_; + _zz_181_[6] = _zz_180_; + _zz_181_[5] = _zz_180_; + _zz_181_[4] = _zz_180_; + _zz_181_[3] = _zz_180_; + _zz_181_[2] = _zz_180_; + _zz_181_[1] = _zz_180_; + _zz_181_[0] = _zz_180_; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_181_,execute_INSTRUCTION[31 : 20]}; + end + default : begin + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_183_,{{{_zz_504_,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_185_,{{{_zz_505_,_zz_506_},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2)begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_306_}; + end + end + endcase + end + + assign _zz_182_ = _zz_304_[19]; + always @ (*) begin + _zz_183_[10] = _zz_182_; + _zz_183_[9] = _zz_182_; + _zz_183_[8] = _zz_182_; + _zz_183_[7] = _zz_182_; + _zz_183_[6] = _zz_182_; + _zz_183_[5] = _zz_182_; + _zz_183_[4] = _zz_182_; + _zz_183_[3] = _zz_182_; + _zz_183_[2] = _zz_182_; + _zz_183_[1] = _zz_182_; + _zz_183_[0] = _zz_182_; + end + + assign _zz_184_ = _zz_305_[11]; + always @ (*) begin + _zz_185_[18] = _zz_184_; + _zz_185_[17] = _zz_184_; + _zz_185_[16] = _zz_184_; + _zz_185_[15] = _zz_184_; + _zz_185_[14] = _zz_184_; + _zz_185_[13] = _zz_184_; + _zz_185_[12] = _zz_184_; + _zz_185_[11] = _zz_184_; + _zz_185_[10] = _zz_184_; + _zz_185_[9] = _zz_184_; + _zz_185_[8] = _zz_184_; + _zz_185_[7] = _zz_184_; + _zz_185_[6] = _zz_184_; + _zz_185_[5] = _zz_184_; + _zz_185_[4] = _zz_184_; + _zz_185_[3] = _zz_184_; + _zz_185_[2] = _zz_184_; + _zz_185_[1] = _zz_184_; + _zz_185_[0] = _zz_184_; + end + + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign _zz_30_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; + assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; + assign BranchPlugin_branchExceptionPort_valid = (memory_arbitration_isValid && (memory_BRANCH_DO && memory_BRANCH_CALC[1])); + assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000); + assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; + assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; + always @ (*) begin + CsrPlugin_privilege = (2'b11); + if(CsrPlugin_forceMachineWire)begin + CsrPlugin_privilege = (2'b11); + end + end + + assign CsrPlugin_misa_base = (2'b01); + assign CsrPlugin_misa_extensions = (26'b00000000000000000001000010); + assign _zz_186_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_187_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_188_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); + assign _zz_189_ = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_190_ = _zz_307_[0]; + assign _zz_191_ = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}; + assign _zz_192_ = _zz_309_[0]; + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_229_)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + end + if(decode_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(execute_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(_zz_233_)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + if(writeBack_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; + end + end + + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_lastStageWasWfi = 1'b0; + always @ (*) begin + CsrPlugin_pipelineLiberator_done = ((! ({writeBack_arbitration_isValid,{memory_arbitration_isValid,execute_arbitration_isValid}} != (3'b000))) && IBusCachedPlugin_pcValids_3); + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != (3'b000)))begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException)begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); + always @ (*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; + if(CsrPlugin_hadException)begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @ (*) begin + CsrPlugin_trapCause = CsrPlugin_interrupt_code; + if(CsrPlugin_hadException)begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + always @ (*) begin + CsrPlugin_xtvec_mode = (2'bxx); + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + end + default : begin + end + endcase + end + + always @ (*) begin + CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign _zz_28_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); + assign _zz_27_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); + assign execute_CsrPlugin_inWfi = 1'b0; + assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)); + always @ (*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + 12'b001100000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + 12'b001101000001 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + 12'b001100000101 : begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + 12'b001101000100 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + 12'b001101000011 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + 12'b111111000000 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + 12'b001100000100 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + 12'b001101000010 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + default : begin + end + endcase + if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @ (*) begin + execute_CsrPlugin_readData = (32'b00000000000000000000000000000000); + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + execute_CsrPlugin_readData[31 : 0] = _zz_200_; + end + 12'b001100000000 : begin + execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE; + end + 12'b001101000001 : begin + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc; + end + 12'b001100000101 : begin + end + 12'b001101000100 : begin + execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP; + end + 12'b001101000011 : begin + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval; + end + 12'b111111000000 : begin + execute_CsrPlugin_readData[31 : 0] = _zz_201_; + end + 12'b001100000100 : begin + execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE; + end + 12'b001101000010 : begin + execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt; + execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + default : begin + end + endcase + end + + assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; + always @ (*) begin + case(_zz_254_) + 1'b0 : begin + execute_CsrPlugin_writeData = execute_SRC1; + end + default : begin + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + always @ (*) begin + memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b0; + if(_zz_217_)begin + if(_zz_231_)begin + memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b1; + end + end + end + + always @ (*) begin + memory_MulDivIterativePlugin_mul_counter_willClear = 1'b0; + if((! memory_arbitration_isStuck))begin + memory_MulDivIterativePlugin_mul_counter_willClear = 1'b1; + end + end + + assign memory_MulDivIterativePlugin_mul_willOverflowIfInc = (memory_MulDivIterativePlugin_mul_counter_value == (6'b100000)); + assign memory_MulDivIterativePlugin_mul_counter_willOverflow = (memory_MulDivIterativePlugin_mul_willOverflowIfInc && memory_MulDivIterativePlugin_mul_counter_willIncrement); + always @ (*) begin + if(memory_MulDivIterativePlugin_mul_counter_willOverflow)begin + memory_MulDivIterativePlugin_mul_counter_valueNext = (6'b000000); + end else begin + memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_312_); + end + if(memory_MulDivIterativePlugin_mul_counter_willClear)begin + memory_MulDivIterativePlugin_mul_counter_valueNext = (6'b000000); + end + end + + always @ (*) begin + memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0; + if(_zz_218_)begin + if(_zz_232_)begin + memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1; + end + end + end + + always @ (*) begin + memory_MulDivIterativePlugin_div_counter_willClear = 1'b0; + if(_zz_246_)begin + memory_MulDivIterativePlugin_div_counter_willClear = 1'b1; + end + end + + assign memory_MulDivIterativePlugin_div_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_div_counter_value == (6'b100001)); + assign memory_MulDivIterativePlugin_div_counter_willOverflow = (memory_MulDivIterativePlugin_div_counter_willOverflowIfInc && memory_MulDivIterativePlugin_div_counter_willIncrement); + always @ (*) begin + if(memory_MulDivIterativePlugin_div_counter_willOverflow)begin + memory_MulDivIterativePlugin_div_counter_valueNext = (6'b000000); + end else begin + memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_320_); + end + if(memory_MulDivIterativePlugin_div_counter_willClear)begin + memory_MulDivIterativePlugin_div_counter_valueNext = (6'b000000); + end + end + + assign _zz_193_ = memory_MulDivIterativePlugin_rs1[31 : 0]; + assign _zz_194_ = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_193_[31]}; + assign _zz_195_ = (_zz_194_ - _zz_321_); + assign _zz_196_ = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); + assign _zz_197_ = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_198_ = ((execute_IS_MUL && _zz_197_) || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @ (*) begin + _zz_199_[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_199_[31 : 0] = execute_RS1; + end + + assign _zz_201_ = (_zz_200_ & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_201_ != (32'b00000000000000000000000000000000)); + assign _zz_24_ = decode_SHIFT_CTRL; + assign _zz_22_ = _zz_73_; + assign _zz_37_ = decode_to_execute_SHIFT_CTRL; + assign _zz_21_ = decode_ENV_CTRL; + assign _zz_18_ = execute_ENV_CTRL; + assign _zz_16_ = memory_ENV_CTRL; + assign _zz_19_ = _zz_67_; + assign _zz_26_ = decode_to_execute_ENV_CTRL; + assign _zz_25_ = execute_to_memory_ENV_CTRL; + assign _zz_29_ = memory_to_writeBack_ENV_CTRL; + assign _zz_14_ = decode_SRC1_CTRL; + assign _zz_12_ = _zz_56_; + assign _zz_44_ = decode_to_execute_SRC1_CTRL; + assign _zz_11_ = decode_BRANCH_CTRL; + assign _zz_95_ = _zz_68_; + assign _zz_32_ = decode_to_execute_BRANCH_CTRL; + assign _zz_9_ = decode_SRC2_CTRL; + assign _zz_7_ = _zz_59_; + assign _zz_42_ = decode_to_execute_SRC2_CTRL; + assign _zz_6_ = decode_ALU_BITWISE_CTRL; + assign _zz_4_ = _zz_70_; + assign _zz_49_ = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_3_ = decode_ALU_CTRL; + assign _zz_1_ = _zz_72_; + assign _zz_47_ = decode_to_execute_ALU_CTRL; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != (3'b000)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != (4'b0000))); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != (2'b00)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != (3'b000))); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != (1'b0)) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != (2'b00))); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != (1'b0))); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + assign iBusWishbone_ADR = {_zz_340_,_zz_202_}; + assign iBusWishbone_CTI = ((_zz_202_ == (3'b111)) ? (3'b111) : (3'b010)); + assign iBusWishbone_BTE = (2'b00); + assign iBusWishbone_SEL = (4'b1111); + assign iBusWishbone_WE = 1'b0; + assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + always @ (*) begin + iBusWishbone_CYC = 1'b0; + if(_zz_247_)begin + iBusWishbone_CYC = 1'b1; + end + end + + always @ (*) begin + iBusWishbone_STB = 1'b0; + if(_zz_247_)begin + iBusWishbone_STB = 1'b1; + end + end + + assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); + assign iBus_rsp_valid = _zz_203_; + assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; + assign iBus_rsp_payload_error = 1'b0; + assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; + assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr; + assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address; + assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data; + assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size; + assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready; + assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2); + assign dBusWishbone_CTI = (3'b000); + assign dBusWishbone_BTE = (2'b00); + always @ (*) begin + case(dBus_cmd_halfPipe_payload_size) + 2'b00 : begin + _zz_204_ = (4'b0001); + end + 2'b01 : begin + _zz_204_ = (4'b0011); + end + default : begin + _zz_204_ = (4'b1111); + end + endcase + end + + always @ (*) begin + dBusWishbone_SEL = _zz_341_[3:0]; + if((! dBus_cmd_halfPipe_payload_wr))begin + dBusWishbone_SEL = (4'b1111); + end + end + + assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr; + assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data; + assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK); + assign dBusWishbone_CYC = dBus_cmd_halfPipe_valid; + assign dBusWishbone_STB = dBus_cmd_halfPipe_valid; + assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); + assign dBus_rsp_data = dBusWishbone_DAT_MISO; + assign dBus_rsp_error = 1'b0; + always @ (posedge clk) begin + if(reset) begin + IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_booted <= 1'b0; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_112_ <= 1'b0; + _zz_114_ <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusCachedPlugin_injector_decodeRemoved <= 1'b0; + IBusCachedPlugin_rspCounter <= _zz_127_; + IBusCachedPlugin_rspCounter <= (32'b00000000000000000000000000000000); + _zz_149_ <= 1'b1; + execute_LightShifterPlugin_isActive <= 1'b0; + _zz_161_ <= 1'b0; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= (2'b11); + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_hadException <= 1'b0; + execute_CsrPlugin_wfiWake <= 1'b0; + memory_MulDivIterativePlugin_mul_counter_value <= (6'b000000); + memory_MulDivIterativePlugin_div_counter_value <= (6'b000000); + _zz_200_ <= (32'b00000000000000000000000000000000); + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + memory_to_writeBack_REGFILE_WRITE_DATA <= (32'b00000000000000000000000000000000); + memory_to_writeBack_INSTRUCTION <= (32'b00000000000000000000000000000000); + _zz_202_ <= (3'b000); + _zz_203_ <= 1'b0; + dBus_cmd_halfPipe_regs_valid <= 1'b0; + dBus_cmd_halfPipe_regs_ready <= 1'b1; + end else begin + IBusCachedPlugin_fetchPc_booted <= 1'b1; + if((IBusCachedPlugin_fetchPc_corrected || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; + end + if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetcherflushIt) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; + end + if(IBusCachedPlugin_fetcherflushIt)begin + _zz_112_ <= 1'b0; + end + if(_zz_110_)begin + _zz_112_ <= IBusCachedPlugin_iBusRsp_stages_0_output_valid; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_114_ <= IBusCachedPlugin_iBusRsp_stages_1_output_valid; + end + if(IBusCachedPlugin_fetcherflushIt)begin + _zz_114_ <= 1'b0; + end + if(IBusCachedPlugin_fetcherflushIt)begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if(IBusCachedPlugin_fetcherflushIt)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; + end + if(IBusCachedPlugin_fetcherflushIt)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(IBusCachedPlugin_fetcherflushIt)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; + end + if(IBusCachedPlugin_fetcherflushIt)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(IBusCachedPlugin_fetcherflushIt)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if((! memory_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; + end + if(IBusCachedPlugin_fetcherflushIt)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusCachedPlugin_fetcherflushIt)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if((! writeBack_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; + end + if(IBusCachedPlugin_fetcherflushIt)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(decode_arbitration_removeIt)begin + IBusCachedPlugin_injector_decodeRemoved <= 1'b1; + end + if(IBusCachedPlugin_fetcherflushIt)begin + IBusCachedPlugin_injector_decodeRemoved <= 1'b0; + end + if(iBus_rsp_valid)begin + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + (32'b00000000000000000000000000000001)); + end + _zz_149_ <= 1'b0; + if(_zz_223_)begin + if(_zz_230_)begin + execute_LightShifterPlugin_isActive <= 1'b1; + if(execute_LightShifterPlugin_done)begin + execute_LightShifterPlugin_isActive <= 1'b0; + end + end + end + if(execute_arbitration_removeIt)begin + execute_LightShifterPlugin_isActive <= 1'b0; + end + _zz_161_ <= _zz_160_; + if((! decode_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + end + if((! execute_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + end + CsrPlugin_interrupt_valid <= 1'b0; + if(_zz_248_)begin + if(_zz_249_)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_250_)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_251_)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_234_)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_235_)begin + case(_zz_236_) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= (2'b00); + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= ({_zz_188_,{_zz_187_,_zz_186_}} != (3'b000)); + memory_MulDivIterativePlugin_mul_counter_value <= memory_MulDivIterativePlugin_mul_counter_valueNext; + memory_MulDivIterativePlugin_div_counter_value <= memory_MulDivIterativePlugin_div_counter_valueNext; + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_35_; + end + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + if(execute_CsrPlugin_writeEnable)begin + _zz_200_ <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000000 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_334_[0]; + CsrPlugin_mstatus_MIE <= _zz_335_[0]; + end + end + 12'b001101000001 : begin + end + 12'b001100000101 : begin + end + 12'b001101000100 : begin + end + 12'b001101000011 : begin + end + 12'b111111000000 : begin + end + 12'b001100000100 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_337_[0]; + CsrPlugin_mie_MTIE <= _zz_338_[0]; + CsrPlugin_mie_MSIE <= _zz_339_[0]; + end + end + 12'b001101000010 : begin + end + default : begin + end + endcase + if(_zz_247_)begin + if(iBusWishbone_ACK)begin + _zz_202_ <= (_zz_202_ + (3'b001)); + end + end + _zz_203_ <= (iBusWishbone_CYC && iBusWishbone_ACK); + if(_zz_252_)begin + dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; + dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); + end else begin + dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready); + dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready; + end + end + end + + always @ (posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_115_ <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + end + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin + $display("ERROR DBusSimplePlugin doesn't allow memory stage stall when read happend"); + end + if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) begin + $display("ERROR DBusSimplePlugin doesn't allow writeback stage stall when read happend"); + end + if(_zz_223_)begin + if(_zz_230_)begin + execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - (5'b00001)); + end + end + if(_zz_160_)begin + _zz_162_ <= _zz_50_[11 : 7]; + _zz_163_ <= _zz_79_; + end + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + if(writeBack_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + end + if(_zz_229_)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_190_ ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_190_ ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(_zz_233_)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_192_ ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_192_ ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr); + end + if(_zz_248_)begin + if(_zz_249_)begin + CsrPlugin_interrupt_code <= (4'b0111); + CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + if(_zz_250_)begin + CsrPlugin_interrupt_code <= (4'b0011); + CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + if(_zz_251_)begin + CsrPlugin_interrupt_code <= (4'b1011); + CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + end + if(_zz_234_)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= writeBack_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + if(_zz_217_)begin + if(_zz_231_)begin + memory_MulDivIterativePlugin_rs2 <= (memory_MulDivIterativePlugin_rs2 >>> 1); + memory_MulDivIterativePlugin_accumulator <= ({_zz_313_,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); + end + end + if((memory_MulDivIterativePlugin_div_counter_value == (6'b100000)))begin + memory_MulDivIterativePlugin_div_done <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + memory_MulDivIterativePlugin_div_done <= 1'b0; + end + if(_zz_218_)begin + if(_zz_232_)begin + memory_MulDivIterativePlugin_rs1[31 : 0] <= _zz_322_[31:0]; + memory_MulDivIterativePlugin_accumulator[31 : 0] <= ((! _zz_195_[32]) ? _zz_323_ : _zz_324_); + if((memory_MulDivIterativePlugin_div_counter_value == (6'b100000)))begin + memory_MulDivIterativePlugin_div_result <= _zz_325_[31:0]; + end + end + end + if(_zz_246_)begin + memory_MulDivIterativePlugin_accumulator <= (65'b00000000000000000000000000000000000000000000000000000000000000000); + memory_MulDivIterativePlugin_rs1 <= ((_zz_198_ ? (~ _zz_199_) : _zz_199_) + _zz_331_); + memory_MulDivIterativePlugin_rs2 <= ((_zz_197_ ? (~ execute_RS2) : execute_RS2) + _zz_333_); + memory_MulDivIterativePlugin_div_needRevert <= ((_zz_198_ ^ (_zz_197_ && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == (32'b00000000000000000000000000000000)) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_23_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_41_; + end + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_97_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_96_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_20_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_17_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_15_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if(((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_36_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1 <= decode_RS1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_13_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_10_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MMU_FAULT <= execute_MMU_FAULT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= decode_RS2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MMU_RSP_physicalAddress <= execute_MMU_RSP_physicalAddress; + execute_to_memory_MMU_RSP_isIoAccess <= execute_MMU_RSP_isIoAccess; + execute_to_memory_MMU_RSP_allowRead <= execute_MMU_RSP_allowRead; + execute_to_memory_MMU_RSP_allowWrite <= execute_MMU_RSP_allowWrite; + execute_to_memory_MMU_RSP_allowExecute <= execute_MMU_RSP_allowExecute; + execute_to_memory_MMU_RSP_exception <= execute_MMU_RSP_exception; + execute_to_memory_MMU_RSP_refilling <= execute_MMU_RSP_refilling; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_8_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_5_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_2_; + end + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + end + 12'b001100000000 : begin + end + 12'b001101000001 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000101 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + end + end + 12'b001101000100 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_336_[0]; + end + end + 12'b001101000011 : begin + end + 12'b111111000000 : begin + end + 12'b001100000100 : begin + end + 12'b001101000010 : begin + end + default : begin + end + endcase + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + if(_zz_252_)begin + dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; + dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; + dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; + dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size; + end + end + +endmodule + diff --git a/minitests/litex/min_ddr/arty/verilog/mem.init b/minitests/litex/min_ddr/arty/verilog/mem.init new file mode 100644 index 00000000..d5e10db0 --- /dev/null +++ b/minitests/litex/min_ddr/arty/verilog/mem.init @@ -0,0 +1,4723 @@ +b00006f +13 +13 +13 +13 +13 +13 +13 +fe112e23 +fe512c23 +fe612a23 +fe712823 +fea12623 +feb12423 +fec12223 +fed12023 +fce12e23 +fcf12c23 +fd012a23 +fd112823 +fdc12623 +fdd12423 +fde12223 +fdf12023 +fc010113 +94000ef +3c12083 +3812283 +3412303 +3012383 +2c12503 +2812583 +2412603 +2012683 +1c12703 +1812783 +1412803 +1012883 +c12e03 +812e83 +412f03 +12f83 +4010113 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new file mode 100644 index 00000000..bf52ef90 --- /dev/null +++ b/minitests/litex/min_ddr/arty/verilog/top.v @@ -0,0 +1,12368 @@ +//-------------------------------------------------------------------------------- +// Auto-generated by Migen (562c046) & LiteX (a0122f98) on 2019-12-11 10:50:34 +//-------------------------------------------------------------------------------- +module top( + output reg serial_tx, + input serial_rx, + (* dont_touch = "true" *) input clk100, + input cpu_reset, + output [13:0] ddram_a, + output [2:0] ddram_ba, + output ddram_ras_n, + output ddram_cas_n, + output ddram_we_n, + output ddram_cs_n, + output [1:0] ddram_dm, + inout [15:0] ddram_dq, + output [1:0] ddram_dqs_p, + output [1:0] ddram_dqs_n, + output ddram_clk_p, + output ddram_clk_n, + output ddram_cke, + output ddram_odt, + output ddram_reset_n +); + +wire main_ctrl_reset_reset_re; +wire main_ctrl_reset_reset_r; +wire main_ctrl_reset_reset_we; +reg main_ctrl_reset_reset_w = 1'd0; +reg [31:0] main_ctrl_storage = 32'd305419896; +reg main_ctrl_re = 1'd0; +wire [31:0] main_ctrl_bus_errors_status; +wire main_ctrl_bus_errors_we; +wire main_ctrl_reset; +wire main_ctrl_bus_error; +reg [31:0] main_ctrl_bus_errors = 32'd0; +wire main_cpu_reset; +wire [29:0] main_cpu_ibus_adr; +wire [31:0] main_cpu_ibus_dat_w; +wire [31:0] main_cpu_ibus_dat_r; +wire [3:0] main_cpu_ibus_sel; +wire main_cpu_ibus_cyc; +wire main_cpu_ibus_stb; +wire main_cpu_ibus_ack; +wire main_cpu_ibus_we; +wire [2:0] main_cpu_ibus_cti; +wire [1:0] main_cpu_ibus_bte; +wire main_cpu_ibus_err; +wire [29:0] main_cpu_dbus_adr; +wire [31:0] main_cpu_dbus_dat_w; +wire [31:0] main_cpu_dbus_dat_r; +wire [3:0] main_cpu_dbus_sel; +wire main_cpu_dbus_cyc; +wire main_cpu_dbus_stb; +wire main_cpu_dbus_ack; +wire main_cpu_dbus_we; +wire [2:0] main_cpu_dbus_cti; +wire [1:0] main_cpu_dbus_bte; +wire main_cpu_dbus_err; +reg [31:0] main_cpu_interrupt = 32'd0; +wire [29:0] main_interface0_soc_bus_adr; +wire [31:0] main_interface0_soc_bus_dat_w; +wire [31:0] main_interface0_soc_bus_dat_r; +wire [3:0] main_interface0_soc_bus_sel; +wire main_interface0_soc_bus_cyc; +wire main_interface0_soc_bus_stb; +wire main_interface0_soc_bus_ack; +wire main_interface0_soc_bus_we; +wire [2:0] main_interface0_soc_bus_cti; +wire [1:0] main_interface0_soc_bus_bte; +wire main_interface0_soc_bus_err; +wire [29:0] main_interface1_soc_bus_adr; +wire [31:0] main_interface1_soc_bus_dat_w; +wire [31:0] main_interface1_soc_bus_dat_r; +wire [3:0] main_interface1_soc_bus_sel; +wire main_interface1_soc_bus_cyc; +wire main_interface1_soc_bus_stb; +wire main_interface1_soc_bus_ack; +wire main_interface1_soc_bus_we; +wire [2:0] main_interface1_soc_bus_cti; +wire [1:0] main_interface1_soc_bus_bte; +wire main_interface1_soc_bus_err; +wire [29:0] main_rom_bus_adr; +wire [31:0] main_rom_bus_dat_w; +wire [31:0] main_rom_bus_dat_r; +wire [3:0] main_rom_bus_sel; +wire main_rom_bus_cyc; +wire main_rom_bus_stb; +reg main_rom_bus_ack = 1'd0; +wire main_rom_bus_we; +wire [2:0] main_rom_bus_cti; +wire [1:0] main_rom_bus_bte; +reg main_rom_bus_err = 1'd0; +wire [12:0] main_rom_adr; +wire [31:0] main_rom_dat_r; +wire [29:0] main_sram_bus_adr; +wire [31:0] main_sram_bus_dat_w; +wire [31:0] main_sram_bus_dat_r; +wire [3:0] main_sram_bus_sel; +wire main_sram_bus_cyc; +wire main_sram_bus_stb; +reg main_sram_bus_ack = 1'd0; +wire main_sram_bus_we; +wire [2:0] main_sram_bus_cti; +wire [1:0] main_sram_bus_bte; +reg main_sram_bus_err = 1'd0; +wire [12:0] main_sram_adr; +wire [31:0] main_sram_dat_r; +reg [3:0] main_sram_we = 4'd0; +wire [31:0] main_sram_dat_w; +reg [31:0] main_uart_phy_storage = 32'd9895604; +reg main_uart_phy_re = 1'd0; +wire main_uart_phy_sink_valid; +reg main_uart_phy_sink_ready = 1'd0; +wire main_uart_phy_sink_first; +wire main_uart_phy_sink_last; +wire [7:0] main_uart_phy_sink_payload_data; +reg main_uart_phy_uart_clk_txen = 1'd0; +reg [31:0] main_uart_phy_phase_accumulator_tx = 32'd0; +reg [7:0] main_uart_phy_tx_reg = 8'd0; +reg [3:0] main_uart_phy_tx_bitcount = 4'd0; +reg main_uart_phy_tx_busy = 1'd0; +reg main_uart_phy_source_valid = 1'd0; +wire main_uart_phy_source_ready; +reg main_uart_phy_source_first = 1'd0; +reg main_uart_phy_source_last = 1'd0; +reg [7:0] main_uart_phy_source_payload_data = 8'd0; +reg main_uart_phy_uart_clk_rxen = 1'd0; +reg [31:0] main_uart_phy_phase_accumulator_rx = 32'd0; +wire main_uart_phy_rx; +reg main_uart_phy_rx_r = 1'd0; +reg [7:0] main_uart_phy_rx_reg = 8'd0; +reg [3:0] main_uart_phy_rx_bitcount = 4'd0; +reg main_uart_phy_rx_busy = 1'd0; +wire main_uart_rxtx_re; +wire [7:0] main_uart_rxtx_r; +wire main_uart_rxtx_we; +wire [7:0] main_uart_rxtx_w; +wire main_uart_txfull_status; +wire main_uart_txfull_we; +wire main_uart_rxempty_status; +wire main_uart_rxempty_we; +wire main_uart_irq; +wire main_uart_tx_status; +reg main_uart_tx_pending = 1'd0; +wire main_uart_tx_trigger; +reg main_uart_tx_clear = 1'd0; +reg main_uart_tx_old_trigger = 1'd0; +wire main_uart_rx_status; +reg main_uart_rx_pending = 1'd0; +wire main_uart_rx_trigger; +reg main_uart_rx_clear = 1'd0; +reg main_uart_rx_old_trigger = 1'd0; +wire main_uart_eventmanager_status_re; +wire [1:0] main_uart_eventmanager_status_r; +wire main_uart_eventmanager_status_we; +reg [1:0] main_uart_eventmanager_status_w = 2'd0; +wire main_uart_eventmanager_pending_re; +wire [1:0] main_uart_eventmanager_pending_r; +wire main_uart_eventmanager_pending_we; +reg [1:0] main_uart_eventmanager_pending_w = 2'd0; +reg [1:0] main_uart_eventmanager_storage = 2'd0; +reg main_uart_eventmanager_re = 1'd0; +wire main_uart_tx_fifo_sink_valid; +wire main_uart_tx_fifo_sink_ready; +reg main_uart_tx_fifo_sink_first = 1'd0; +reg main_uart_tx_fifo_sink_last = 1'd0; +wire [7:0] main_uart_tx_fifo_sink_payload_data; +wire main_uart_tx_fifo_source_valid; +wire main_uart_tx_fifo_source_ready; +wire main_uart_tx_fifo_source_first; +wire main_uart_tx_fifo_source_last; +wire [7:0] main_uart_tx_fifo_source_payload_data; +wire main_uart_tx_fifo_re; +reg main_uart_tx_fifo_readable = 1'd0; +wire main_uart_tx_fifo_syncfifo_we; +wire main_uart_tx_fifo_syncfifo_writable; +wire main_uart_tx_fifo_syncfifo_re; +wire main_uart_tx_fifo_syncfifo_readable; +wire [9:0] main_uart_tx_fifo_syncfifo_din; +wire [9:0] main_uart_tx_fifo_syncfifo_dout; +reg [4:0] main_uart_tx_fifo_level0 = 5'd0; +reg main_uart_tx_fifo_replace = 1'd0; +reg [3:0] main_uart_tx_fifo_produce = 4'd0; +reg [3:0] main_uart_tx_fifo_consume = 4'd0; +reg [3:0] main_uart_tx_fifo_wrport_adr = 4'd0; +wire [9:0] main_uart_tx_fifo_wrport_dat_r; +wire main_uart_tx_fifo_wrport_we; +wire [9:0] main_uart_tx_fifo_wrport_dat_w; +wire main_uart_tx_fifo_do_read; +wire [3:0] main_uart_tx_fifo_rdport_adr; +wire [9:0] main_uart_tx_fifo_rdport_dat_r; +wire main_uart_tx_fifo_rdport_re; +wire [4:0] main_uart_tx_fifo_level1; +wire [7:0] main_uart_tx_fifo_fifo_in_payload_data; +wire main_uart_tx_fifo_fifo_in_first; +wire main_uart_tx_fifo_fifo_in_last; +wire [7:0] main_uart_tx_fifo_fifo_out_payload_data; +wire main_uart_tx_fifo_fifo_out_first; +wire main_uart_tx_fifo_fifo_out_last; +wire main_uart_rx_fifo_sink_valid; +wire main_uart_rx_fifo_sink_ready; +wire main_uart_rx_fifo_sink_first; +wire main_uart_rx_fifo_sink_last; +wire [7:0] main_uart_rx_fifo_sink_payload_data; +wire main_uart_rx_fifo_source_valid; +wire main_uart_rx_fifo_source_ready; +wire main_uart_rx_fifo_source_first; +wire main_uart_rx_fifo_source_last; +wire [7:0] main_uart_rx_fifo_source_payload_data; +wire main_uart_rx_fifo_re; +reg main_uart_rx_fifo_readable = 1'd0; +wire main_uart_rx_fifo_syncfifo_we; +wire main_uart_rx_fifo_syncfifo_writable; +wire main_uart_rx_fifo_syncfifo_re; +wire main_uart_rx_fifo_syncfifo_readable; +wire [9:0] main_uart_rx_fifo_syncfifo_din; +wire [9:0] main_uart_rx_fifo_syncfifo_dout; +reg [4:0] main_uart_rx_fifo_level0 = 5'd0; +reg main_uart_rx_fifo_replace = 1'd0; +reg [3:0] main_uart_rx_fifo_produce = 4'd0; +reg [3:0] main_uart_rx_fifo_consume = 4'd0; +reg [3:0] main_uart_rx_fifo_wrport_adr = 4'd0; +wire [9:0] main_uart_rx_fifo_wrport_dat_r; +wire main_uart_rx_fifo_wrport_we; +wire [9:0] main_uart_rx_fifo_wrport_dat_w; +wire main_uart_rx_fifo_do_read; +wire [3:0] main_uart_rx_fifo_rdport_adr; +wire [9:0] main_uart_rx_fifo_rdport_dat_r; +wire main_uart_rx_fifo_rdport_re; +wire [4:0] main_uart_rx_fifo_level1; +wire [7:0] main_uart_rx_fifo_fifo_in_payload_data; +wire main_uart_rx_fifo_fifo_in_first; +wire main_uart_rx_fifo_fifo_in_last; +wire [7:0] main_uart_rx_fifo_fifo_out_payload_data; +wire main_uart_rx_fifo_fifo_out_first; +wire main_uart_rx_fifo_fifo_out_last; +reg main_uart_reset = 1'd0; +reg [31:0] main_timer0_load_storage = 32'd0; +reg main_timer0_load_re = 1'd0; +reg [31:0] main_timer0_reload_storage = 32'd0; +reg main_timer0_reload_re = 1'd0; +reg main_timer0_en_storage = 1'd0; +reg main_timer0_en_re = 1'd0; +reg main_timer0_update_value_storage = 1'd0; +reg main_timer0_update_value_re = 1'd0; +reg [31:0] main_timer0_value_status = 32'd0; +wire main_timer0_value_we; +wire main_timer0_irq; +wire main_timer0_zero_status; +reg main_timer0_zero_pending = 1'd0; +wire main_timer0_zero_trigger; +reg main_timer0_zero_clear = 1'd0; +reg main_timer0_zero_old_trigger = 1'd0; +wire main_timer0_eventmanager_status_re; +wire main_timer0_eventmanager_status_r; +wire main_timer0_eventmanager_status_we; +wire main_timer0_eventmanager_status_w; +wire main_timer0_eventmanager_pending_re; +wire main_timer0_eventmanager_pending_r; +wire main_timer0_eventmanager_pending_we; +wire main_timer0_eventmanager_pending_w; +reg main_timer0_eventmanager_storage = 1'd0; +reg main_timer0_eventmanager_re = 1'd0; +reg [31:0] main_timer0_value = 32'd0; +reg [13:0] main_interface_adr = 14'd0; +reg main_interface_we = 1'd0; +wire [7:0] main_interface_dat_w; +wire [7:0] main_interface_dat_r; +wire [29:0] main_bus_wishbone_adr; +wire [31:0] main_bus_wishbone_dat_w; +wire [31:0] main_bus_wishbone_dat_r; +wire [3:0] main_bus_wishbone_sel; +wire main_bus_wishbone_cyc; +wire main_bus_wishbone_stb; +reg main_bus_wishbone_ack = 1'd0; +wire main_bus_wishbone_we; +wire [2:0] main_bus_wishbone_cti; +wire [1:0] main_bus_wishbone_bte; +reg main_bus_wishbone_err = 1'd0; +wire [29:0] main_interface0_wb_sdram_adr; +wire [31:0] main_interface0_wb_sdram_dat_w; +reg [31:0] main_interface0_wb_sdram_dat_r = 32'd0; +wire [3:0] main_interface0_wb_sdram_sel; +wire main_interface0_wb_sdram_cyc; +wire main_interface0_wb_sdram_stb; +reg main_interface0_wb_sdram_ack = 1'd0; +wire main_interface0_wb_sdram_we; +wire [2:0] main_interface0_wb_sdram_cti; +wire [1:0] main_interface0_wb_sdram_bte; +reg main_interface0_wb_sdram_err = 1'd0; +wire sys_clk; +wire sys_rst; +wire sys4x_clk; +wire sys4x_dqs_clk; +wire clk200_clk; +wire clk200_rst; +wire main_pll_clkin; +wire main_reset; +wire main_locked; +wire main_clkin; +wire main_clkout0; +wire main_clkout_buf0; +wire main_clkout1; +wire main_clkout_buf1; +wire main_clkout2; +wire main_clkout_buf2; +wire main_clkout3; +wire main_clkout_buf3; +reg [3:0] main_reset_counter = 4'd15; +reg main_ic_reset = 1'd1; +reg [4:0] main_a7ddrphy_half_sys8x_taps_storage = 5'd16; +reg main_a7ddrphy_half_sys8x_taps_re = 1'd0; +wire main_a7ddrphy_cdly_rst_re; +wire main_a7ddrphy_cdly_rst_r; +wire main_a7ddrphy_cdly_rst_we; +reg main_a7ddrphy_cdly_rst_w = 1'd0; +wire main_a7ddrphy_cdly_inc_re; +wire main_a7ddrphy_cdly_inc_r; +wire main_a7ddrphy_cdly_inc_we; +reg main_a7ddrphy_cdly_inc_w = 1'd0; +reg [1:0] main_a7ddrphy_dly_sel_storage = 2'd0; +reg main_a7ddrphy_dly_sel_re = 1'd0; +wire main_a7ddrphy_rdly_dq_rst_re; +wire main_a7ddrphy_rdly_dq_rst_r; +wire main_a7ddrphy_rdly_dq_rst_we; +reg main_a7ddrphy_rdly_dq_rst_w = 1'd0; +wire main_a7ddrphy_rdly_dq_inc_re; +wire main_a7ddrphy_rdly_dq_inc_r; +wire main_a7ddrphy_rdly_dq_inc_we; +reg main_a7ddrphy_rdly_dq_inc_w = 1'd0; +wire main_a7ddrphy_rdly_dq_bitslip_rst_re; +wire main_a7ddrphy_rdly_dq_bitslip_rst_r; +wire main_a7ddrphy_rdly_dq_bitslip_rst_we; +reg main_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0; +wire main_a7ddrphy_rdly_dq_bitslip_re; +wire main_a7ddrphy_rdly_dq_bitslip_r; +wire main_a7ddrphy_rdly_dq_bitslip_we; +reg main_a7ddrphy_rdly_dq_bitslip_w = 1'd0; +wire [13:0] main_a7ddrphy_dfi_p0_address; +wire [2:0] main_a7ddrphy_dfi_p0_bank; +wire main_a7ddrphy_dfi_p0_cas_n; +wire main_a7ddrphy_dfi_p0_cs_n; +wire main_a7ddrphy_dfi_p0_ras_n; +wire main_a7ddrphy_dfi_p0_we_n; +wire main_a7ddrphy_dfi_p0_cke; +wire main_a7ddrphy_dfi_p0_odt; +wire main_a7ddrphy_dfi_p0_reset_n; +wire main_a7ddrphy_dfi_p0_act_n; +wire [31:0] main_a7ddrphy_dfi_p0_wrdata; +wire main_a7ddrphy_dfi_p0_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p0_wrdata_mask; +wire main_a7ddrphy_dfi_p0_rddata_en; +reg [31:0] main_a7ddrphy_dfi_p0_rddata = 32'd0; +reg main_a7ddrphy_dfi_p0_rddata_valid = 1'd0; +wire [13:0] main_a7ddrphy_dfi_p1_address; +wire [2:0] main_a7ddrphy_dfi_p1_bank; +wire main_a7ddrphy_dfi_p1_cas_n; +wire main_a7ddrphy_dfi_p1_cs_n; +wire main_a7ddrphy_dfi_p1_ras_n; +wire main_a7ddrphy_dfi_p1_we_n; +wire main_a7ddrphy_dfi_p1_cke; +wire main_a7ddrphy_dfi_p1_odt; +wire main_a7ddrphy_dfi_p1_reset_n; +wire main_a7ddrphy_dfi_p1_act_n; +wire [31:0] main_a7ddrphy_dfi_p1_wrdata; +wire main_a7ddrphy_dfi_p1_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p1_wrdata_mask; +wire main_a7ddrphy_dfi_p1_rddata_en; +reg [31:0] main_a7ddrphy_dfi_p1_rddata = 32'd0; +reg main_a7ddrphy_dfi_p1_rddata_valid = 1'd0; +wire [13:0] main_a7ddrphy_dfi_p2_address; +wire [2:0] main_a7ddrphy_dfi_p2_bank; +wire main_a7ddrphy_dfi_p2_cas_n; +wire main_a7ddrphy_dfi_p2_cs_n; +wire main_a7ddrphy_dfi_p2_ras_n; +wire main_a7ddrphy_dfi_p2_we_n; +wire main_a7ddrphy_dfi_p2_cke; +wire main_a7ddrphy_dfi_p2_odt; +wire main_a7ddrphy_dfi_p2_reset_n; +wire main_a7ddrphy_dfi_p2_act_n; +wire [31:0] main_a7ddrphy_dfi_p2_wrdata; +wire main_a7ddrphy_dfi_p2_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p2_wrdata_mask; +wire main_a7ddrphy_dfi_p2_rddata_en; +reg [31:0] main_a7ddrphy_dfi_p2_rddata = 32'd0; +reg main_a7ddrphy_dfi_p2_rddata_valid = 1'd0; +wire [13:0] main_a7ddrphy_dfi_p3_address; +wire [2:0] main_a7ddrphy_dfi_p3_bank; +wire main_a7ddrphy_dfi_p3_cas_n; +wire main_a7ddrphy_dfi_p3_cs_n; +wire main_a7ddrphy_dfi_p3_ras_n; +wire main_a7ddrphy_dfi_p3_we_n; +wire main_a7ddrphy_dfi_p3_cke; +wire main_a7ddrphy_dfi_p3_odt; +wire main_a7ddrphy_dfi_p3_reset_n; +wire main_a7ddrphy_dfi_p3_act_n; +wire [31:0] main_a7ddrphy_dfi_p3_wrdata; +wire main_a7ddrphy_dfi_p3_wrdata_en; +wire [3:0] main_a7ddrphy_dfi_p3_wrdata_mask; +wire main_a7ddrphy_dfi_p3_rddata_en; +reg [31:0] main_a7ddrphy_dfi_p3_rddata = 32'd0; +reg main_a7ddrphy_dfi_p3_rddata_valid = 1'd0; +wire main_a7ddrphy_sd_clk_se_nodelay; +reg main_a7ddrphy_oe_dqs = 1'd0; +wire main_a7ddrphy_dqs_preamble; +wire main_a7ddrphy_dqs_postamble; +reg [7:0] main_a7ddrphy_dqs_serdes_pattern = 8'd85; +wire main_a7ddrphy_dqs_nodelay0; +wire main_a7ddrphy_dqs_t0; +wire main_a7ddrphy0; +wire main_a7ddrphy_dqs_nodelay1; +wire main_a7ddrphy_dqs_t1; +wire main_a7ddrphy1; +reg main_a7ddrphy_oe_dq = 1'd0; +wire main_a7ddrphy_dq_o_nodelay0; +wire main_a7ddrphy_dq_i_nodelay0; +wire main_a7ddrphy_dq_i_delayed0; +wire main_a7ddrphy_dq_t0; +wire [7:0] main_a7ddrphy_dq_i_data0; +wire [7:0] main_a7ddrphy_bitslip0_i; +reg [7:0] main_a7ddrphy_bitslip0_o = 8'd0; +reg [2:0] main_a7ddrphy_bitslip0_value = 3'd0; +reg [15:0] main_a7ddrphy_bitslip0_r = 16'd0; +wire main_a7ddrphy_dq_o_nodelay1; +wire main_a7ddrphy_dq_i_nodelay1; +wire main_a7ddrphy_dq_i_delayed1; +wire main_a7ddrphy_dq_t1; +wire [7:0] main_a7ddrphy_dq_i_data1; +wire [7:0] main_a7ddrphy_bitslip1_i; +reg [7:0] main_a7ddrphy_bitslip1_o = 8'd0; +reg [2:0] main_a7ddrphy_bitslip1_value = 3'd0; +reg [15:0] main_a7ddrphy_bitslip1_r = 16'd0; +wire main_a7ddrphy_dq_o_nodelay2; +wire main_a7ddrphy_dq_i_nodelay2; +wire main_a7ddrphy_dq_i_delayed2; +wire main_a7ddrphy_dq_t2; +wire [7:0] main_a7ddrphy_dq_i_data2; +wire [7:0] main_a7ddrphy_bitslip2_i; +reg [7:0] main_a7ddrphy_bitslip2_o = 8'd0; +reg [2:0] main_a7ddrphy_bitslip2_value = 3'd0; +reg [15:0] main_a7ddrphy_bitslip2_r = 16'd0; +wire main_a7ddrphy_dq_o_nodelay3; +wire main_a7ddrphy_dq_i_nodelay3; +wire main_a7ddrphy_dq_i_delayed3; +wire main_a7ddrphy_dq_t3; +wire [7:0] main_a7ddrphy_dq_i_data3; +wire [7:0] main_a7ddrphy_bitslip3_i; +reg [7:0] main_a7ddrphy_bitslip3_o = 8'd0; +reg [2:0] main_a7ddrphy_bitslip3_value = 3'd0; +reg [15:0] main_a7ddrphy_bitslip3_r = 16'd0; +wire main_a7ddrphy_dq_o_nodelay4; +wire main_a7ddrphy_dq_i_nodelay4; +wire main_a7ddrphy_dq_i_delayed4; +wire main_a7ddrphy_dq_t4; +wire [7:0] main_a7ddrphy_dq_i_data4; +wire [7:0] main_a7ddrphy_bitslip4_i; +reg [7:0] main_a7ddrphy_bitslip4_o = 8'd0; +reg [2:0] main_a7ddrphy_bitslip4_value = 3'd0; +reg [15:0] main_a7ddrphy_bitslip4_r = 16'd0; +wire main_a7ddrphy_dq_o_nodelay5; +wire main_a7ddrphy_dq_i_nodelay5; +wire main_a7ddrphy_dq_i_delayed5; +wire main_a7ddrphy_dq_t5; +wire [7:0] main_a7ddrphy_dq_i_data5; +wire [7:0] main_a7ddrphy_bitslip5_i; +reg [7:0] main_a7ddrphy_bitslip5_o = 8'd0; +reg [2:0] main_a7ddrphy_bitslip5_value = 3'd0; +reg [15:0] main_a7ddrphy_bitslip5_r = 16'd0; +wire main_a7ddrphy_dq_o_nodelay6; +wire main_a7ddrphy_dq_i_nodelay6; +wire main_a7ddrphy_dq_i_delayed6; +wire main_a7ddrphy_dq_t6; +wire [7:0] main_a7ddrphy_dq_i_data6; +wire [7:0] main_a7ddrphy_bitslip6_i; +reg [7:0] main_a7ddrphy_bitslip6_o = 8'd0; +reg [2:0] main_a7ddrphy_bitslip6_value = 3'd0; +reg [15:0] main_a7ddrphy_bitslip6_r = 16'd0; +wire main_a7ddrphy_dq_o_nodelay7; +wire main_a7ddrphy_dq_i_nodelay7; +wire main_a7ddrphy_dq_i_delayed7; +wire main_a7ddrphy_dq_t7; +wire [7:0] main_a7ddrphy_dq_i_data7; +wire [7:0] main_a7ddrphy_bitslip7_i; +reg [7:0] main_a7ddrphy_bitslip7_o = 8'd0; +reg [2:0] main_a7ddrphy_bitslip7_value = 3'd0; +reg [15:0] main_a7ddrphy_bitslip7_r = 16'd0; +wire main_a7ddrphy_dq_o_nodelay8; +wire main_a7ddrphy_dq_i_nodelay8; +wire main_a7ddrphy_dq_i_delayed8; +wire main_a7ddrphy_dq_t8; +wire [7:0] main_a7ddrphy_dq_i_data8; +wire [7:0] main_a7ddrphy_bitslip8_i; +reg [7:0] main_a7ddrphy_bitslip8_o = 8'd0; +reg [2:0] main_a7ddrphy_bitslip8_value = 3'd0; +reg [15:0] main_a7ddrphy_bitslip8_r = 16'd0; +wire main_a7ddrphy_dq_o_nodelay9; +wire main_a7ddrphy_dq_i_nodelay9; +wire main_a7ddrphy_dq_i_delayed9; +wire main_a7ddrphy_dq_t9; +wire [7:0] main_a7ddrphy_dq_i_data9; +wire [7:0] main_a7ddrphy_bitslip9_i; +reg [7:0] main_a7ddrphy_bitslip9_o = 8'd0; +reg [2:0] main_a7ddrphy_bitslip9_value = 3'd0; +reg [15:0] main_a7ddrphy_bitslip9_r = 16'd0; +wire main_a7ddrphy_dq_o_nodelay10; +wire main_a7ddrphy_dq_i_nodelay10; +wire main_a7ddrphy_dq_i_delayed10; +wire main_a7ddrphy_dq_t10; +wire [7:0] main_a7ddrphy_dq_i_data10; +wire [7:0] main_a7ddrphy_bitslip10_i; +reg [7:0] main_a7ddrphy_bitslip10_o = 8'd0; +reg [2:0] main_a7ddrphy_bitslip10_value = 3'd0; +reg [15:0] main_a7ddrphy_bitslip10_r = 16'd0; +wire main_a7ddrphy_dq_o_nodelay11; +wire main_a7ddrphy_dq_i_nodelay11; +wire main_a7ddrphy_dq_i_delayed11; +wire main_a7ddrphy_dq_t11; +wire [7:0] main_a7ddrphy_dq_i_data11; +wire [7:0] main_a7ddrphy_bitslip11_i; +reg [7:0] main_a7ddrphy_bitslip11_o = 8'd0; +reg [2:0] main_a7ddrphy_bitslip11_value = 3'd0; +reg [15:0] main_a7ddrphy_bitslip11_r = 16'd0; +wire main_a7ddrphy_dq_o_nodelay12; +wire main_a7ddrphy_dq_i_nodelay12; +wire main_a7ddrphy_dq_i_delayed12; +wire main_a7ddrphy_dq_t12; +wire [7:0] main_a7ddrphy_dq_i_data12; +wire [7:0] main_a7ddrphy_bitslip12_i; +reg [7:0] main_a7ddrphy_bitslip12_o = 8'd0; +reg [2:0] main_a7ddrphy_bitslip12_value = 3'd0; +reg [15:0] main_a7ddrphy_bitslip12_r = 16'd0; +wire main_a7ddrphy_dq_o_nodelay13; +wire main_a7ddrphy_dq_i_nodelay13; +wire main_a7ddrphy_dq_i_delayed13; +wire main_a7ddrphy_dq_t13; +wire [7:0] main_a7ddrphy_dq_i_data13; +wire [7:0] main_a7ddrphy_bitslip13_i; +reg [7:0] main_a7ddrphy_bitslip13_o = 8'd0; +reg [2:0] main_a7ddrphy_bitslip13_value = 3'd0; +reg [15:0] main_a7ddrphy_bitslip13_r = 16'd0; +wire main_a7ddrphy_dq_o_nodelay14; +wire main_a7ddrphy_dq_i_nodelay14; +wire main_a7ddrphy_dq_i_delayed14; +wire main_a7ddrphy_dq_t14; +wire [7:0] main_a7ddrphy_dq_i_data14; +wire [7:0] main_a7ddrphy_bitslip14_i; +reg [7:0] main_a7ddrphy_bitslip14_o = 8'd0; +reg [2:0] main_a7ddrphy_bitslip14_value = 3'd0; +reg [15:0] main_a7ddrphy_bitslip14_r = 16'd0; +wire main_a7ddrphy_dq_o_nodelay15; +wire main_a7ddrphy_dq_i_nodelay15; +wire main_a7ddrphy_dq_i_delayed15; +wire main_a7ddrphy_dq_t15; +wire [7:0] main_a7ddrphy_dq_i_data15; +wire [7:0] main_a7ddrphy_bitslip15_i; +reg [7:0] main_a7ddrphy_bitslip15_o = 8'd0; +reg [2:0] main_a7ddrphy_bitslip15_value = 3'd0; +reg [15:0] main_a7ddrphy_bitslip15_r = 16'd0; +reg main_a7ddrphy_n_rddata_en0 = 1'd0; +reg main_a7ddrphy_n_rddata_en1 = 1'd0; +reg main_a7ddrphy_n_rddata_en2 = 1'd0; +reg main_a7ddrphy_n_rddata_en3 = 1'd0; +reg main_a7ddrphy_n_rddata_en4 = 1'd0; +reg main_a7ddrphy_n_rddata_en5 = 1'd0; +reg main_a7ddrphy_n_rddata_en6 = 1'd0; +reg main_a7ddrphy_n_rddata_en7 = 1'd0; +wire main_a7ddrphy_oe; +reg [3:0] main_a7ddrphy_last_wrdata_en = 4'd0; +wire [13:0] main_sdram_inti_p0_address; +wire [2:0] main_sdram_inti_p0_bank; +reg main_sdram_inti_p0_cas_n = 1'd1; +reg main_sdram_inti_p0_cs_n = 1'd1; +reg main_sdram_inti_p0_ras_n = 1'd1; +reg main_sdram_inti_p0_we_n = 1'd1; +wire main_sdram_inti_p0_cke; +wire main_sdram_inti_p0_odt; +wire main_sdram_inti_p0_reset_n; +reg main_sdram_inti_p0_act_n = 1'd1; +wire [31:0] main_sdram_inti_p0_wrdata; +wire main_sdram_inti_p0_wrdata_en; +wire [3:0] main_sdram_inti_p0_wrdata_mask; +wire main_sdram_inti_p0_rddata_en; +reg [31:0] main_sdram_inti_p0_rddata = 32'd0; +reg main_sdram_inti_p0_rddata_valid = 1'd0; +wire [13:0] main_sdram_inti_p1_address; +wire [2:0] main_sdram_inti_p1_bank; +reg main_sdram_inti_p1_cas_n = 1'd1; +reg main_sdram_inti_p1_cs_n = 1'd1; +reg main_sdram_inti_p1_ras_n = 1'd1; +reg main_sdram_inti_p1_we_n = 1'd1; +wire main_sdram_inti_p1_cke; +wire main_sdram_inti_p1_odt; +wire main_sdram_inti_p1_reset_n; +reg main_sdram_inti_p1_act_n = 1'd1; +wire [31:0] main_sdram_inti_p1_wrdata; +wire main_sdram_inti_p1_wrdata_en; +wire [3:0] main_sdram_inti_p1_wrdata_mask; +wire main_sdram_inti_p1_rddata_en; +reg [31:0] main_sdram_inti_p1_rddata = 32'd0; +reg main_sdram_inti_p1_rddata_valid = 1'd0; +wire [13:0] main_sdram_inti_p2_address; +wire [2:0] main_sdram_inti_p2_bank; +reg main_sdram_inti_p2_cas_n = 1'd1; +reg main_sdram_inti_p2_cs_n = 1'd1; +reg main_sdram_inti_p2_ras_n = 1'd1; +reg main_sdram_inti_p2_we_n = 1'd1; +wire main_sdram_inti_p2_cke; +wire main_sdram_inti_p2_odt; +wire main_sdram_inti_p2_reset_n; +reg main_sdram_inti_p2_act_n = 1'd1; +wire [31:0] main_sdram_inti_p2_wrdata; +wire main_sdram_inti_p2_wrdata_en; +wire [3:0] main_sdram_inti_p2_wrdata_mask; +wire main_sdram_inti_p2_rddata_en; +reg [31:0] main_sdram_inti_p2_rddata = 32'd0; +reg main_sdram_inti_p2_rddata_valid = 1'd0; +wire [13:0] main_sdram_inti_p3_address; +wire [2:0] main_sdram_inti_p3_bank; +reg main_sdram_inti_p3_cas_n = 1'd1; +reg main_sdram_inti_p3_cs_n = 1'd1; +reg main_sdram_inti_p3_ras_n = 1'd1; +reg main_sdram_inti_p3_we_n = 1'd1; +wire main_sdram_inti_p3_cke; +wire main_sdram_inti_p3_odt; +wire main_sdram_inti_p3_reset_n; +reg main_sdram_inti_p3_act_n = 1'd1; +wire [31:0] main_sdram_inti_p3_wrdata; +wire main_sdram_inti_p3_wrdata_en; +wire [3:0] main_sdram_inti_p3_wrdata_mask; +wire main_sdram_inti_p3_rddata_en; +reg [31:0] main_sdram_inti_p3_rddata = 32'd0; +reg main_sdram_inti_p3_rddata_valid = 1'd0; +wire [13:0] main_sdram_slave_p0_address; +wire [2:0] main_sdram_slave_p0_bank; +wire main_sdram_slave_p0_cas_n; +wire main_sdram_slave_p0_cs_n; +wire main_sdram_slave_p0_ras_n; +wire main_sdram_slave_p0_we_n; +wire main_sdram_slave_p0_cke; +wire main_sdram_slave_p0_odt; +wire main_sdram_slave_p0_reset_n; +wire main_sdram_slave_p0_act_n; +wire [31:0] main_sdram_slave_p0_wrdata; +wire main_sdram_slave_p0_wrdata_en; +wire [3:0] main_sdram_slave_p0_wrdata_mask; +wire main_sdram_slave_p0_rddata_en; +reg [31:0] main_sdram_slave_p0_rddata = 32'd0; +reg main_sdram_slave_p0_rddata_valid = 1'd0; +wire [13:0] main_sdram_slave_p1_address; +wire [2:0] main_sdram_slave_p1_bank; +wire main_sdram_slave_p1_cas_n; +wire main_sdram_slave_p1_cs_n; +wire main_sdram_slave_p1_ras_n; +wire main_sdram_slave_p1_we_n; +wire main_sdram_slave_p1_cke; +wire main_sdram_slave_p1_odt; +wire main_sdram_slave_p1_reset_n; +wire main_sdram_slave_p1_act_n; +wire [31:0] main_sdram_slave_p1_wrdata; +wire main_sdram_slave_p1_wrdata_en; +wire [3:0] main_sdram_slave_p1_wrdata_mask; +wire main_sdram_slave_p1_rddata_en; +reg [31:0] main_sdram_slave_p1_rddata = 32'd0; +reg main_sdram_slave_p1_rddata_valid = 1'd0; +wire [13:0] main_sdram_slave_p2_address; +wire [2:0] main_sdram_slave_p2_bank; +wire main_sdram_slave_p2_cas_n; +wire main_sdram_slave_p2_cs_n; +wire main_sdram_slave_p2_ras_n; +wire main_sdram_slave_p2_we_n; +wire main_sdram_slave_p2_cke; +wire main_sdram_slave_p2_odt; +wire main_sdram_slave_p2_reset_n; +wire main_sdram_slave_p2_act_n; +wire [31:0] main_sdram_slave_p2_wrdata; +wire main_sdram_slave_p2_wrdata_en; +wire [3:0] main_sdram_slave_p2_wrdata_mask; +wire main_sdram_slave_p2_rddata_en; +reg [31:0] main_sdram_slave_p2_rddata = 32'd0; +reg main_sdram_slave_p2_rddata_valid = 1'd0; +wire [13:0] main_sdram_slave_p3_address; +wire [2:0] main_sdram_slave_p3_bank; +wire main_sdram_slave_p3_cas_n; +wire main_sdram_slave_p3_cs_n; +wire main_sdram_slave_p3_ras_n; +wire main_sdram_slave_p3_we_n; +wire main_sdram_slave_p3_cke; +wire main_sdram_slave_p3_odt; +wire main_sdram_slave_p3_reset_n; +wire main_sdram_slave_p3_act_n; +wire [31:0] main_sdram_slave_p3_wrdata; +wire main_sdram_slave_p3_wrdata_en; +wire [3:0] main_sdram_slave_p3_wrdata_mask; +wire main_sdram_slave_p3_rddata_en; +reg [31:0] main_sdram_slave_p3_rddata = 32'd0; +reg main_sdram_slave_p3_rddata_valid = 1'd0; +reg [13:0] main_sdram_master_p0_address = 14'd0; +reg [2:0] main_sdram_master_p0_bank = 3'd0; +reg main_sdram_master_p0_cas_n = 1'd1; +reg main_sdram_master_p0_cs_n = 1'd1; +reg main_sdram_master_p0_ras_n = 1'd1; +reg main_sdram_master_p0_we_n = 1'd1; +reg main_sdram_master_p0_cke = 1'd0; +reg main_sdram_master_p0_odt = 1'd0; +reg main_sdram_master_p0_reset_n = 1'd0; +reg main_sdram_master_p0_act_n = 1'd1; +reg [31:0] main_sdram_master_p0_wrdata = 32'd0; +reg main_sdram_master_p0_wrdata_en = 1'd0; +reg [3:0] main_sdram_master_p0_wrdata_mask = 4'd0; +reg main_sdram_master_p0_rddata_en = 1'd0; +wire [31:0] main_sdram_master_p0_rddata; +wire main_sdram_master_p0_rddata_valid; +reg [13:0] main_sdram_master_p1_address = 14'd0; +reg [2:0] main_sdram_master_p1_bank = 3'd0; +reg main_sdram_master_p1_cas_n = 1'd1; +reg main_sdram_master_p1_cs_n = 1'd1; +reg main_sdram_master_p1_ras_n = 1'd1; +reg main_sdram_master_p1_we_n = 1'd1; +reg main_sdram_master_p1_cke = 1'd0; +reg main_sdram_master_p1_odt = 1'd0; +reg main_sdram_master_p1_reset_n = 1'd0; +reg main_sdram_master_p1_act_n = 1'd1; +reg [31:0] main_sdram_master_p1_wrdata = 32'd0; +reg main_sdram_master_p1_wrdata_en = 1'd0; +reg [3:0] main_sdram_master_p1_wrdata_mask = 4'd0; +reg main_sdram_master_p1_rddata_en = 1'd0; +wire [31:0] main_sdram_master_p1_rddata; +wire main_sdram_master_p1_rddata_valid; +reg [13:0] main_sdram_master_p2_address = 14'd0; +reg [2:0] main_sdram_master_p2_bank = 3'd0; +reg main_sdram_master_p2_cas_n = 1'd1; +reg main_sdram_master_p2_cs_n = 1'd1; +reg main_sdram_master_p2_ras_n = 1'd1; +reg main_sdram_master_p2_we_n = 1'd1; +reg main_sdram_master_p2_cke = 1'd0; +reg main_sdram_master_p2_odt = 1'd0; +reg main_sdram_master_p2_reset_n = 1'd0; +reg main_sdram_master_p2_act_n = 1'd1; +reg [31:0] main_sdram_master_p2_wrdata = 32'd0; +reg main_sdram_master_p2_wrdata_en = 1'd0; +reg [3:0] main_sdram_master_p2_wrdata_mask = 4'd0; +reg main_sdram_master_p2_rddata_en = 1'd0; +wire [31:0] main_sdram_master_p2_rddata; +wire main_sdram_master_p2_rddata_valid; +reg [13:0] main_sdram_master_p3_address = 14'd0; +reg [2:0] main_sdram_master_p3_bank = 3'd0; +reg main_sdram_master_p3_cas_n = 1'd1; +reg main_sdram_master_p3_cs_n = 1'd1; +reg main_sdram_master_p3_ras_n = 1'd1; +reg main_sdram_master_p3_we_n = 1'd1; +reg main_sdram_master_p3_cke = 1'd0; +reg main_sdram_master_p3_odt = 1'd0; +reg main_sdram_master_p3_reset_n = 1'd0; +reg main_sdram_master_p3_act_n = 1'd1; +reg [31:0] main_sdram_master_p3_wrdata = 32'd0; +reg main_sdram_master_p3_wrdata_en = 1'd0; +reg [3:0] main_sdram_master_p3_wrdata_mask = 4'd0; +reg main_sdram_master_p3_rddata_en = 1'd0; +wire [31:0] main_sdram_master_p3_rddata; +wire main_sdram_master_p3_rddata_valid; +reg [3:0] main_sdram_storage = 4'd0; +reg main_sdram_re = 1'd0; +reg [5:0] main_sdram_phaseinjector0_command_storage = 6'd0; +reg main_sdram_phaseinjector0_command_re = 1'd0; +wire main_sdram_phaseinjector0_command_issue_re; +wire main_sdram_phaseinjector0_command_issue_r; +wire main_sdram_phaseinjector0_command_issue_we; +reg main_sdram_phaseinjector0_command_issue_w = 1'd0; +reg [13:0] main_sdram_phaseinjector0_address_storage = 14'd0; +reg main_sdram_phaseinjector0_address_re = 1'd0; +reg [2:0] main_sdram_phaseinjector0_baddress_storage = 3'd0; +reg main_sdram_phaseinjector0_baddress_re = 1'd0; +reg [31:0] main_sdram_phaseinjector0_wrdata_storage = 32'd0; +reg main_sdram_phaseinjector0_wrdata_re = 1'd0; +reg [31:0] main_sdram_phaseinjector0_status = 32'd0; +wire main_sdram_phaseinjector0_we; +reg [5:0] main_sdram_phaseinjector1_command_storage = 6'd0; +reg main_sdram_phaseinjector1_command_re = 1'd0; +wire main_sdram_phaseinjector1_command_issue_re; +wire main_sdram_phaseinjector1_command_issue_r; +wire main_sdram_phaseinjector1_command_issue_we; +reg main_sdram_phaseinjector1_command_issue_w = 1'd0; +reg [13:0] main_sdram_phaseinjector1_address_storage = 14'd0; +reg main_sdram_phaseinjector1_address_re = 1'd0; +reg [2:0] main_sdram_phaseinjector1_baddress_storage = 3'd0; +reg main_sdram_phaseinjector1_baddress_re = 1'd0; +reg [31:0] main_sdram_phaseinjector1_wrdata_storage = 32'd0; +reg main_sdram_phaseinjector1_wrdata_re = 1'd0; +reg [31:0] main_sdram_phaseinjector1_status = 32'd0; +wire main_sdram_phaseinjector1_we; +reg [5:0] main_sdram_phaseinjector2_command_storage = 6'd0; +reg main_sdram_phaseinjector2_command_re = 1'd0; +wire main_sdram_phaseinjector2_command_issue_re; +wire main_sdram_phaseinjector2_command_issue_r; +wire main_sdram_phaseinjector2_command_issue_we; +reg main_sdram_phaseinjector2_command_issue_w = 1'd0; +reg [13:0] main_sdram_phaseinjector2_address_storage = 14'd0; +reg main_sdram_phaseinjector2_address_re = 1'd0; +reg [2:0] main_sdram_phaseinjector2_baddress_storage = 3'd0; +reg main_sdram_phaseinjector2_baddress_re = 1'd0; +reg [31:0] main_sdram_phaseinjector2_wrdata_storage = 32'd0; +reg main_sdram_phaseinjector2_wrdata_re = 1'd0; +reg [31:0] main_sdram_phaseinjector2_status = 32'd0; +wire main_sdram_phaseinjector2_we; +reg [5:0] main_sdram_phaseinjector3_command_storage = 6'd0; +reg main_sdram_phaseinjector3_command_re = 1'd0; +wire main_sdram_phaseinjector3_command_issue_re; +wire main_sdram_phaseinjector3_command_issue_r; +wire main_sdram_phaseinjector3_command_issue_we; +reg main_sdram_phaseinjector3_command_issue_w = 1'd0; +reg [13:0] main_sdram_phaseinjector3_address_storage = 14'd0; +reg main_sdram_phaseinjector3_address_re = 1'd0; +reg [2:0] main_sdram_phaseinjector3_baddress_storage = 3'd0; +reg main_sdram_phaseinjector3_baddress_re = 1'd0; +reg [31:0] main_sdram_phaseinjector3_wrdata_storage = 32'd0; +reg main_sdram_phaseinjector3_wrdata_re = 1'd0; +reg [31:0] main_sdram_phaseinjector3_status = 32'd0; +wire main_sdram_phaseinjector3_we; +wire main_sdram_interface_bank0_valid; +wire main_sdram_interface_bank0_ready; +wire main_sdram_interface_bank0_we; +wire [20:0] main_sdram_interface_bank0_addr; +wire main_sdram_interface_bank0_lock; +wire main_sdram_interface_bank0_wdata_ready; +wire main_sdram_interface_bank0_rdata_valid; +wire main_sdram_interface_bank1_valid; +wire main_sdram_interface_bank1_ready; +wire main_sdram_interface_bank1_we; +wire [20:0] main_sdram_interface_bank1_addr; +wire main_sdram_interface_bank1_lock; +wire main_sdram_interface_bank1_wdata_ready; +wire main_sdram_interface_bank1_rdata_valid; +wire main_sdram_interface_bank2_valid; +wire main_sdram_interface_bank2_ready; +wire main_sdram_interface_bank2_we; +wire [20:0] main_sdram_interface_bank2_addr; +wire main_sdram_interface_bank2_lock; +wire main_sdram_interface_bank2_wdata_ready; +wire main_sdram_interface_bank2_rdata_valid; +wire main_sdram_interface_bank3_valid; +wire main_sdram_interface_bank3_ready; +wire main_sdram_interface_bank3_we; +wire [20:0] main_sdram_interface_bank3_addr; +wire main_sdram_interface_bank3_lock; +wire main_sdram_interface_bank3_wdata_ready; +wire main_sdram_interface_bank3_rdata_valid; +wire main_sdram_interface_bank4_valid; +wire main_sdram_interface_bank4_ready; +wire main_sdram_interface_bank4_we; +wire [20:0] main_sdram_interface_bank4_addr; +wire main_sdram_interface_bank4_lock; +wire main_sdram_interface_bank4_wdata_ready; +wire main_sdram_interface_bank4_rdata_valid; +wire main_sdram_interface_bank5_valid; +wire main_sdram_interface_bank5_ready; +wire main_sdram_interface_bank5_we; +wire [20:0] main_sdram_interface_bank5_addr; +wire main_sdram_interface_bank5_lock; +wire main_sdram_interface_bank5_wdata_ready; +wire main_sdram_interface_bank5_rdata_valid; +wire main_sdram_interface_bank6_valid; +wire main_sdram_interface_bank6_ready; +wire main_sdram_interface_bank6_we; +wire [20:0] main_sdram_interface_bank6_addr; +wire main_sdram_interface_bank6_lock; +wire main_sdram_interface_bank6_wdata_ready; +wire main_sdram_interface_bank6_rdata_valid; +wire main_sdram_interface_bank7_valid; +wire main_sdram_interface_bank7_ready; +wire main_sdram_interface_bank7_we; +wire [20:0] main_sdram_interface_bank7_addr; +wire main_sdram_interface_bank7_lock; +wire main_sdram_interface_bank7_wdata_ready; +wire main_sdram_interface_bank7_rdata_valid; +reg [127:0] main_sdram_interface_wdata = 128'd0; +reg [15:0] main_sdram_interface_wdata_we = 16'd0; +wire [127:0] main_sdram_interface_rdata; +reg [13:0] main_sdram_dfi_p0_address = 14'd0; +reg [2:0] main_sdram_dfi_p0_bank = 3'd0; +reg main_sdram_dfi_p0_cas_n = 1'd1; +reg main_sdram_dfi_p0_cs_n = 1'd1; +reg main_sdram_dfi_p0_ras_n = 1'd1; +reg main_sdram_dfi_p0_we_n = 1'd1; +wire main_sdram_dfi_p0_cke; +wire main_sdram_dfi_p0_odt; +wire main_sdram_dfi_p0_reset_n; +reg main_sdram_dfi_p0_act_n = 1'd1; +wire [31:0] main_sdram_dfi_p0_wrdata; +reg main_sdram_dfi_p0_wrdata_en = 1'd0; +wire [3:0] main_sdram_dfi_p0_wrdata_mask; +reg main_sdram_dfi_p0_rddata_en = 1'd0; +wire [31:0] main_sdram_dfi_p0_rddata; +wire main_sdram_dfi_p0_rddata_valid; +reg [13:0] main_sdram_dfi_p1_address = 14'd0; +reg [2:0] main_sdram_dfi_p1_bank = 3'd0; +reg main_sdram_dfi_p1_cas_n = 1'd1; +reg main_sdram_dfi_p1_cs_n = 1'd1; +reg main_sdram_dfi_p1_ras_n = 1'd1; +reg main_sdram_dfi_p1_we_n = 1'd1; +wire main_sdram_dfi_p1_cke; +wire main_sdram_dfi_p1_odt; +wire main_sdram_dfi_p1_reset_n; +reg main_sdram_dfi_p1_act_n = 1'd1; +wire [31:0] main_sdram_dfi_p1_wrdata; +reg main_sdram_dfi_p1_wrdata_en = 1'd0; +wire [3:0] main_sdram_dfi_p1_wrdata_mask; +reg main_sdram_dfi_p1_rddata_en = 1'd0; +wire [31:0] main_sdram_dfi_p1_rddata; +wire main_sdram_dfi_p1_rddata_valid; +reg [13:0] main_sdram_dfi_p2_address = 14'd0; +reg [2:0] main_sdram_dfi_p2_bank = 3'd0; +reg main_sdram_dfi_p2_cas_n = 1'd1; +reg main_sdram_dfi_p2_cs_n = 1'd1; +reg main_sdram_dfi_p2_ras_n = 1'd1; +reg main_sdram_dfi_p2_we_n = 1'd1; +wire main_sdram_dfi_p2_cke; +wire main_sdram_dfi_p2_odt; +wire main_sdram_dfi_p2_reset_n; +reg main_sdram_dfi_p2_act_n = 1'd1; +wire [31:0] main_sdram_dfi_p2_wrdata; +reg main_sdram_dfi_p2_wrdata_en = 1'd0; +wire [3:0] main_sdram_dfi_p2_wrdata_mask; +reg main_sdram_dfi_p2_rddata_en = 1'd0; +wire [31:0] main_sdram_dfi_p2_rddata; +wire main_sdram_dfi_p2_rddata_valid; +reg [13:0] main_sdram_dfi_p3_address = 14'd0; +reg [2:0] main_sdram_dfi_p3_bank = 3'd0; +reg main_sdram_dfi_p3_cas_n = 1'd1; +reg main_sdram_dfi_p3_cs_n = 1'd1; +reg main_sdram_dfi_p3_ras_n = 1'd1; +reg main_sdram_dfi_p3_we_n = 1'd1; +wire main_sdram_dfi_p3_cke; +wire main_sdram_dfi_p3_odt; +wire main_sdram_dfi_p3_reset_n; +reg main_sdram_dfi_p3_act_n = 1'd1; +wire [31:0] main_sdram_dfi_p3_wrdata; +reg main_sdram_dfi_p3_wrdata_en = 1'd0; +wire [3:0] main_sdram_dfi_p3_wrdata_mask; +reg main_sdram_dfi_p3_rddata_en = 1'd0; +wire [31:0] main_sdram_dfi_p3_rddata; +wire main_sdram_dfi_p3_rddata_valid; +reg main_sdram_cmd_valid = 1'd0; +reg main_sdram_cmd_ready = 1'd0; +reg main_sdram_cmd_last = 1'd0; +reg [13:0] main_sdram_cmd_payload_a = 14'd0; +reg [2:0] main_sdram_cmd_payload_ba = 3'd0; +reg main_sdram_cmd_payload_cas = 1'd0; +reg main_sdram_cmd_payload_ras = 1'd0; +reg main_sdram_cmd_payload_we = 1'd0; +reg main_sdram_cmd_payload_is_read = 1'd0; +reg main_sdram_cmd_payload_is_write = 1'd0; +wire main_sdram_wants_refresh; +wire main_sdram_wants_zqcs; +wire main_sdram_timer_wait; +wire main_sdram_timer_done0; +wire [8:0] main_sdram_timer_count0; +wire main_sdram_timer_done1; +reg [8:0] main_sdram_timer_count1 = 9'd390; +wire main_sdram_postponer_req_i; +reg main_sdram_postponer_req_o = 1'd0; +reg main_sdram_postponer_count = 1'd0; +reg main_sdram_sequencer_start0 = 1'd0; +wire main_sdram_sequencer_done0; +wire main_sdram_sequencer_start1; +reg main_sdram_sequencer_done1 = 1'd0; +reg [5:0] main_sdram_sequencer_counter = 6'd0; +reg main_sdram_sequencer_count = 1'd0; +wire main_sdram_zqcs_timer_wait; +wire main_sdram_zqcs_timer_done0; +wire [25:0] main_sdram_zqcs_timer_count0; +wire main_sdram_zqcs_timer_done1; +reg [25:0] main_sdram_zqcs_timer_count1 = 26'd49999999; +reg main_sdram_zqcs_executer_start = 1'd0; +reg main_sdram_zqcs_executer_done = 1'd0; +reg [4:0] main_sdram_zqcs_executer_counter = 5'd0; +wire main_sdram_bankmachine0_req_valid; +wire main_sdram_bankmachine0_req_ready; +wire main_sdram_bankmachine0_req_we; +wire [20:0] main_sdram_bankmachine0_req_addr; +wire main_sdram_bankmachine0_req_lock; +reg main_sdram_bankmachine0_req_wdata_ready = 1'd0; +reg main_sdram_bankmachine0_req_rdata_valid = 1'd0; +wire main_sdram_bankmachine0_refresh_req; +reg main_sdram_bankmachine0_refresh_gnt = 1'd0; +reg main_sdram_bankmachine0_cmd_valid = 1'd0; +reg main_sdram_bankmachine0_cmd_ready = 1'd0; +reg [13:0] main_sdram_bankmachine0_cmd_payload_a = 14'd0; +wire [2:0] main_sdram_bankmachine0_cmd_payload_ba; +reg main_sdram_bankmachine0_cmd_payload_cas = 1'd0; +reg main_sdram_bankmachine0_cmd_payload_ras = 1'd0; +reg main_sdram_bankmachine0_cmd_payload_we = 1'd0; +reg main_sdram_bankmachine0_cmd_payload_is_cmd = 1'd0; +reg main_sdram_bankmachine0_cmd_payload_is_read = 1'd0; +reg main_sdram_bankmachine0_cmd_payload_is_write = 1'd0; +reg main_sdram_bankmachine0_auto_precharge = 1'd0; +wire main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid; +wire main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready; +reg main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +wire main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid; +wire main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready; +wire main_sdram_bankmachine0_cmd_buffer_lookahead_source_first; +wire main_sdram_bankmachine0_cmd_buffer_lookahead_source_last; +wire main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we; +wire [20:0] main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +wire main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we; +wire main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +wire main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re; +wire main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +wire [23:0] main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +wire [23:0] main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +reg [3:0] main_sdram_bankmachine0_cmd_buffer_lookahead_level = 4'd0; +reg main_sdram_bankmachine0_cmd_buffer_lookahead_replace = 1'd0; +reg [2:0] main_sdram_bankmachine0_cmd_buffer_lookahead_produce = 3'd0; +reg [2:0] main_sdram_bankmachine0_cmd_buffer_lookahead_consume = 3'd0; +reg [2:0] main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr = 3'd0; +wire [23:0] main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r; +wire main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we; +wire [23:0] main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; +wire main_sdram_bankmachine0_cmd_buffer_lookahead_do_read; +wire [2:0] main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr; +wire [23:0] main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +wire main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first; +wire main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last; +wire main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +wire main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +wire main_sdram_bankmachine0_cmd_buffer_sink_valid; +wire main_sdram_bankmachine0_cmd_buffer_sink_ready; +wire main_sdram_bankmachine0_cmd_buffer_sink_first; +wire main_sdram_bankmachine0_cmd_buffer_sink_last; +wire main_sdram_bankmachine0_cmd_buffer_sink_payload_we; +wire [20:0] main_sdram_bankmachine0_cmd_buffer_sink_payload_addr; +wire main_sdram_bankmachine0_cmd_buffer_source_valid; +wire main_sdram_bankmachine0_cmd_buffer_source_ready; +wire main_sdram_bankmachine0_cmd_buffer_source_first; +wire main_sdram_bankmachine0_cmd_buffer_source_last; +reg main_sdram_bankmachine0_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_sdram_bankmachine0_cmd_buffer_source_payload_addr = 21'd0; +wire main_sdram_bankmachine0_cmd_buffer_pipe_ce; +wire main_sdram_bankmachine0_cmd_buffer_busy; +reg main_sdram_bankmachine0_cmd_buffer_valid_n = 1'd0; +reg main_sdram_bankmachine0_cmd_buffer_first_n = 1'd0; +reg main_sdram_bankmachine0_cmd_buffer_last_n = 1'd0; +reg [13:0] main_sdram_bankmachine0_row = 14'd0; +reg main_sdram_bankmachine0_row_opened = 1'd0; +wire main_sdram_bankmachine0_row_hit; +reg main_sdram_bankmachine0_row_open = 1'd0; +reg main_sdram_bankmachine0_row_close = 1'd0; +reg main_sdram_bankmachine0_row_col_n_addr_sel = 1'd0; +wire main_sdram_bankmachine0_twtpcon_valid; +(* dont_touch = "true" *) reg main_sdram_bankmachine0_twtpcon_ready = 1'd1; +reg [2:0] main_sdram_bankmachine0_twtpcon_count = 3'd0; +wire main_sdram_bankmachine0_trccon_valid; +(* dont_touch = "true" *) reg main_sdram_bankmachine0_trccon_ready = 1'd1; +reg [1:0] main_sdram_bankmachine0_trccon_count = 2'd0; +wire main_sdram_bankmachine0_trascon_valid; +(* dont_touch = "true" *) reg main_sdram_bankmachine0_trascon_ready = 1'd1; +reg [1:0] main_sdram_bankmachine0_trascon_count = 2'd0; +wire main_sdram_bankmachine1_req_valid; +wire main_sdram_bankmachine1_req_ready; +wire main_sdram_bankmachine1_req_we; +wire [20:0] main_sdram_bankmachine1_req_addr; +wire main_sdram_bankmachine1_req_lock; +reg main_sdram_bankmachine1_req_wdata_ready = 1'd0; +reg main_sdram_bankmachine1_req_rdata_valid = 1'd0; +wire main_sdram_bankmachine1_refresh_req; +reg main_sdram_bankmachine1_refresh_gnt = 1'd0; +reg main_sdram_bankmachine1_cmd_valid = 1'd0; +reg main_sdram_bankmachine1_cmd_ready = 1'd0; +reg [13:0] main_sdram_bankmachine1_cmd_payload_a = 14'd0; +wire [2:0] main_sdram_bankmachine1_cmd_payload_ba; +reg main_sdram_bankmachine1_cmd_payload_cas = 1'd0; +reg main_sdram_bankmachine1_cmd_payload_ras = 1'd0; +reg main_sdram_bankmachine1_cmd_payload_we = 1'd0; +reg main_sdram_bankmachine1_cmd_payload_is_cmd = 1'd0; +reg main_sdram_bankmachine1_cmd_payload_is_read = 1'd0; +reg main_sdram_bankmachine1_cmd_payload_is_write = 1'd0; +reg main_sdram_bankmachine1_auto_precharge = 1'd0; +wire main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid; +wire main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready; +reg main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +wire main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid; +wire main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready; +wire main_sdram_bankmachine1_cmd_buffer_lookahead_source_first; +wire main_sdram_bankmachine1_cmd_buffer_lookahead_source_last; +wire main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we; +wire [20:0] main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +wire main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we; +wire main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +wire main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re; +wire main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +wire [23:0] main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +wire [23:0] main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +reg [3:0] main_sdram_bankmachine1_cmd_buffer_lookahead_level = 4'd0; +reg main_sdram_bankmachine1_cmd_buffer_lookahead_replace = 1'd0; +reg [2:0] main_sdram_bankmachine1_cmd_buffer_lookahead_produce = 3'd0; +reg [2:0] main_sdram_bankmachine1_cmd_buffer_lookahead_consume = 3'd0; +reg [2:0] main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr = 3'd0; +wire [23:0] main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r; +wire main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we; +wire [23:0] main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; +wire main_sdram_bankmachine1_cmd_buffer_lookahead_do_read; +wire [2:0] main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr; +wire [23:0] main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +wire main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first; +wire main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last; +wire main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +wire main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +wire main_sdram_bankmachine1_cmd_buffer_sink_valid; +wire main_sdram_bankmachine1_cmd_buffer_sink_ready; +wire main_sdram_bankmachine1_cmd_buffer_sink_first; +wire main_sdram_bankmachine1_cmd_buffer_sink_last; +wire main_sdram_bankmachine1_cmd_buffer_sink_payload_we; +wire [20:0] main_sdram_bankmachine1_cmd_buffer_sink_payload_addr; +wire main_sdram_bankmachine1_cmd_buffer_source_valid; +wire main_sdram_bankmachine1_cmd_buffer_source_ready; +wire main_sdram_bankmachine1_cmd_buffer_source_first; +wire main_sdram_bankmachine1_cmd_buffer_source_last; +reg main_sdram_bankmachine1_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_sdram_bankmachine1_cmd_buffer_source_payload_addr = 21'd0; +wire main_sdram_bankmachine1_cmd_buffer_pipe_ce; +wire main_sdram_bankmachine1_cmd_buffer_busy; +reg main_sdram_bankmachine1_cmd_buffer_valid_n = 1'd0; +reg main_sdram_bankmachine1_cmd_buffer_first_n = 1'd0; +reg main_sdram_bankmachine1_cmd_buffer_last_n = 1'd0; +reg [13:0] main_sdram_bankmachine1_row = 14'd0; +reg main_sdram_bankmachine1_row_opened = 1'd0; +wire main_sdram_bankmachine1_row_hit; +reg main_sdram_bankmachine1_row_open = 1'd0; +reg main_sdram_bankmachine1_row_close = 1'd0; +reg main_sdram_bankmachine1_row_col_n_addr_sel = 1'd0; +wire main_sdram_bankmachine1_twtpcon_valid; +(* dont_touch = "true" *) reg main_sdram_bankmachine1_twtpcon_ready = 1'd1; +reg [2:0] main_sdram_bankmachine1_twtpcon_count = 3'd0; +wire main_sdram_bankmachine1_trccon_valid; +(* dont_touch = "true" *) reg main_sdram_bankmachine1_trccon_ready = 1'd1; +reg [1:0] main_sdram_bankmachine1_trccon_count = 2'd0; +wire main_sdram_bankmachine1_trascon_valid; +(* dont_touch = "true" *) reg main_sdram_bankmachine1_trascon_ready = 1'd1; +reg [1:0] main_sdram_bankmachine1_trascon_count = 2'd0; +wire main_sdram_bankmachine2_req_valid; +wire main_sdram_bankmachine2_req_ready; +wire main_sdram_bankmachine2_req_we; +wire [20:0] main_sdram_bankmachine2_req_addr; +wire main_sdram_bankmachine2_req_lock; +reg main_sdram_bankmachine2_req_wdata_ready = 1'd0; +reg main_sdram_bankmachine2_req_rdata_valid = 1'd0; +wire main_sdram_bankmachine2_refresh_req; +reg main_sdram_bankmachine2_refresh_gnt = 1'd0; +reg main_sdram_bankmachine2_cmd_valid = 1'd0; +reg main_sdram_bankmachine2_cmd_ready = 1'd0; +reg [13:0] main_sdram_bankmachine2_cmd_payload_a = 14'd0; +wire [2:0] main_sdram_bankmachine2_cmd_payload_ba; +reg main_sdram_bankmachine2_cmd_payload_cas = 1'd0; +reg main_sdram_bankmachine2_cmd_payload_ras = 1'd0; +reg main_sdram_bankmachine2_cmd_payload_we = 1'd0; +reg main_sdram_bankmachine2_cmd_payload_is_cmd = 1'd0; +reg main_sdram_bankmachine2_cmd_payload_is_read = 1'd0; +reg main_sdram_bankmachine2_cmd_payload_is_write = 1'd0; +reg main_sdram_bankmachine2_auto_precharge = 1'd0; +wire main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid; +wire main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready; +reg main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +wire main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid; +wire main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready; +wire main_sdram_bankmachine2_cmd_buffer_lookahead_source_first; +wire main_sdram_bankmachine2_cmd_buffer_lookahead_source_last; +wire main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we; +wire [20:0] main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +wire main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we; +wire main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +wire main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re; +wire main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +wire [23:0] main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +wire [23:0] main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +reg [3:0] main_sdram_bankmachine2_cmd_buffer_lookahead_level = 4'd0; +reg main_sdram_bankmachine2_cmd_buffer_lookahead_replace = 1'd0; +reg [2:0] main_sdram_bankmachine2_cmd_buffer_lookahead_produce = 3'd0; +reg [2:0] main_sdram_bankmachine2_cmd_buffer_lookahead_consume = 3'd0; +reg [2:0] main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr = 3'd0; +wire [23:0] main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r; +wire main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we; +wire [23:0] main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; +wire main_sdram_bankmachine2_cmd_buffer_lookahead_do_read; +wire [2:0] main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr; +wire [23:0] main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +wire main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first; +wire main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last; +wire main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +wire main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +wire main_sdram_bankmachine2_cmd_buffer_sink_valid; +wire main_sdram_bankmachine2_cmd_buffer_sink_ready; +wire main_sdram_bankmachine2_cmd_buffer_sink_first; +wire main_sdram_bankmachine2_cmd_buffer_sink_last; +wire main_sdram_bankmachine2_cmd_buffer_sink_payload_we; +wire [20:0] main_sdram_bankmachine2_cmd_buffer_sink_payload_addr; +wire main_sdram_bankmachine2_cmd_buffer_source_valid; +wire main_sdram_bankmachine2_cmd_buffer_source_ready; +wire main_sdram_bankmachine2_cmd_buffer_source_first; +wire main_sdram_bankmachine2_cmd_buffer_source_last; +reg main_sdram_bankmachine2_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_sdram_bankmachine2_cmd_buffer_source_payload_addr = 21'd0; +wire main_sdram_bankmachine2_cmd_buffer_pipe_ce; +wire main_sdram_bankmachine2_cmd_buffer_busy; +reg main_sdram_bankmachine2_cmd_buffer_valid_n = 1'd0; +reg main_sdram_bankmachine2_cmd_buffer_first_n = 1'd0; +reg main_sdram_bankmachine2_cmd_buffer_last_n = 1'd0; +reg [13:0] main_sdram_bankmachine2_row = 14'd0; +reg main_sdram_bankmachine2_row_opened = 1'd0; +wire main_sdram_bankmachine2_row_hit; +reg main_sdram_bankmachine2_row_open = 1'd0; +reg main_sdram_bankmachine2_row_close = 1'd0; +reg main_sdram_bankmachine2_row_col_n_addr_sel = 1'd0; +wire main_sdram_bankmachine2_twtpcon_valid; +(* dont_touch = "true" *) reg main_sdram_bankmachine2_twtpcon_ready = 1'd1; +reg [2:0] main_sdram_bankmachine2_twtpcon_count = 3'd0; +wire main_sdram_bankmachine2_trccon_valid; +(* dont_touch = "true" *) reg main_sdram_bankmachine2_trccon_ready = 1'd1; +reg [1:0] main_sdram_bankmachine2_trccon_count = 2'd0; +wire main_sdram_bankmachine2_trascon_valid; +(* dont_touch = "true" *) reg main_sdram_bankmachine2_trascon_ready = 1'd1; +reg [1:0] main_sdram_bankmachine2_trascon_count = 2'd0; +wire main_sdram_bankmachine3_req_valid; +wire main_sdram_bankmachine3_req_ready; +wire main_sdram_bankmachine3_req_we; +wire [20:0] main_sdram_bankmachine3_req_addr; +wire main_sdram_bankmachine3_req_lock; +reg main_sdram_bankmachine3_req_wdata_ready = 1'd0; +reg main_sdram_bankmachine3_req_rdata_valid = 1'd0; +wire main_sdram_bankmachine3_refresh_req; +reg main_sdram_bankmachine3_refresh_gnt = 1'd0; +reg main_sdram_bankmachine3_cmd_valid = 1'd0; +reg main_sdram_bankmachine3_cmd_ready = 1'd0; +reg [13:0] main_sdram_bankmachine3_cmd_payload_a = 14'd0; +wire [2:0] main_sdram_bankmachine3_cmd_payload_ba; +reg main_sdram_bankmachine3_cmd_payload_cas = 1'd0; +reg main_sdram_bankmachine3_cmd_payload_ras = 1'd0; +reg main_sdram_bankmachine3_cmd_payload_we = 1'd0; +reg main_sdram_bankmachine3_cmd_payload_is_cmd = 1'd0; +reg main_sdram_bankmachine3_cmd_payload_is_read = 1'd0; +reg main_sdram_bankmachine3_cmd_payload_is_write = 1'd0; +reg main_sdram_bankmachine3_auto_precharge = 1'd0; +wire main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid; +wire main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready; +reg main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +wire main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid; +wire main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready; +wire main_sdram_bankmachine3_cmd_buffer_lookahead_source_first; +wire main_sdram_bankmachine3_cmd_buffer_lookahead_source_last; +wire main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we; +wire [20:0] main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +wire main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we; +wire main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +wire main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re; +wire main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +wire [23:0] main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +wire [23:0] main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +reg [3:0] main_sdram_bankmachine3_cmd_buffer_lookahead_level = 4'd0; +reg main_sdram_bankmachine3_cmd_buffer_lookahead_replace = 1'd0; +reg [2:0] main_sdram_bankmachine3_cmd_buffer_lookahead_produce = 3'd0; +reg [2:0] main_sdram_bankmachine3_cmd_buffer_lookahead_consume = 3'd0; +reg [2:0] main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr = 3'd0; +wire [23:0] main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r; +wire main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we; +wire [23:0] main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; +wire main_sdram_bankmachine3_cmd_buffer_lookahead_do_read; +wire [2:0] main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr; +wire [23:0] main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +wire main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first; +wire main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last; +wire main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +wire main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +wire main_sdram_bankmachine3_cmd_buffer_sink_valid; +wire main_sdram_bankmachine3_cmd_buffer_sink_ready; +wire main_sdram_bankmachine3_cmd_buffer_sink_first; +wire main_sdram_bankmachine3_cmd_buffer_sink_last; +wire main_sdram_bankmachine3_cmd_buffer_sink_payload_we; +wire [20:0] main_sdram_bankmachine3_cmd_buffer_sink_payload_addr; +wire main_sdram_bankmachine3_cmd_buffer_source_valid; +wire main_sdram_bankmachine3_cmd_buffer_source_ready; +wire main_sdram_bankmachine3_cmd_buffer_source_first; +wire main_sdram_bankmachine3_cmd_buffer_source_last; +reg main_sdram_bankmachine3_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_sdram_bankmachine3_cmd_buffer_source_payload_addr = 21'd0; +wire main_sdram_bankmachine3_cmd_buffer_pipe_ce; +wire main_sdram_bankmachine3_cmd_buffer_busy; +reg main_sdram_bankmachine3_cmd_buffer_valid_n = 1'd0; +reg main_sdram_bankmachine3_cmd_buffer_first_n = 1'd0; +reg main_sdram_bankmachine3_cmd_buffer_last_n = 1'd0; +reg [13:0] main_sdram_bankmachine3_row = 14'd0; +reg main_sdram_bankmachine3_row_opened = 1'd0; +wire main_sdram_bankmachine3_row_hit; +reg main_sdram_bankmachine3_row_open = 1'd0; +reg main_sdram_bankmachine3_row_close = 1'd0; +reg main_sdram_bankmachine3_row_col_n_addr_sel = 1'd0; +wire main_sdram_bankmachine3_twtpcon_valid; +(* dont_touch = "true" *) reg main_sdram_bankmachine3_twtpcon_ready = 1'd1; +reg [2:0] main_sdram_bankmachine3_twtpcon_count = 3'd0; +wire main_sdram_bankmachine3_trccon_valid; +(* dont_touch = "true" *) reg main_sdram_bankmachine3_trccon_ready = 1'd1; +reg [1:0] main_sdram_bankmachine3_trccon_count = 2'd0; +wire main_sdram_bankmachine3_trascon_valid; +(* dont_touch = "true" *) reg main_sdram_bankmachine3_trascon_ready = 1'd1; +reg [1:0] main_sdram_bankmachine3_trascon_count = 2'd0; +wire main_sdram_bankmachine4_req_valid; +wire main_sdram_bankmachine4_req_ready; +wire main_sdram_bankmachine4_req_we; +wire [20:0] main_sdram_bankmachine4_req_addr; +wire main_sdram_bankmachine4_req_lock; +reg main_sdram_bankmachine4_req_wdata_ready = 1'd0; +reg main_sdram_bankmachine4_req_rdata_valid = 1'd0; +wire main_sdram_bankmachine4_refresh_req; +reg main_sdram_bankmachine4_refresh_gnt = 1'd0; +reg main_sdram_bankmachine4_cmd_valid = 1'd0; +reg main_sdram_bankmachine4_cmd_ready = 1'd0; +reg [13:0] main_sdram_bankmachine4_cmd_payload_a = 14'd0; +wire [2:0] main_sdram_bankmachine4_cmd_payload_ba; +reg main_sdram_bankmachine4_cmd_payload_cas = 1'd0; +reg main_sdram_bankmachine4_cmd_payload_ras = 1'd0; +reg main_sdram_bankmachine4_cmd_payload_we = 1'd0; +reg main_sdram_bankmachine4_cmd_payload_is_cmd = 1'd0; +reg main_sdram_bankmachine4_cmd_payload_is_read = 1'd0; +reg main_sdram_bankmachine4_cmd_payload_is_write = 1'd0; +reg main_sdram_bankmachine4_auto_precharge = 1'd0; +wire main_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid; +wire main_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready; +reg main_sdram_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_sdram_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] main_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +wire main_sdram_bankmachine4_cmd_buffer_lookahead_source_valid; +wire main_sdram_bankmachine4_cmd_buffer_lookahead_source_ready; +wire main_sdram_bankmachine4_cmd_buffer_lookahead_source_first; +wire main_sdram_bankmachine4_cmd_buffer_lookahead_source_last; +wire main_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we; +wire [20:0] main_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +wire main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we; +wire main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +wire main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re; +wire main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +wire [23:0] main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +wire [23:0] main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +reg [3:0] main_sdram_bankmachine4_cmd_buffer_lookahead_level = 4'd0; +reg main_sdram_bankmachine4_cmd_buffer_lookahead_replace = 1'd0; +reg [2:0] main_sdram_bankmachine4_cmd_buffer_lookahead_produce = 3'd0; +reg [2:0] main_sdram_bankmachine4_cmd_buffer_lookahead_consume = 3'd0; +reg [2:0] main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr = 3'd0; +wire [23:0] main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r; +wire main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we; +wire [23:0] main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; +wire main_sdram_bankmachine4_cmd_buffer_lookahead_do_read; +wire [2:0] main_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr; +wire [23:0] main_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +wire main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first; +wire main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last; +wire main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +wire main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +wire main_sdram_bankmachine4_cmd_buffer_sink_valid; +wire main_sdram_bankmachine4_cmd_buffer_sink_ready; +wire main_sdram_bankmachine4_cmd_buffer_sink_first; +wire main_sdram_bankmachine4_cmd_buffer_sink_last; +wire main_sdram_bankmachine4_cmd_buffer_sink_payload_we; +wire [20:0] main_sdram_bankmachine4_cmd_buffer_sink_payload_addr; +wire main_sdram_bankmachine4_cmd_buffer_source_valid; +wire main_sdram_bankmachine4_cmd_buffer_source_ready; +wire main_sdram_bankmachine4_cmd_buffer_source_first; +wire main_sdram_bankmachine4_cmd_buffer_source_last; +reg main_sdram_bankmachine4_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_sdram_bankmachine4_cmd_buffer_source_payload_addr = 21'd0; +wire main_sdram_bankmachine4_cmd_buffer_pipe_ce; +wire main_sdram_bankmachine4_cmd_buffer_busy; +reg main_sdram_bankmachine4_cmd_buffer_valid_n = 1'd0; +reg main_sdram_bankmachine4_cmd_buffer_first_n = 1'd0; +reg main_sdram_bankmachine4_cmd_buffer_last_n = 1'd0; +reg [13:0] main_sdram_bankmachine4_row = 14'd0; +reg main_sdram_bankmachine4_row_opened = 1'd0; +wire main_sdram_bankmachine4_row_hit; +reg main_sdram_bankmachine4_row_open = 1'd0; +reg main_sdram_bankmachine4_row_close = 1'd0; +reg main_sdram_bankmachine4_row_col_n_addr_sel = 1'd0; +wire main_sdram_bankmachine4_twtpcon_valid; +(* dont_touch = "true" *) reg main_sdram_bankmachine4_twtpcon_ready = 1'd1; +reg [2:0] main_sdram_bankmachine4_twtpcon_count = 3'd0; +wire main_sdram_bankmachine4_trccon_valid; +(* dont_touch = "true" *) reg main_sdram_bankmachine4_trccon_ready = 1'd1; +reg [1:0] main_sdram_bankmachine4_trccon_count = 2'd0; +wire main_sdram_bankmachine4_trascon_valid; +(* dont_touch = "true" *) reg main_sdram_bankmachine4_trascon_ready = 1'd1; +reg [1:0] main_sdram_bankmachine4_trascon_count = 2'd0; +wire main_sdram_bankmachine5_req_valid; +wire main_sdram_bankmachine5_req_ready; +wire main_sdram_bankmachine5_req_we; +wire [20:0] main_sdram_bankmachine5_req_addr; +wire main_sdram_bankmachine5_req_lock; +reg main_sdram_bankmachine5_req_wdata_ready = 1'd0; +reg main_sdram_bankmachine5_req_rdata_valid = 1'd0; +wire main_sdram_bankmachine5_refresh_req; +reg main_sdram_bankmachine5_refresh_gnt = 1'd0; +reg main_sdram_bankmachine5_cmd_valid = 1'd0; +reg main_sdram_bankmachine5_cmd_ready = 1'd0; +reg [13:0] main_sdram_bankmachine5_cmd_payload_a = 14'd0; +wire [2:0] main_sdram_bankmachine5_cmd_payload_ba; +reg main_sdram_bankmachine5_cmd_payload_cas = 1'd0; +reg main_sdram_bankmachine5_cmd_payload_ras = 1'd0; +reg main_sdram_bankmachine5_cmd_payload_we = 1'd0; +reg main_sdram_bankmachine5_cmd_payload_is_cmd = 1'd0; +reg main_sdram_bankmachine5_cmd_payload_is_read = 1'd0; +reg main_sdram_bankmachine5_cmd_payload_is_write = 1'd0; +reg main_sdram_bankmachine5_auto_precharge = 1'd0; +wire main_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid; +wire main_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready; +reg main_sdram_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_sdram_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] main_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +wire main_sdram_bankmachine5_cmd_buffer_lookahead_source_valid; +wire main_sdram_bankmachine5_cmd_buffer_lookahead_source_ready; +wire main_sdram_bankmachine5_cmd_buffer_lookahead_source_first; +wire main_sdram_bankmachine5_cmd_buffer_lookahead_source_last; +wire main_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we; +wire [20:0] main_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +wire main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we; +wire main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +wire main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re; +wire main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +wire [23:0] main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +wire [23:0] main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +reg [3:0] main_sdram_bankmachine5_cmd_buffer_lookahead_level = 4'd0; +reg main_sdram_bankmachine5_cmd_buffer_lookahead_replace = 1'd0; +reg [2:0] main_sdram_bankmachine5_cmd_buffer_lookahead_produce = 3'd0; +reg [2:0] main_sdram_bankmachine5_cmd_buffer_lookahead_consume = 3'd0; +reg [2:0] main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr = 3'd0; +wire [23:0] main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r; +wire main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we; +wire [23:0] main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; +wire main_sdram_bankmachine5_cmd_buffer_lookahead_do_read; +wire [2:0] main_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr; +wire [23:0] main_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +wire main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first; +wire main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last; +wire main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +wire main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +wire main_sdram_bankmachine5_cmd_buffer_sink_valid; +wire main_sdram_bankmachine5_cmd_buffer_sink_ready; +wire main_sdram_bankmachine5_cmd_buffer_sink_first; +wire main_sdram_bankmachine5_cmd_buffer_sink_last; +wire main_sdram_bankmachine5_cmd_buffer_sink_payload_we; +wire [20:0] main_sdram_bankmachine5_cmd_buffer_sink_payload_addr; +wire main_sdram_bankmachine5_cmd_buffer_source_valid; +wire main_sdram_bankmachine5_cmd_buffer_source_ready; +wire main_sdram_bankmachine5_cmd_buffer_source_first; +wire main_sdram_bankmachine5_cmd_buffer_source_last; +reg main_sdram_bankmachine5_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_sdram_bankmachine5_cmd_buffer_source_payload_addr = 21'd0; +wire main_sdram_bankmachine5_cmd_buffer_pipe_ce; +wire main_sdram_bankmachine5_cmd_buffer_busy; +reg main_sdram_bankmachine5_cmd_buffer_valid_n = 1'd0; +reg main_sdram_bankmachine5_cmd_buffer_first_n = 1'd0; +reg main_sdram_bankmachine5_cmd_buffer_last_n = 1'd0; +reg [13:0] main_sdram_bankmachine5_row = 14'd0; +reg main_sdram_bankmachine5_row_opened = 1'd0; +wire main_sdram_bankmachine5_row_hit; +reg main_sdram_bankmachine5_row_open = 1'd0; +reg main_sdram_bankmachine5_row_close = 1'd0; +reg main_sdram_bankmachine5_row_col_n_addr_sel = 1'd0; +wire main_sdram_bankmachine5_twtpcon_valid; +(* dont_touch = "true" *) reg main_sdram_bankmachine5_twtpcon_ready = 1'd1; +reg [2:0] main_sdram_bankmachine5_twtpcon_count = 3'd0; +wire main_sdram_bankmachine5_trccon_valid; +(* dont_touch = "true" *) reg main_sdram_bankmachine5_trccon_ready = 1'd1; +reg [1:0] main_sdram_bankmachine5_trccon_count = 2'd0; +wire main_sdram_bankmachine5_trascon_valid; +(* dont_touch = "true" *) reg main_sdram_bankmachine5_trascon_ready = 1'd1; +reg [1:0] main_sdram_bankmachine5_trascon_count = 2'd0; +wire main_sdram_bankmachine6_req_valid; +wire main_sdram_bankmachine6_req_ready; +wire main_sdram_bankmachine6_req_we; +wire [20:0] main_sdram_bankmachine6_req_addr; +wire main_sdram_bankmachine6_req_lock; +reg main_sdram_bankmachine6_req_wdata_ready = 1'd0; +reg main_sdram_bankmachine6_req_rdata_valid = 1'd0; +wire main_sdram_bankmachine6_refresh_req; +reg main_sdram_bankmachine6_refresh_gnt = 1'd0; +reg main_sdram_bankmachine6_cmd_valid = 1'd0; +reg main_sdram_bankmachine6_cmd_ready = 1'd0; +reg [13:0] main_sdram_bankmachine6_cmd_payload_a = 14'd0; +wire [2:0] main_sdram_bankmachine6_cmd_payload_ba; +reg main_sdram_bankmachine6_cmd_payload_cas = 1'd0; +reg main_sdram_bankmachine6_cmd_payload_ras = 1'd0; +reg main_sdram_bankmachine6_cmd_payload_we = 1'd0; +reg main_sdram_bankmachine6_cmd_payload_is_cmd = 1'd0; +reg main_sdram_bankmachine6_cmd_payload_is_read = 1'd0; +reg main_sdram_bankmachine6_cmd_payload_is_write = 1'd0; +reg main_sdram_bankmachine6_auto_precharge = 1'd0; +wire main_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid; +wire main_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready; +reg main_sdram_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_sdram_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] main_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +wire main_sdram_bankmachine6_cmd_buffer_lookahead_source_valid; +wire main_sdram_bankmachine6_cmd_buffer_lookahead_source_ready; +wire main_sdram_bankmachine6_cmd_buffer_lookahead_source_first; +wire main_sdram_bankmachine6_cmd_buffer_lookahead_source_last; +wire main_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we; +wire [20:0] main_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +wire main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we; +wire main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +wire main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re; +wire main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +wire [23:0] main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +wire [23:0] main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +reg [3:0] main_sdram_bankmachine6_cmd_buffer_lookahead_level = 4'd0; +reg main_sdram_bankmachine6_cmd_buffer_lookahead_replace = 1'd0; +reg [2:0] main_sdram_bankmachine6_cmd_buffer_lookahead_produce = 3'd0; +reg [2:0] main_sdram_bankmachine6_cmd_buffer_lookahead_consume = 3'd0; +reg [2:0] main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr = 3'd0; +wire [23:0] main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r; +wire main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we; +wire [23:0] main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; +wire main_sdram_bankmachine6_cmd_buffer_lookahead_do_read; +wire [2:0] main_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr; +wire [23:0] main_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +wire main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first; +wire main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last; +wire main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +wire main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +wire main_sdram_bankmachine6_cmd_buffer_sink_valid; +wire main_sdram_bankmachine6_cmd_buffer_sink_ready; +wire main_sdram_bankmachine6_cmd_buffer_sink_first; +wire main_sdram_bankmachine6_cmd_buffer_sink_last; +wire main_sdram_bankmachine6_cmd_buffer_sink_payload_we; +wire [20:0] main_sdram_bankmachine6_cmd_buffer_sink_payload_addr; +wire main_sdram_bankmachine6_cmd_buffer_source_valid; +wire main_sdram_bankmachine6_cmd_buffer_source_ready; +wire main_sdram_bankmachine6_cmd_buffer_source_first; +wire main_sdram_bankmachine6_cmd_buffer_source_last; +reg main_sdram_bankmachine6_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_sdram_bankmachine6_cmd_buffer_source_payload_addr = 21'd0; +wire main_sdram_bankmachine6_cmd_buffer_pipe_ce; +wire main_sdram_bankmachine6_cmd_buffer_busy; +reg main_sdram_bankmachine6_cmd_buffer_valid_n = 1'd0; +reg main_sdram_bankmachine6_cmd_buffer_first_n = 1'd0; +reg main_sdram_bankmachine6_cmd_buffer_last_n = 1'd0; +reg [13:0] main_sdram_bankmachine6_row = 14'd0; +reg main_sdram_bankmachine6_row_opened = 1'd0; +wire main_sdram_bankmachine6_row_hit; +reg main_sdram_bankmachine6_row_open = 1'd0; +reg main_sdram_bankmachine6_row_close = 1'd0; +reg main_sdram_bankmachine6_row_col_n_addr_sel = 1'd0; +wire main_sdram_bankmachine6_twtpcon_valid; +(* dont_touch = "true" *) reg main_sdram_bankmachine6_twtpcon_ready = 1'd1; +reg [2:0] main_sdram_bankmachine6_twtpcon_count = 3'd0; +wire main_sdram_bankmachine6_trccon_valid; +(* dont_touch = "true" *) reg main_sdram_bankmachine6_trccon_ready = 1'd1; +reg [1:0] main_sdram_bankmachine6_trccon_count = 2'd0; +wire main_sdram_bankmachine6_trascon_valid; +(* dont_touch = "true" *) reg main_sdram_bankmachine6_trascon_ready = 1'd1; +reg [1:0] main_sdram_bankmachine6_trascon_count = 2'd0; +wire main_sdram_bankmachine7_req_valid; +wire main_sdram_bankmachine7_req_ready; +wire main_sdram_bankmachine7_req_we; +wire [20:0] main_sdram_bankmachine7_req_addr; +wire main_sdram_bankmachine7_req_lock; +reg main_sdram_bankmachine7_req_wdata_ready = 1'd0; +reg main_sdram_bankmachine7_req_rdata_valid = 1'd0; +wire main_sdram_bankmachine7_refresh_req; +reg main_sdram_bankmachine7_refresh_gnt = 1'd0; +reg main_sdram_bankmachine7_cmd_valid = 1'd0; +reg main_sdram_bankmachine7_cmd_ready = 1'd0; +reg [13:0] main_sdram_bankmachine7_cmd_payload_a = 14'd0; +wire [2:0] main_sdram_bankmachine7_cmd_payload_ba; +reg main_sdram_bankmachine7_cmd_payload_cas = 1'd0; +reg main_sdram_bankmachine7_cmd_payload_ras = 1'd0; +reg main_sdram_bankmachine7_cmd_payload_we = 1'd0; +reg main_sdram_bankmachine7_cmd_payload_is_cmd = 1'd0; +reg main_sdram_bankmachine7_cmd_payload_is_read = 1'd0; +reg main_sdram_bankmachine7_cmd_payload_is_write = 1'd0; +reg main_sdram_bankmachine7_auto_precharge = 1'd0; +wire main_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid; +wire main_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready; +reg main_sdram_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0; +reg main_sdram_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0; +wire main_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +wire [20:0] main_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +wire main_sdram_bankmachine7_cmd_buffer_lookahead_source_valid; +wire main_sdram_bankmachine7_cmd_buffer_lookahead_source_ready; +wire main_sdram_bankmachine7_cmd_buffer_lookahead_source_first; +wire main_sdram_bankmachine7_cmd_buffer_lookahead_source_last; +wire main_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we; +wire [20:0] main_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +wire main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we; +wire main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +wire main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re; +wire main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +wire [23:0] main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +wire [23:0] main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +reg [3:0] main_sdram_bankmachine7_cmd_buffer_lookahead_level = 4'd0; +reg main_sdram_bankmachine7_cmd_buffer_lookahead_replace = 1'd0; +reg [2:0] main_sdram_bankmachine7_cmd_buffer_lookahead_produce = 3'd0; +reg [2:0] main_sdram_bankmachine7_cmd_buffer_lookahead_consume = 3'd0; +reg [2:0] main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr = 3'd0; +wire [23:0] main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r; +wire main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we; +wire [23:0] main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; +wire main_sdram_bankmachine7_cmd_buffer_lookahead_do_read; +wire [2:0] main_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr; +wire [23:0] main_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +wire main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we; +wire [20:0] main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr; +wire main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first; +wire main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last; +wire main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +wire [20:0] main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +wire main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +wire main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +wire main_sdram_bankmachine7_cmd_buffer_sink_valid; +wire main_sdram_bankmachine7_cmd_buffer_sink_ready; +wire main_sdram_bankmachine7_cmd_buffer_sink_first; +wire main_sdram_bankmachine7_cmd_buffer_sink_last; +wire main_sdram_bankmachine7_cmd_buffer_sink_payload_we; +wire [20:0] main_sdram_bankmachine7_cmd_buffer_sink_payload_addr; +wire main_sdram_bankmachine7_cmd_buffer_source_valid; +wire main_sdram_bankmachine7_cmd_buffer_source_ready; +wire main_sdram_bankmachine7_cmd_buffer_source_first; +wire main_sdram_bankmachine7_cmd_buffer_source_last; +reg main_sdram_bankmachine7_cmd_buffer_source_payload_we = 1'd0; +reg [20:0] main_sdram_bankmachine7_cmd_buffer_source_payload_addr = 21'd0; +wire main_sdram_bankmachine7_cmd_buffer_pipe_ce; +wire main_sdram_bankmachine7_cmd_buffer_busy; +reg main_sdram_bankmachine7_cmd_buffer_valid_n = 1'd0; +reg main_sdram_bankmachine7_cmd_buffer_first_n = 1'd0; +reg main_sdram_bankmachine7_cmd_buffer_last_n = 1'd0; +reg [13:0] main_sdram_bankmachine7_row = 14'd0; +reg main_sdram_bankmachine7_row_opened = 1'd0; +wire main_sdram_bankmachine7_row_hit; +reg main_sdram_bankmachine7_row_open = 1'd0; +reg main_sdram_bankmachine7_row_close = 1'd0; +reg main_sdram_bankmachine7_row_col_n_addr_sel = 1'd0; +wire main_sdram_bankmachine7_twtpcon_valid; +(* dont_touch = "true" *) reg main_sdram_bankmachine7_twtpcon_ready = 1'd1; +reg [2:0] main_sdram_bankmachine7_twtpcon_count = 3'd0; +wire main_sdram_bankmachine7_trccon_valid; +(* dont_touch = "true" *) reg main_sdram_bankmachine7_trccon_ready = 1'd1; +reg [1:0] main_sdram_bankmachine7_trccon_count = 2'd0; +wire main_sdram_bankmachine7_trascon_valid; +(* dont_touch = "true" *) reg main_sdram_bankmachine7_trascon_ready = 1'd1; +reg [1:0] main_sdram_bankmachine7_trascon_count = 2'd0; +wire main_sdram_ras_allowed; +wire main_sdram_cas_allowed; +reg main_sdram_choose_cmd_want_reads = 1'd0; +reg main_sdram_choose_cmd_want_writes = 1'd0; +reg main_sdram_choose_cmd_want_cmds = 1'd0; +reg main_sdram_choose_cmd_want_activates = 1'd0; +wire main_sdram_choose_cmd_cmd_valid; +reg main_sdram_choose_cmd_cmd_ready = 1'd0; +wire [13:0] main_sdram_choose_cmd_cmd_payload_a; +wire [2:0] main_sdram_choose_cmd_cmd_payload_ba; +reg main_sdram_choose_cmd_cmd_payload_cas = 1'd0; +reg main_sdram_choose_cmd_cmd_payload_ras = 1'd0; +reg main_sdram_choose_cmd_cmd_payload_we = 1'd0; +wire main_sdram_choose_cmd_cmd_payload_is_cmd; +wire main_sdram_choose_cmd_cmd_payload_is_read; +wire main_sdram_choose_cmd_cmd_payload_is_write; +reg [7:0] main_sdram_choose_cmd_valids = 8'd0; +wire [7:0] main_sdram_choose_cmd_request; +reg [2:0] main_sdram_choose_cmd_grant = 3'd0; +wire main_sdram_choose_cmd_ce; +reg main_sdram_choose_req_want_reads = 1'd0; +reg main_sdram_choose_req_want_writes = 1'd0; +reg main_sdram_choose_req_want_cmds = 1'd0; +reg main_sdram_choose_req_want_activates = 1'd0; +wire main_sdram_choose_req_cmd_valid; +reg main_sdram_choose_req_cmd_ready = 1'd0; +wire [13:0] main_sdram_choose_req_cmd_payload_a; +wire [2:0] main_sdram_choose_req_cmd_payload_ba; +reg main_sdram_choose_req_cmd_payload_cas = 1'd0; +reg main_sdram_choose_req_cmd_payload_ras = 1'd0; +reg main_sdram_choose_req_cmd_payload_we = 1'd0; +wire main_sdram_choose_req_cmd_payload_is_cmd; +wire main_sdram_choose_req_cmd_payload_is_read; +wire main_sdram_choose_req_cmd_payload_is_write; +reg [7:0] main_sdram_choose_req_valids = 8'd0; +wire [7:0] main_sdram_choose_req_request; +reg [2:0] main_sdram_choose_req_grant = 3'd0; +wire main_sdram_choose_req_ce; +reg [13:0] main_sdram_nop_a = 14'd0; +reg [2:0] main_sdram_nop_ba = 3'd0; +reg [1:0] main_sdram_steerer_sel0 = 2'd0; +reg [1:0] main_sdram_steerer_sel1 = 2'd0; +reg [1:0] main_sdram_steerer_sel2 = 2'd0; +reg [1:0] main_sdram_steerer_sel3 = 2'd0; +reg main_sdram_steerer0 = 1'd1; +reg main_sdram_steerer1 = 1'd1; +reg main_sdram_steerer2 = 1'd1; +reg main_sdram_steerer3 = 1'd1; +reg main_sdram_steerer4 = 1'd1; +reg main_sdram_steerer5 = 1'd1; +reg main_sdram_steerer6 = 1'd1; +reg main_sdram_steerer7 = 1'd1; +wire main_sdram_trrdcon_valid; +(* dont_touch = "true" *) reg main_sdram_trrdcon_ready = 1'd1; +reg main_sdram_trrdcon_count = 1'd0; +wire main_sdram_tfawcon_valid; +(* dont_touch = "true" *) reg main_sdram_tfawcon_ready = 1'd1; +wire [1:0] main_sdram_tfawcon_count; +reg [2:0] main_sdram_tfawcon_window = 3'd0; +wire main_sdram_tccdcon_valid; +(* dont_touch = "true" *) reg main_sdram_tccdcon_ready = 1'd1; +reg main_sdram_tccdcon_count = 1'd0; +wire main_sdram_twtrcon_valid; +(* dont_touch = "true" *) reg main_sdram_twtrcon_ready = 1'd1; +reg [2:0] main_sdram_twtrcon_count = 3'd0; +wire main_sdram_read_available; +wire main_sdram_write_available; +reg main_sdram_en0 = 1'd0; +wire main_sdram_max_time0; +reg [4:0] main_sdram_time0 = 5'd0; +reg main_sdram_en1 = 1'd0; +wire main_sdram_max_time1; +reg [3:0] main_sdram_time1 = 4'd0; +wire main_sdram_go_to_refresh; +reg main_port_cmd_valid = 1'd0; +wire main_port_cmd_ready; +reg main_port_cmd_payload_we = 1'd0; +wire [23:0] main_port_cmd_payload_addr; +reg main_port_wdata_valid = 1'd0; +wire main_port_wdata_ready; +wire [127:0] main_port_wdata_payload_data; +wire [15:0] main_port_wdata_payload_we; +wire main_port_rdata_valid; +reg main_port_rdata_ready = 1'd0; +wire [127:0] main_port_rdata_payload_data; +wire [29:0] main_interface1_wb_sdram_adr; +wire [31:0] main_interface1_wb_sdram_dat_w; +wire [31:0] main_interface1_wb_sdram_dat_r; +wire [3:0] main_interface1_wb_sdram_sel; +wire main_interface1_wb_sdram_cyc; +wire main_interface1_wb_sdram_stb; +wire main_interface1_wb_sdram_ack; +wire main_interface1_wb_sdram_we; +wire [2:0] main_interface1_wb_sdram_cti; +wire [1:0] main_interface1_wb_sdram_bte; +wire main_interface1_wb_sdram_err; +wire [29:0] main_adr; +wire [127:0] main_dat_w; +wire [127:0] main_dat_r; +wire [15:0] main_sel; +reg main_cyc = 1'd0; +reg main_stb = 1'd0; +reg main_ack = 1'd0; +reg main_we = 1'd0; +wire [8:0] main_data_port_adr; +wire [127:0] main_data_port_dat_r; +reg [15:0] main_data_port_we = 16'd0; +reg [127:0] main_data_port_dat_w = 128'd0; +reg main_write_from_slave = 1'd0; +reg [1:0] main_adr_offset_r = 2'd0; +wire [8:0] main_tag_port_adr; +wire [23:0] main_tag_port_dat_r; +reg main_tag_port_we = 1'd0; +wire [23:0] main_tag_port_dat_w; +wire [22:0] main_tag_do_tag; +wire main_tag_do_dirty; +wire [22:0] main_tag_di_tag; +reg main_tag_di_dirty = 1'd0; +reg main_word_clr = 1'd0; +reg main_word_inc = 1'd0; +reg builder_wb2csr_state = 1'd0; +reg builder_wb2csr_next_state = 1'd0; +wire builder_pll_fb; +reg [1:0] builder_refresher_state = 2'd0; +reg [1:0] builder_refresher_next_state = 2'd0; +reg [2:0] builder_bankmachine0_state = 3'd0; +reg [2:0] builder_bankmachine0_next_state = 3'd0; +reg [2:0] builder_bankmachine1_state = 3'd0; +reg [2:0] builder_bankmachine1_next_state = 3'd0; +reg [2:0] builder_bankmachine2_state = 3'd0; +reg [2:0] builder_bankmachine2_next_state = 3'd0; +reg [2:0] builder_bankmachine3_state = 3'd0; +reg [2:0] builder_bankmachine3_next_state = 3'd0; +reg [2:0] builder_bankmachine4_state = 3'd0; +reg [2:0] builder_bankmachine4_next_state = 3'd0; +reg [2:0] builder_bankmachine5_state = 3'd0; +reg [2:0] builder_bankmachine5_next_state = 3'd0; +reg [2:0] builder_bankmachine6_state = 3'd0; +reg [2:0] builder_bankmachine6_next_state = 3'd0; +reg [2:0] builder_bankmachine7_state = 3'd0; +reg [2:0] builder_bankmachine7_next_state = 3'd0; +reg [3:0] builder_multiplexer_state = 4'd0; +reg [3:0] builder_multiplexer_next_state = 4'd0; +wire builder_roundrobin0_request; +wire builder_roundrobin0_grant; +wire builder_roundrobin0_ce; +wire builder_roundrobin1_request; +wire builder_roundrobin1_grant; +wire builder_roundrobin1_ce; +wire builder_roundrobin2_request; +wire builder_roundrobin2_grant; +wire builder_roundrobin2_ce; +wire builder_roundrobin3_request; +wire builder_roundrobin3_grant; +wire builder_roundrobin3_ce; +wire builder_roundrobin4_request; +wire builder_roundrobin4_grant; +wire builder_roundrobin4_ce; +wire builder_roundrobin5_request; +wire builder_roundrobin5_grant; +wire builder_roundrobin5_ce; +wire builder_roundrobin6_request; +wire builder_roundrobin6_grant; +wire builder_roundrobin6_ce; +wire builder_roundrobin7_request; +wire builder_roundrobin7_grant; +wire builder_roundrobin7_ce; +reg [2:0] builder_rbank = 3'd0; +reg [2:0] builder_wbank = 3'd0; +reg builder_locked0 = 1'd0; +reg builder_locked1 = 1'd0; +reg builder_locked2 = 1'd0; +reg builder_locked3 = 1'd0; +reg builder_locked4 = 1'd0; +reg builder_locked5 = 1'd0; +reg builder_locked6 = 1'd0; +reg builder_locked7 = 1'd0; +reg builder_new_master_wdata_ready0 = 1'd0; +reg builder_new_master_wdata_ready1 = 1'd0; +reg builder_new_master_wdata_ready2 = 1'd0; +reg builder_new_master_rdata_valid0 = 1'd0; +reg builder_new_master_rdata_valid1 = 1'd0; +reg builder_new_master_rdata_valid2 = 1'd0; +reg builder_new_master_rdata_valid3 = 1'd0; +reg builder_new_master_rdata_valid4 = 1'd0; +reg builder_new_master_rdata_valid5 = 1'd0; +reg builder_new_master_rdata_valid6 = 1'd0; +reg builder_new_master_rdata_valid7 = 1'd0; +reg builder_new_master_rdata_valid8 = 1'd0; +reg builder_new_master_rdata_valid9 = 1'd0; +reg [2:0] builder_fullmemorywe_state = 3'd0; +reg [2:0] builder_fullmemorywe_next_state = 3'd0; +reg [1:0] builder_litedramwishbone2native_state = 2'd0; +reg [1:0] builder_litedramwishbone2native_next_state = 2'd0; +wire builder_wb_sdram_con_request; +wire builder_wb_sdram_con_grant; +wire [29:0] builder_minsoc_shared_adr; +wire [31:0] builder_minsoc_shared_dat_w; +reg [31:0] builder_minsoc_shared_dat_r = 32'd0; +wire [3:0] builder_minsoc_shared_sel; +wire builder_minsoc_shared_cyc; +wire builder_minsoc_shared_stb; +reg builder_minsoc_shared_ack = 1'd0; +wire builder_minsoc_shared_we; +wire [2:0] builder_minsoc_shared_cti; +wire [1:0] builder_minsoc_shared_bte; +wire builder_minsoc_shared_err; +wire [1:0] builder_minsoc_request; +reg builder_minsoc_grant = 1'd0; +reg [3:0] builder_minsoc_slave_sel = 4'd0; +reg [3:0] builder_minsoc_slave_sel_r = 4'd0; +reg builder_minsoc_error = 1'd0; +wire builder_minsoc_wait; +wire builder_minsoc_done; +reg [19:0] builder_minsoc_count = 20'd1000000; +wire [13:0] builder_minsoc_interface0_bank_bus_adr; +wire builder_minsoc_interface0_bank_bus_we; +wire [7:0] builder_minsoc_interface0_bank_bus_dat_w; +reg [7:0] builder_minsoc_interface0_bank_bus_dat_r = 8'd0; +wire builder_minsoc_csrbank0_scratch3_re; +wire [7:0] builder_minsoc_csrbank0_scratch3_r; +wire builder_minsoc_csrbank0_scratch3_we; +wire [7:0] builder_minsoc_csrbank0_scratch3_w; +wire builder_minsoc_csrbank0_scratch2_re; +wire [7:0] builder_minsoc_csrbank0_scratch2_r; +wire builder_minsoc_csrbank0_scratch2_we; +wire [7:0] builder_minsoc_csrbank0_scratch2_w; +wire builder_minsoc_csrbank0_scratch1_re; +wire [7:0] builder_minsoc_csrbank0_scratch1_r; +wire builder_minsoc_csrbank0_scratch1_we; +wire [7:0] builder_minsoc_csrbank0_scratch1_w; +wire builder_minsoc_csrbank0_scratch0_re; +wire [7:0] builder_minsoc_csrbank0_scratch0_r; +wire builder_minsoc_csrbank0_scratch0_we; +wire [7:0] builder_minsoc_csrbank0_scratch0_w; +wire builder_minsoc_csrbank0_bus_errors3_re; +wire [7:0] builder_minsoc_csrbank0_bus_errors3_r; +wire builder_minsoc_csrbank0_bus_errors3_we; +wire [7:0] builder_minsoc_csrbank0_bus_errors3_w; +wire builder_minsoc_csrbank0_bus_errors2_re; +wire [7:0] builder_minsoc_csrbank0_bus_errors2_r; +wire builder_minsoc_csrbank0_bus_errors2_we; +wire [7:0] builder_minsoc_csrbank0_bus_errors2_w; +wire builder_minsoc_csrbank0_bus_errors1_re; +wire [7:0] builder_minsoc_csrbank0_bus_errors1_r; +wire builder_minsoc_csrbank0_bus_errors1_we; +wire [7:0] builder_minsoc_csrbank0_bus_errors1_w; +wire builder_minsoc_csrbank0_bus_errors0_re; +wire [7:0] builder_minsoc_csrbank0_bus_errors0_r; +wire builder_minsoc_csrbank0_bus_errors0_we; +wire [7:0] builder_minsoc_csrbank0_bus_errors0_w; +wire builder_minsoc_csrbank0_sel; +wire [13:0] builder_minsoc_interface1_bank_bus_adr; +wire builder_minsoc_interface1_bank_bus_we; +wire [7:0] builder_minsoc_interface1_bank_bus_dat_w; +reg [7:0] builder_minsoc_interface1_bank_bus_dat_r = 8'd0; +wire builder_minsoc_csrbank1_half_sys8x_taps0_re; +wire [4:0] builder_minsoc_csrbank1_half_sys8x_taps0_r; +wire builder_minsoc_csrbank1_half_sys8x_taps0_we; +wire [4:0] builder_minsoc_csrbank1_half_sys8x_taps0_w; +wire builder_minsoc_csrbank1_dly_sel0_re; +wire [1:0] builder_minsoc_csrbank1_dly_sel0_r; +wire builder_minsoc_csrbank1_dly_sel0_we; +wire [1:0] builder_minsoc_csrbank1_dly_sel0_w; +wire builder_minsoc_csrbank1_sel; +wire [13:0] builder_minsoc_interface2_bank_bus_adr; +wire builder_minsoc_interface2_bank_bus_we; +wire [7:0] builder_minsoc_interface2_bank_bus_dat_w; +reg [7:0] builder_minsoc_interface2_bank_bus_dat_r = 8'd0; +wire builder_minsoc_csrbank2_dfii_control0_re; +wire [3:0] builder_minsoc_csrbank2_dfii_control0_r; +wire builder_minsoc_csrbank2_dfii_control0_we; +wire [3:0] builder_minsoc_csrbank2_dfii_control0_w; +wire builder_minsoc_csrbank2_dfii_pi0_command0_re; +wire [5:0] builder_minsoc_csrbank2_dfii_pi0_command0_r; +wire builder_minsoc_csrbank2_dfii_pi0_command0_we; +wire [5:0] builder_minsoc_csrbank2_dfii_pi0_command0_w; +wire builder_minsoc_csrbank2_dfii_pi0_address1_re; +wire [5:0] builder_minsoc_csrbank2_dfii_pi0_address1_r; +wire builder_minsoc_csrbank2_dfii_pi0_address1_we; +wire [5:0] builder_minsoc_csrbank2_dfii_pi0_address1_w; +wire builder_minsoc_csrbank2_dfii_pi0_address0_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi0_address0_r; +wire builder_minsoc_csrbank2_dfii_pi0_address0_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi0_address0_w; +wire builder_minsoc_csrbank2_dfii_pi0_baddress0_re; +wire [2:0] builder_minsoc_csrbank2_dfii_pi0_baddress0_r; +wire builder_minsoc_csrbank2_dfii_pi0_baddress0_we; +wire [2:0] builder_minsoc_csrbank2_dfii_pi0_baddress0_w; +wire builder_minsoc_csrbank2_dfii_pi0_wrdata3_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi0_wrdata3_r; +wire builder_minsoc_csrbank2_dfii_pi0_wrdata3_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi0_wrdata3_w; +wire builder_minsoc_csrbank2_dfii_pi0_wrdata2_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi0_wrdata2_r; +wire builder_minsoc_csrbank2_dfii_pi0_wrdata2_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi0_wrdata2_w; +wire builder_minsoc_csrbank2_dfii_pi0_wrdata1_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi0_wrdata1_r; +wire builder_minsoc_csrbank2_dfii_pi0_wrdata1_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi0_wrdata1_w; +wire builder_minsoc_csrbank2_dfii_pi0_wrdata0_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi0_wrdata0_r; +wire builder_minsoc_csrbank2_dfii_pi0_wrdata0_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi0_wrdata0_w; +wire builder_minsoc_csrbank2_dfii_pi0_rddata3_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi0_rddata3_r; +wire builder_minsoc_csrbank2_dfii_pi0_rddata3_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi0_rddata3_w; +wire builder_minsoc_csrbank2_dfii_pi0_rddata2_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi0_rddata2_r; +wire builder_minsoc_csrbank2_dfii_pi0_rddata2_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi0_rddata2_w; +wire builder_minsoc_csrbank2_dfii_pi0_rddata1_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi0_rddata1_r; +wire builder_minsoc_csrbank2_dfii_pi0_rddata1_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi0_rddata1_w; +wire builder_minsoc_csrbank2_dfii_pi0_rddata0_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi0_rddata0_r; +wire builder_minsoc_csrbank2_dfii_pi0_rddata0_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi0_rddata0_w; +wire builder_minsoc_csrbank2_dfii_pi1_command0_re; +wire [5:0] builder_minsoc_csrbank2_dfii_pi1_command0_r; +wire builder_minsoc_csrbank2_dfii_pi1_command0_we; +wire [5:0] builder_minsoc_csrbank2_dfii_pi1_command0_w; +wire builder_minsoc_csrbank2_dfii_pi1_address1_re; +wire [5:0] builder_minsoc_csrbank2_dfii_pi1_address1_r; +wire builder_minsoc_csrbank2_dfii_pi1_address1_we; +wire [5:0] builder_minsoc_csrbank2_dfii_pi1_address1_w; +wire builder_minsoc_csrbank2_dfii_pi1_address0_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi1_address0_r; +wire builder_minsoc_csrbank2_dfii_pi1_address0_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi1_address0_w; +wire builder_minsoc_csrbank2_dfii_pi1_baddress0_re; +wire [2:0] builder_minsoc_csrbank2_dfii_pi1_baddress0_r; +wire builder_minsoc_csrbank2_dfii_pi1_baddress0_we; +wire [2:0] builder_minsoc_csrbank2_dfii_pi1_baddress0_w; +wire builder_minsoc_csrbank2_dfii_pi1_wrdata3_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi1_wrdata3_r; +wire builder_minsoc_csrbank2_dfii_pi1_wrdata3_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi1_wrdata3_w; +wire builder_minsoc_csrbank2_dfii_pi1_wrdata2_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi1_wrdata2_r; +wire builder_minsoc_csrbank2_dfii_pi1_wrdata2_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi1_wrdata2_w; +wire builder_minsoc_csrbank2_dfii_pi1_wrdata1_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi1_wrdata1_r; +wire builder_minsoc_csrbank2_dfii_pi1_wrdata1_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi1_wrdata1_w; +wire builder_minsoc_csrbank2_dfii_pi1_wrdata0_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi1_wrdata0_r; +wire builder_minsoc_csrbank2_dfii_pi1_wrdata0_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi1_wrdata0_w; +wire builder_minsoc_csrbank2_dfii_pi1_rddata3_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi1_rddata3_r; +wire builder_minsoc_csrbank2_dfii_pi1_rddata3_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi1_rddata3_w; +wire builder_minsoc_csrbank2_dfii_pi1_rddata2_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi1_rddata2_r; +wire builder_minsoc_csrbank2_dfii_pi1_rddata2_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi1_rddata2_w; +wire builder_minsoc_csrbank2_dfii_pi1_rddata1_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi1_rddata1_r; +wire builder_minsoc_csrbank2_dfii_pi1_rddata1_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi1_rddata1_w; +wire builder_minsoc_csrbank2_dfii_pi1_rddata0_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi1_rddata0_r; +wire builder_minsoc_csrbank2_dfii_pi1_rddata0_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi1_rddata0_w; +wire builder_minsoc_csrbank2_dfii_pi2_command0_re; +wire [5:0] builder_minsoc_csrbank2_dfii_pi2_command0_r; +wire builder_minsoc_csrbank2_dfii_pi2_command0_we; +wire [5:0] builder_minsoc_csrbank2_dfii_pi2_command0_w; +wire builder_minsoc_csrbank2_dfii_pi2_address1_re; +wire [5:0] builder_minsoc_csrbank2_dfii_pi2_address1_r; +wire builder_minsoc_csrbank2_dfii_pi2_address1_we; +wire [5:0] builder_minsoc_csrbank2_dfii_pi2_address1_w; +wire builder_minsoc_csrbank2_dfii_pi2_address0_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi2_address0_r; +wire builder_minsoc_csrbank2_dfii_pi2_address0_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi2_address0_w; +wire builder_minsoc_csrbank2_dfii_pi2_baddress0_re; +wire [2:0] builder_minsoc_csrbank2_dfii_pi2_baddress0_r; +wire builder_minsoc_csrbank2_dfii_pi2_baddress0_we; +wire [2:0] builder_minsoc_csrbank2_dfii_pi2_baddress0_w; +wire builder_minsoc_csrbank2_dfii_pi2_wrdata3_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi2_wrdata3_r; +wire builder_minsoc_csrbank2_dfii_pi2_wrdata3_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi2_wrdata3_w; +wire builder_minsoc_csrbank2_dfii_pi2_wrdata2_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi2_wrdata2_r; +wire builder_minsoc_csrbank2_dfii_pi2_wrdata2_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi2_wrdata2_w; +wire builder_minsoc_csrbank2_dfii_pi2_wrdata1_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi2_wrdata1_r; +wire builder_minsoc_csrbank2_dfii_pi2_wrdata1_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi2_wrdata1_w; +wire builder_minsoc_csrbank2_dfii_pi2_wrdata0_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi2_wrdata0_r; +wire builder_minsoc_csrbank2_dfii_pi2_wrdata0_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi2_wrdata0_w; +wire builder_minsoc_csrbank2_dfii_pi2_rddata3_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi2_rddata3_r; +wire builder_minsoc_csrbank2_dfii_pi2_rddata3_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi2_rddata3_w; +wire builder_minsoc_csrbank2_dfii_pi2_rddata2_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi2_rddata2_r; +wire builder_minsoc_csrbank2_dfii_pi2_rddata2_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi2_rddata2_w; +wire builder_minsoc_csrbank2_dfii_pi2_rddata1_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi2_rddata1_r; +wire builder_minsoc_csrbank2_dfii_pi2_rddata1_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi2_rddata1_w; +wire builder_minsoc_csrbank2_dfii_pi2_rddata0_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi2_rddata0_r; +wire builder_minsoc_csrbank2_dfii_pi2_rddata0_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi2_rddata0_w; +wire builder_minsoc_csrbank2_dfii_pi3_command0_re; +wire [5:0] builder_minsoc_csrbank2_dfii_pi3_command0_r; +wire builder_minsoc_csrbank2_dfii_pi3_command0_we; +wire [5:0] builder_minsoc_csrbank2_dfii_pi3_command0_w; +wire builder_minsoc_csrbank2_dfii_pi3_address1_re; +wire [5:0] builder_minsoc_csrbank2_dfii_pi3_address1_r; +wire builder_minsoc_csrbank2_dfii_pi3_address1_we; +wire [5:0] builder_minsoc_csrbank2_dfii_pi3_address1_w; +wire builder_minsoc_csrbank2_dfii_pi3_address0_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi3_address0_r; +wire builder_minsoc_csrbank2_dfii_pi3_address0_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi3_address0_w; +wire builder_minsoc_csrbank2_dfii_pi3_baddress0_re; +wire [2:0] builder_minsoc_csrbank2_dfii_pi3_baddress0_r; +wire builder_minsoc_csrbank2_dfii_pi3_baddress0_we; +wire [2:0] builder_minsoc_csrbank2_dfii_pi3_baddress0_w; +wire builder_minsoc_csrbank2_dfii_pi3_wrdata3_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi3_wrdata3_r; +wire builder_minsoc_csrbank2_dfii_pi3_wrdata3_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi3_wrdata3_w; +wire builder_minsoc_csrbank2_dfii_pi3_wrdata2_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi3_wrdata2_r; +wire builder_minsoc_csrbank2_dfii_pi3_wrdata2_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi3_wrdata2_w; +wire builder_minsoc_csrbank2_dfii_pi3_wrdata1_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi3_wrdata1_r; +wire builder_minsoc_csrbank2_dfii_pi3_wrdata1_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi3_wrdata1_w; +wire builder_minsoc_csrbank2_dfii_pi3_wrdata0_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi3_wrdata0_r; +wire builder_minsoc_csrbank2_dfii_pi3_wrdata0_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi3_wrdata0_w; +wire builder_minsoc_csrbank2_dfii_pi3_rddata3_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi3_rddata3_r; +wire builder_minsoc_csrbank2_dfii_pi3_rddata3_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi3_rddata3_w; +wire builder_minsoc_csrbank2_dfii_pi3_rddata2_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi3_rddata2_r; +wire builder_minsoc_csrbank2_dfii_pi3_rddata2_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi3_rddata2_w; +wire builder_minsoc_csrbank2_dfii_pi3_rddata1_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi3_rddata1_r; +wire builder_minsoc_csrbank2_dfii_pi3_rddata1_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi3_rddata1_w; +wire builder_minsoc_csrbank2_dfii_pi3_rddata0_re; +wire [7:0] builder_minsoc_csrbank2_dfii_pi3_rddata0_r; +wire builder_minsoc_csrbank2_dfii_pi3_rddata0_we; +wire [7:0] builder_minsoc_csrbank2_dfii_pi3_rddata0_w; +wire builder_minsoc_csrbank2_sel; +wire [13:0] builder_minsoc_interface3_bank_bus_adr; +wire builder_minsoc_interface3_bank_bus_we; +wire [7:0] builder_minsoc_interface3_bank_bus_dat_w; +reg [7:0] builder_minsoc_interface3_bank_bus_dat_r = 8'd0; +wire builder_minsoc_csrbank3_load3_re; +wire [7:0] builder_minsoc_csrbank3_load3_r; +wire builder_minsoc_csrbank3_load3_we; +wire [7:0] builder_minsoc_csrbank3_load3_w; +wire builder_minsoc_csrbank3_load2_re; +wire [7:0] builder_minsoc_csrbank3_load2_r; +wire builder_minsoc_csrbank3_load2_we; +wire [7:0] builder_minsoc_csrbank3_load2_w; +wire builder_minsoc_csrbank3_load1_re; +wire [7:0] builder_minsoc_csrbank3_load1_r; +wire builder_minsoc_csrbank3_load1_we; +wire [7:0] builder_minsoc_csrbank3_load1_w; +wire builder_minsoc_csrbank3_load0_re; +wire [7:0] builder_minsoc_csrbank3_load0_r; +wire builder_minsoc_csrbank3_load0_we; +wire [7:0] builder_minsoc_csrbank3_load0_w; +wire builder_minsoc_csrbank3_reload3_re; +wire [7:0] builder_minsoc_csrbank3_reload3_r; +wire builder_minsoc_csrbank3_reload3_we; +wire [7:0] builder_minsoc_csrbank3_reload3_w; +wire builder_minsoc_csrbank3_reload2_re; +wire [7:0] builder_minsoc_csrbank3_reload2_r; +wire builder_minsoc_csrbank3_reload2_we; +wire [7:0] builder_minsoc_csrbank3_reload2_w; +wire builder_minsoc_csrbank3_reload1_re; +wire [7:0] builder_minsoc_csrbank3_reload1_r; +wire builder_minsoc_csrbank3_reload1_we; +wire [7:0] builder_minsoc_csrbank3_reload1_w; +wire builder_minsoc_csrbank3_reload0_re; +wire [7:0] builder_minsoc_csrbank3_reload0_r; +wire builder_minsoc_csrbank3_reload0_we; +wire [7:0] builder_minsoc_csrbank3_reload0_w; +wire builder_minsoc_csrbank3_en0_re; +wire builder_minsoc_csrbank3_en0_r; +wire builder_minsoc_csrbank3_en0_we; +wire builder_minsoc_csrbank3_en0_w; +wire builder_minsoc_csrbank3_update_value0_re; +wire builder_minsoc_csrbank3_update_value0_r; +wire builder_minsoc_csrbank3_update_value0_we; +wire builder_minsoc_csrbank3_update_value0_w; +wire builder_minsoc_csrbank3_value3_re; +wire [7:0] builder_minsoc_csrbank3_value3_r; +wire builder_minsoc_csrbank3_value3_we; +wire [7:0] builder_minsoc_csrbank3_value3_w; +wire builder_minsoc_csrbank3_value2_re; +wire [7:0] builder_minsoc_csrbank3_value2_r; +wire builder_minsoc_csrbank3_value2_we; +wire [7:0] builder_minsoc_csrbank3_value2_w; +wire builder_minsoc_csrbank3_value1_re; +wire [7:0] builder_minsoc_csrbank3_value1_r; +wire builder_minsoc_csrbank3_value1_we; +wire [7:0] builder_minsoc_csrbank3_value1_w; +wire builder_minsoc_csrbank3_value0_re; +wire [7:0] builder_minsoc_csrbank3_value0_r; +wire builder_minsoc_csrbank3_value0_we; +wire [7:0] builder_minsoc_csrbank3_value0_w; +wire builder_minsoc_csrbank3_ev_enable0_re; +wire builder_minsoc_csrbank3_ev_enable0_r; +wire builder_minsoc_csrbank3_ev_enable0_we; +wire builder_minsoc_csrbank3_ev_enable0_w; +wire builder_minsoc_csrbank3_sel; +wire [13:0] builder_minsoc_interface4_bank_bus_adr; +wire builder_minsoc_interface4_bank_bus_we; +wire [7:0] builder_minsoc_interface4_bank_bus_dat_w; +reg [7:0] builder_minsoc_interface4_bank_bus_dat_r = 8'd0; +wire builder_minsoc_csrbank4_txfull_re; +wire builder_minsoc_csrbank4_txfull_r; +wire builder_minsoc_csrbank4_txfull_we; +wire builder_minsoc_csrbank4_txfull_w; +wire builder_minsoc_csrbank4_rxempty_re; +wire builder_minsoc_csrbank4_rxempty_r; +wire builder_minsoc_csrbank4_rxempty_we; +wire builder_minsoc_csrbank4_rxempty_w; +wire builder_minsoc_csrbank4_ev_enable0_re; +wire [1:0] builder_minsoc_csrbank4_ev_enable0_r; +wire builder_minsoc_csrbank4_ev_enable0_we; +wire [1:0] builder_minsoc_csrbank4_ev_enable0_w; +wire builder_minsoc_csrbank4_sel; +wire [13:0] builder_minsoc_interface5_bank_bus_adr; +wire builder_minsoc_interface5_bank_bus_we; +wire [7:0] builder_minsoc_interface5_bank_bus_dat_w; +reg [7:0] builder_minsoc_interface5_bank_bus_dat_r = 8'd0; +wire builder_minsoc_csrbank5_tuning_word3_re; +wire [7:0] builder_minsoc_csrbank5_tuning_word3_r; +wire builder_minsoc_csrbank5_tuning_word3_we; +wire [7:0] builder_minsoc_csrbank5_tuning_word3_w; +wire builder_minsoc_csrbank5_tuning_word2_re; +wire [7:0] builder_minsoc_csrbank5_tuning_word2_r; +wire builder_minsoc_csrbank5_tuning_word2_we; +wire [7:0] builder_minsoc_csrbank5_tuning_word2_w; +wire builder_minsoc_csrbank5_tuning_word1_re; +wire [7:0] builder_minsoc_csrbank5_tuning_word1_r; +wire builder_minsoc_csrbank5_tuning_word1_we; +wire [7:0] builder_minsoc_csrbank5_tuning_word1_w; +wire builder_minsoc_csrbank5_tuning_word0_re; +wire [7:0] builder_minsoc_csrbank5_tuning_word0_r; +wire builder_minsoc_csrbank5_tuning_word0_we; +wire [7:0] builder_minsoc_csrbank5_tuning_word0_w; +wire builder_minsoc_csrbank5_sel; +wire [13:0] builder_minsoc_adr; +wire builder_minsoc_we; +wire [7:0] builder_minsoc_dat_w; +wire [7:0] builder_minsoc_dat_r; +reg builder_rhs_array_muxed0 = 1'd0; +reg [13:0] builder_rhs_array_muxed1 = 14'd0; +reg [2:0] builder_rhs_array_muxed2 = 3'd0; +reg builder_rhs_array_muxed3 = 1'd0; +reg builder_rhs_array_muxed4 = 1'd0; +reg builder_rhs_array_muxed5 = 1'd0; +reg builder_t_array_muxed0 = 1'd0; +reg builder_t_array_muxed1 = 1'd0; +reg builder_t_array_muxed2 = 1'd0; +reg builder_rhs_array_muxed6 = 1'd0; +reg [13:0] builder_rhs_array_muxed7 = 14'd0; +reg [2:0] builder_rhs_array_muxed8 = 3'd0; +reg builder_rhs_array_muxed9 = 1'd0; +reg builder_rhs_array_muxed10 = 1'd0; +reg builder_rhs_array_muxed11 = 1'd0; +reg builder_t_array_muxed3 = 1'd0; +reg builder_t_array_muxed4 = 1'd0; +reg builder_t_array_muxed5 = 1'd0; +reg [20:0] builder_rhs_array_muxed12 = 21'd0; +reg builder_rhs_array_muxed13 = 1'd0; +reg builder_rhs_array_muxed14 = 1'd0; +reg [20:0] builder_rhs_array_muxed15 = 21'd0; +reg builder_rhs_array_muxed16 = 1'd0; +reg builder_rhs_array_muxed17 = 1'd0; +reg [20:0] builder_rhs_array_muxed18 = 21'd0; +reg builder_rhs_array_muxed19 = 1'd0; +reg builder_rhs_array_muxed20 = 1'd0; +reg [20:0] builder_rhs_array_muxed21 = 21'd0; +reg builder_rhs_array_muxed22 = 1'd0; +reg builder_rhs_array_muxed23 = 1'd0; +reg [20:0] builder_rhs_array_muxed24 = 21'd0; +reg builder_rhs_array_muxed25 = 1'd0; +reg builder_rhs_array_muxed26 = 1'd0; +reg [20:0] builder_rhs_array_muxed27 = 21'd0; +reg builder_rhs_array_muxed28 = 1'd0; +reg builder_rhs_array_muxed29 = 1'd0; +reg [20:0] builder_rhs_array_muxed30 = 21'd0; +reg builder_rhs_array_muxed31 = 1'd0; +reg builder_rhs_array_muxed32 = 1'd0; +reg [20:0] builder_rhs_array_muxed33 = 21'd0; +reg builder_rhs_array_muxed34 = 1'd0; +reg builder_rhs_array_muxed35 = 1'd0; +reg [29:0] builder_rhs_array_muxed36 = 30'd0; +reg [31:0] builder_rhs_array_muxed37 = 32'd0; +reg [3:0] builder_rhs_array_muxed38 = 4'd0; +reg builder_rhs_array_muxed39 = 1'd0; +reg builder_rhs_array_muxed40 = 1'd0; +reg builder_rhs_array_muxed41 = 1'd0; +reg [2:0] builder_rhs_array_muxed42 = 3'd0; +reg [1:0] builder_rhs_array_muxed43 = 2'd0; +reg [29:0] builder_rhs_array_muxed44 = 30'd0; +reg [31:0] builder_rhs_array_muxed45 = 32'd0; +reg [3:0] builder_rhs_array_muxed46 = 4'd0; +reg builder_rhs_array_muxed47 = 1'd0; +reg builder_rhs_array_muxed48 = 1'd0; +reg builder_rhs_array_muxed49 = 1'd0; +reg [2:0] builder_rhs_array_muxed50 = 3'd0; +reg [1:0] builder_rhs_array_muxed51 = 2'd0; +reg [2:0] builder_array_muxed0 = 3'd0; +reg [13:0] builder_array_muxed1 = 14'd0; +reg builder_array_muxed2 = 1'd0; +reg builder_array_muxed3 = 1'd0; +reg builder_array_muxed4 = 1'd0; +reg builder_array_muxed5 = 1'd0; +reg builder_array_muxed6 = 1'd0; +reg [2:0] builder_array_muxed7 = 3'd0; +reg [13:0] builder_array_muxed8 = 14'd0; +reg builder_array_muxed9 = 1'd0; +reg builder_array_muxed10 = 1'd0; +reg builder_array_muxed11 = 1'd0; +reg builder_array_muxed12 = 1'd0; +reg builder_array_muxed13 = 1'd0; +reg [2:0] builder_array_muxed14 = 3'd0; +reg [13:0] builder_array_muxed15 = 14'd0; +reg builder_array_muxed16 = 1'd0; +reg builder_array_muxed17 = 1'd0; +reg builder_array_muxed18 = 1'd0; +reg builder_array_muxed19 = 1'd0; +reg builder_array_muxed20 = 1'd0; +reg [2:0] builder_array_muxed21 = 3'd0; +reg [13:0] builder_array_muxed22 = 14'd0; +reg builder_array_muxed23 = 1'd0; +reg builder_array_muxed24 = 1'd0; +reg builder_array_muxed25 = 1'd0; +reg builder_array_muxed26 = 1'd0; +reg builder_array_muxed27 = 1'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg builder_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg builder_regs1 = 1'd0; +wire builder_xilinxasyncresetsynchronizerimpl0; +wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl1; +wire builder_xilinxasyncresetsynchronizerimpl1_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl1_expr; +wire builder_xilinxasyncresetsynchronizerimpl2; +wire builder_xilinxasyncresetsynchronizerimpl2_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl2_expr; +wire builder_xilinxasyncresetsynchronizerimpl3; +wire builder_xilinxasyncresetsynchronizerimpl3_rst_meta; + +assign main_cpu_reset = main_ctrl_reset; +assign main_ctrl_bus_error = builder_minsoc_error; +always @(*) begin + main_cpu_interrupt <= 32'd0; + main_cpu_interrupt[1] <= main_timer0_irq; + main_cpu_interrupt[0] <= main_uart_irq; +end +assign main_ctrl_reset = main_ctrl_reset_reset_re; +assign main_ctrl_bus_errors_status = main_ctrl_bus_errors; +assign main_interface0_soc_bus_adr = main_cpu_ibus_adr; +assign main_interface0_soc_bus_dat_w = main_cpu_ibus_dat_w; +assign main_cpu_ibus_dat_r = main_interface0_soc_bus_dat_r; +assign main_interface0_soc_bus_sel = main_cpu_ibus_sel; +assign main_interface0_soc_bus_cyc = main_cpu_ibus_cyc; +assign main_interface0_soc_bus_stb = main_cpu_ibus_stb; +assign main_cpu_ibus_ack = main_interface0_soc_bus_ack; +assign main_interface0_soc_bus_we = main_cpu_ibus_we; +assign main_interface0_soc_bus_cti = main_cpu_ibus_cti; +assign main_interface0_soc_bus_bte = main_cpu_ibus_bte; +assign main_cpu_ibus_err = main_interface0_soc_bus_err; +assign main_interface1_soc_bus_adr = main_cpu_dbus_adr; +assign main_interface1_soc_bus_dat_w = main_cpu_dbus_dat_w; +assign main_cpu_dbus_dat_r = main_interface1_soc_bus_dat_r; +assign main_interface1_soc_bus_sel = main_cpu_dbus_sel; +assign main_interface1_soc_bus_cyc = main_cpu_dbus_cyc; +assign main_interface1_soc_bus_stb = main_cpu_dbus_stb; +assign main_cpu_dbus_ack = main_interface1_soc_bus_ack; +assign main_interface1_soc_bus_we = main_cpu_dbus_we; +assign main_interface1_soc_bus_cti = main_cpu_dbus_cti; +assign main_interface1_soc_bus_bte = main_cpu_dbus_bte; +assign main_cpu_dbus_err = main_interface1_soc_bus_err; +assign main_rom_adr = main_rom_bus_adr[12:0]; +assign main_rom_bus_dat_r = main_rom_dat_r; +always @(*) begin + main_sram_we <= 4'd0; + main_sram_we[0] <= (((main_sram_bus_cyc & main_sram_bus_stb) & main_sram_bus_we) & main_sram_bus_sel[0]); + main_sram_we[1] <= (((main_sram_bus_cyc & main_sram_bus_stb) & main_sram_bus_we) & main_sram_bus_sel[1]); + main_sram_we[2] <= (((main_sram_bus_cyc & main_sram_bus_stb) & main_sram_bus_we) & main_sram_bus_sel[2]); + main_sram_we[3] <= (((main_sram_bus_cyc & main_sram_bus_stb) & main_sram_bus_we) & main_sram_bus_sel[3]); +end +assign main_sram_adr = main_sram_bus_adr[12:0]; +assign main_sram_bus_dat_r = main_sram_dat_r; +assign main_sram_dat_w = main_sram_bus_dat_w; +assign main_uart_tx_fifo_sink_valid = main_uart_rxtx_re; +assign main_uart_tx_fifo_sink_payload_data = main_uart_rxtx_r; +assign main_uart_txfull_status = (~main_uart_tx_fifo_sink_ready); +assign main_uart_phy_sink_valid = main_uart_tx_fifo_source_valid; +assign main_uart_tx_fifo_source_ready = main_uart_phy_sink_ready; +assign main_uart_phy_sink_first = main_uart_tx_fifo_source_first; +assign main_uart_phy_sink_last = main_uart_tx_fifo_source_last; +assign main_uart_phy_sink_payload_data = main_uart_tx_fifo_source_payload_data; +assign main_uart_tx_trigger = (~main_uart_tx_fifo_sink_ready); +assign main_uart_rx_fifo_sink_valid = main_uart_phy_source_valid; +assign main_uart_phy_source_ready = main_uart_rx_fifo_sink_ready; +assign main_uart_rx_fifo_sink_first = main_uart_phy_source_first; +assign main_uart_rx_fifo_sink_last = main_uart_phy_source_last; +assign main_uart_rx_fifo_sink_payload_data = main_uart_phy_source_payload_data; +assign main_uart_rxempty_status = (~main_uart_rx_fifo_source_valid); +assign main_uart_rxtx_w = main_uart_rx_fifo_source_payload_data; +assign main_uart_rx_fifo_source_ready = main_uart_rx_clear; +assign main_uart_rx_trigger = (~main_uart_rx_fifo_source_valid); +always @(*) begin + main_uart_tx_clear <= 1'd0; + if ((main_uart_eventmanager_pending_re & main_uart_eventmanager_pending_r[0])) begin + main_uart_tx_clear <= 1'd1; + end +end +always @(*) begin + main_uart_eventmanager_status_w <= 2'd0; + main_uart_eventmanager_status_w[0] <= main_uart_tx_status; + main_uart_eventmanager_status_w[1] <= main_uart_rx_status; +end +always @(*) begin + main_uart_rx_clear <= 1'd0; + if ((main_uart_eventmanager_pending_re & main_uart_eventmanager_pending_r[1])) begin + main_uart_rx_clear <= 1'd1; + end +end +always @(*) begin + main_uart_eventmanager_pending_w <= 2'd0; + main_uart_eventmanager_pending_w[0] <= main_uart_tx_pending; + main_uart_eventmanager_pending_w[1] <= main_uart_rx_pending; +end +assign main_uart_irq = ((main_uart_eventmanager_pending_w[0] & main_uart_eventmanager_storage[0]) | (main_uart_eventmanager_pending_w[1] & main_uart_eventmanager_storage[1])); +assign main_uart_tx_status = main_uart_tx_trigger; +assign main_uart_rx_status = main_uart_rx_trigger; +assign main_uart_tx_fifo_syncfifo_din = {main_uart_tx_fifo_fifo_in_last, main_uart_tx_fifo_fifo_in_first, main_uart_tx_fifo_fifo_in_payload_data}; +assign {main_uart_tx_fifo_fifo_out_last, main_uart_tx_fifo_fifo_out_first, main_uart_tx_fifo_fifo_out_payload_data} = main_uart_tx_fifo_syncfifo_dout; +assign main_uart_tx_fifo_sink_ready = main_uart_tx_fifo_syncfifo_writable; +assign main_uart_tx_fifo_syncfifo_we = main_uart_tx_fifo_sink_valid; +assign main_uart_tx_fifo_fifo_in_first = main_uart_tx_fifo_sink_first; +assign main_uart_tx_fifo_fifo_in_last = main_uart_tx_fifo_sink_last; +assign main_uart_tx_fifo_fifo_in_payload_data = main_uart_tx_fifo_sink_payload_data; +assign main_uart_tx_fifo_source_valid = main_uart_tx_fifo_readable; +assign main_uart_tx_fifo_source_first = main_uart_tx_fifo_fifo_out_first; +assign main_uart_tx_fifo_source_last = main_uart_tx_fifo_fifo_out_last; +assign main_uart_tx_fifo_source_payload_data = main_uart_tx_fifo_fifo_out_payload_data; +assign main_uart_tx_fifo_re = main_uart_tx_fifo_source_ready; +assign main_uart_tx_fifo_syncfifo_re = (main_uart_tx_fifo_syncfifo_readable & ((~main_uart_tx_fifo_readable) | main_uart_tx_fifo_re)); +assign main_uart_tx_fifo_level1 = (main_uart_tx_fifo_level0 + main_uart_tx_fifo_readable); +always @(*) begin + main_uart_tx_fifo_wrport_adr <= 4'd0; + if (main_uart_tx_fifo_replace) begin + main_uart_tx_fifo_wrport_adr <= (main_uart_tx_fifo_produce - 1'd1); + end else begin + main_uart_tx_fifo_wrport_adr <= main_uart_tx_fifo_produce; + end +end +assign main_uart_tx_fifo_wrport_dat_w = main_uart_tx_fifo_syncfifo_din; +assign main_uart_tx_fifo_wrport_we = (main_uart_tx_fifo_syncfifo_we & (main_uart_tx_fifo_syncfifo_writable | main_uart_tx_fifo_replace)); +assign main_uart_tx_fifo_do_read = (main_uart_tx_fifo_syncfifo_readable & main_uart_tx_fifo_syncfifo_re); +assign main_uart_tx_fifo_rdport_adr = main_uart_tx_fifo_consume; +assign main_uart_tx_fifo_syncfifo_dout = main_uart_tx_fifo_rdport_dat_r; +assign main_uart_tx_fifo_rdport_re = main_uart_tx_fifo_do_read; +assign main_uart_tx_fifo_syncfifo_writable = (main_uart_tx_fifo_level0 != 5'd16); +assign main_uart_tx_fifo_syncfifo_readable = (main_uart_tx_fifo_level0 != 1'd0); +assign main_uart_rx_fifo_syncfifo_din = {main_uart_rx_fifo_fifo_in_last, main_uart_rx_fifo_fifo_in_first, main_uart_rx_fifo_fifo_in_payload_data}; +assign {main_uart_rx_fifo_fifo_out_last, main_uart_rx_fifo_fifo_out_first, main_uart_rx_fifo_fifo_out_payload_data} = main_uart_rx_fifo_syncfifo_dout; +assign main_uart_rx_fifo_sink_ready = main_uart_rx_fifo_syncfifo_writable; +assign main_uart_rx_fifo_syncfifo_we = main_uart_rx_fifo_sink_valid; +assign main_uart_rx_fifo_fifo_in_first = main_uart_rx_fifo_sink_first; +assign main_uart_rx_fifo_fifo_in_last = main_uart_rx_fifo_sink_last; +assign main_uart_rx_fifo_fifo_in_payload_data = main_uart_rx_fifo_sink_payload_data; +assign main_uart_rx_fifo_source_valid = main_uart_rx_fifo_readable; +assign main_uart_rx_fifo_source_first = main_uart_rx_fifo_fifo_out_first; +assign main_uart_rx_fifo_source_last = main_uart_rx_fifo_fifo_out_last; +assign main_uart_rx_fifo_source_payload_data = main_uart_rx_fifo_fifo_out_payload_data; +assign main_uart_rx_fifo_re = main_uart_rx_fifo_source_ready; +assign main_uart_rx_fifo_syncfifo_re = (main_uart_rx_fifo_syncfifo_readable & ((~main_uart_rx_fifo_readable) | main_uart_rx_fifo_re)); +assign main_uart_rx_fifo_level1 = (main_uart_rx_fifo_level0 + main_uart_rx_fifo_readable); +always @(*) begin + main_uart_rx_fifo_wrport_adr <= 4'd0; + if (main_uart_rx_fifo_replace) begin + main_uart_rx_fifo_wrport_adr <= (main_uart_rx_fifo_produce - 1'd1); + end else begin + main_uart_rx_fifo_wrport_adr <= main_uart_rx_fifo_produce; + end +end +assign main_uart_rx_fifo_wrport_dat_w = main_uart_rx_fifo_syncfifo_din; +assign main_uart_rx_fifo_wrport_we = (main_uart_rx_fifo_syncfifo_we & (main_uart_rx_fifo_syncfifo_writable | main_uart_rx_fifo_replace)); +assign main_uart_rx_fifo_do_read = (main_uart_rx_fifo_syncfifo_readable & main_uart_rx_fifo_syncfifo_re); +assign main_uart_rx_fifo_rdport_adr = main_uart_rx_fifo_consume; +assign main_uart_rx_fifo_syncfifo_dout = main_uart_rx_fifo_rdport_dat_r; +assign main_uart_rx_fifo_rdport_re = main_uart_rx_fifo_do_read; +assign main_uart_rx_fifo_syncfifo_writable = (main_uart_rx_fifo_level0 != 5'd16); +assign main_uart_rx_fifo_syncfifo_readable = (main_uart_rx_fifo_level0 != 1'd0); +assign main_timer0_zero_trigger = (main_timer0_value != 1'd0); +assign main_timer0_eventmanager_status_w = main_timer0_zero_status; +always @(*) begin + main_timer0_zero_clear <= 1'd0; + if ((main_timer0_eventmanager_pending_re & main_timer0_eventmanager_pending_r)) begin + main_timer0_zero_clear <= 1'd1; + end +end +assign main_timer0_eventmanager_pending_w = main_timer0_zero_pending; +assign main_timer0_irq = (main_timer0_eventmanager_pending_w & main_timer0_eventmanager_storage); +assign main_timer0_zero_status = main_timer0_zero_trigger; +assign main_interface_dat_w = main_bus_wishbone_dat_w; +assign main_bus_wishbone_dat_r = main_interface_dat_r; +always @(*) begin + builder_wb2csr_next_state <= 1'd0; + main_interface_adr <= 14'd0; + main_interface_we <= 1'd0; + main_bus_wishbone_ack <= 1'd0; + builder_wb2csr_next_state <= builder_wb2csr_state; + case (builder_wb2csr_state) + 1'd1: begin + main_bus_wishbone_ack <= 1'd1; + builder_wb2csr_next_state <= 1'd0; + end + default: begin + if ((main_bus_wishbone_cyc & main_bus_wishbone_stb)) begin + main_interface_adr <= main_bus_wishbone_adr; + main_interface_we <= main_bus_wishbone_we; + builder_wb2csr_next_state <= 1'd1; + end + end + endcase +end +assign main_reset = (~cpu_reset); +assign main_clkin = main_pll_clkin; +assign sys_clk = main_clkout_buf0; +assign sys4x_clk = main_clkout_buf1; +assign sys4x_dqs_clk = main_clkout_buf2; +assign clk200_clk = main_clkout_buf3; +always @(*) begin + main_a7ddrphy_dqs_serdes_pattern <= 8'd85; + if ((main_a7ddrphy_dqs_preamble | main_a7ddrphy_dqs_postamble)) begin + main_a7ddrphy_dqs_serdes_pattern <= 1'd0; + end else begin + main_a7ddrphy_dqs_serdes_pattern <= 7'd85; + end +end +assign main_a7ddrphy_bitslip0_i = main_a7ddrphy_dq_i_data0; +assign main_a7ddrphy_bitslip1_i = main_a7ddrphy_dq_i_data1; +assign main_a7ddrphy_bitslip2_i = main_a7ddrphy_dq_i_data2; +assign main_a7ddrphy_bitslip3_i = main_a7ddrphy_dq_i_data3; +assign main_a7ddrphy_bitslip4_i = main_a7ddrphy_dq_i_data4; +assign main_a7ddrphy_bitslip5_i = main_a7ddrphy_dq_i_data5; +assign main_a7ddrphy_bitslip6_i = main_a7ddrphy_dq_i_data6; +assign main_a7ddrphy_bitslip7_i = main_a7ddrphy_dq_i_data7; +assign main_a7ddrphy_bitslip8_i = main_a7ddrphy_dq_i_data8; +assign main_a7ddrphy_bitslip9_i = main_a7ddrphy_dq_i_data9; +assign main_a7ddrphy_bitslip10_i = main_a7ddrphy_dq_i_data10; +assign main_a7ddrphy_bitslip11_i = main_a7ddrphy_dq_i_data11; +assign main_a7ddrphy_bitslip12_i = main_a7ddrphy_dq_i_data12; +assign main_a7ddrphy_bitslip13_i = main_a7ddrphy_dq_i_data13; +assign main_a7ddrphy_bitslip14_i = main_a7ddrphy_dq_i_data14; +assign main_a7ddrphy_bitslip15_i = main_a7ddrphy_dq_i_data15; +always @(*) begin + main_a7ddrphy_dfi_p0_rddata <= 32'd0; + main_a7ddrphy_dfi_p0_rddata[0] <= main_a7ddrphy_bitslip0_o[0]; + main_a7ddrphy_dfi_p0_rddata[16] <= main_a7ddrphy_bitslip0_o[1]; + main_a7ddrphy_dfi_p0_rddata[1] <= main_a7ddrphy_bitslip1_o[0]; + main_a7ddrphy_dfi_p0_rddata[17] <= main_a7ddrphy_bitslip1_o[1]; + main_a7ddrphy_dfi_p0_rddata[2] <= main_a7ddrphy_bitslip2_o[0]; + main_a7ddrphy_dfi_p0_rddata[18] <= main_a7ddrphy_bitslip2_o[1]; + main_a7ddrphy_dfi_p0_rddata[3] <= main_a7ddrphy_bitslip3_o[0]; + main_a7ddrphy_dfi_p0_rddata[19] <= main_a7ddrphy_bitslip3_o[1]; + main_a7ddrphy_dfi_p0_rddata[4] <= main_a7ddrphy_bitslip4_o[0]; + main_a7ddrphy_dfi_p0_rddata[20] <= main_a7ddrphy_bitslip4_o[1]; + main_a7ddrphy_dfi_p0_rddata[5] <= main_a7ddrphy_bitslip5_o[0]; + main_a7ddrphy_dfi_p0_rddata[21] <= main_a7ddrphy_bitslip5_o[1]; + main_a7ddrphy_dfi_p0_rddata[6] <= main_a7ddrphy_bitslip6_o[0]; + main_a7ddrphy_dfi_p0_rddata[22] <= main_a7ddrphy_bitslip6_o[1]; + main_a7ddrphy_dfi_p0_rddata[7] <= main_a7ddrphy_bitslip7_o[0]; + main_a7ddrphy_dfi_p0_rddata[23] <= main_a7ddrphy_bitslip7_o[1]; + main_a7ddrphy_dfi_p0_rddata[8] <= main_a7ddrphy_bitslip8_o[0]; + main_a7ddrphy_dfi_p0_rddata[24] <= main_a7ddrphy_bitslip8_o[1]; + main_a7ddrphy_dfi_p0_rddata[9] <= main_a7ddrphy_bitslip9_o[0]; + main_a7ddrphy_dfi_p0_rddata[25] <= main_a7ddrphy_bitslip9_o[1]; + main_a7ddrphy_dfi_p0_rddata[10] <= main_a7ddrphy_bitslip10_o[0]; + main_a7ddrphy_dfi_p0_rddata[26] <= main_a7ddrphy_bitslip10_o[1]; + main_a7ddrphy_dfi_p0_rddata[11] <= main_a7ddrphy_bitslip11_o[0]; + main_a7ddrphy_dfi_p0_rddata[27] <= main_a7ddrphy_bitslip11_o[1]; + main_a7ddrphy_dfi_p0_rddata[12] <= main_a7ddrphy_bitslip12_o[0]; + main_a7ddrphy_dfi_p0_rddata[28] <= main_a7ddrphy_bitslip12_o[1]; + main_a7ddrphy_dfi_p0_rddata[13] <= main_a7ddrphy_bitslip13_o[0]; + main_a7ddrphy_dfi_p0_rddata[29] <= main_a7ddrphy_bitslip13_o[1]; + main_a7ddrphy_dfi_p0_rddata[14] <= main_a7ddrphy_bitslip14_o[0]; + main_a7ddrphy_dfi_p0_rddata[30] <= main_a7ddrphy_bitslip14_o[1]; + main_a7ddrphy_dfi_p0_rddata[15] <= main_a7ddrphy_bitslip15_o[0]; + main_a7ddrphy_dfi_p0_rddata[31] <= main_a7ddrphy_bitslip15_o[1]; +end +always @(*) begin + main_a7ddrphy_dfi_p1_rddata <= 32'd0; + main_a7ddrphy_dfi_p1_rddata[0] <= main_a7ddrphy_bitslip0_o[2]; + main_a7ddrphy_dfi_p1_rddata[16] <= main_a7ddrphy_bitslip0_o[3]; + main_a7ddrphy_dfi_p1_rddata[1] <= main_a7ddrphy_bitslip1_o[2]; + main_a7ddrphy_dfi_p1_rddata[17] <= main_a7ddrphy_bitslip1_o[3]; + main_a7ddrphy_dfi_p1_rddata[2] <= main_a7ddrphy_bitslip2_o[2]; + main_a7ddrphy_dfi_p1_rddata[18] <= main_a7ddrphy_bitslip2_o[3]; + main_a7ddrphy_dfi_p1_rddata[3] <= main_a7ddrphy_bitslip3_o[2]; + main_a7ddrphy_dfi_p1_rddata[19] <= main_a7ddrphy_bitslip3_o[3]; + main_a7ddrphy_dfi_p1_rddata[4] <= main_a7ddrphy_bitslip4_o[2]; + main_a7ddrphy_dfi_p1_rddata[20] <= main_a7ddrphy_bitslip4_o[3]; + main_a7ddrphy_dfi_p1_rddata[5] <= main_a7ddrphy_bitslip5_o[2]; + main_a7ddrphy_dfi_p1_rddata[21] <= main_a7ddrphy_bitslip5_o[3]; + main_a7ddrphy_dfi_p1_rddata[6] <= main_a7ddrphy_bitslip6_o[2]; + main_a7ddrphy_dfi_p1_rddata[22] <= main_a7ddrphy_bitslip6_o[3]; + main_a7ddrphy_dfi_p1_rddata[7] <= main_a7ddrphy_bitslip7_o[2]; + main_a7ddrphy_dfi_p1_rddata[23] <= main_a7ddrphy_bitslip7_o[3]; + main_a7ddrphy_dfi_p1_rddata[8] <= main_a7ddrphy_bitslip8_o[2]; + main_a7ddrphy_dfi_p1_rddata[24] <= main_a7ddrphy_bitslip8_o[3]; + main_a7ddrphy_dfi_p1_rddata[9] <= main_a7ddrphy_bitslip9_o[2]; + main_a7ddrphy_dfi_p1_rddata[25] <= main_a7ddrphy_bitslip9_o[3]; + main_a7ddrphy_dfi_p1_rddata[10] <= main_a7ddrphy_bitslip10_o[2]; + main_a7ddrphy_dfi_p1_rddata[26] <= main_a7ddrphy_bitslip10_o[3]; + main_a7ddrphy_dfi_p1_rddata[11] <= main_a7ddrphy_bitslip11_o[2]; + main_a7ddrphy_dfi_p1_rddata[27] <= main_a7ddrphy_bitslip11_o[3]; + main_a7ddrphy_dfi_p1_rddata[12] <= main_a7ddrphy_bitslip12_o[2]; + main_a7ddrphy_dfi_p1_rddata[28] <= main_a7ddrphy_bitslip12_o[3]; + main_a7ddrphy_dfi_p1_rddata[13] <= main_a7ddrphy_bitslip13_o[2]; + main_a7ddrphy_dfi_p1_rddata[29] <= main_a7ddrphy_bitslip13_o[3]; + main_a7ddrphy_dfi_p1_rddata[14] <= main_a7ddrphy_bitslip14_o[2]; + main_a7ddrphy_dfi_p1_rddata[30] <= main_a7ddrphy_bitslip14_o[3]; + main_a7ddrphy_dfi_p1_rddata[15] <= main_a7ddrphy_bitslip15_o[2]; + main_a7ddrphy_dfi_p1_rddata[31] <= main_a7ddrphy_bitslip15_o[3]; +end +always @(*) begin + main_a7ddrphy_dfi_p2_rddata <= 32'd0; + main_a7ddrphy_dfi_p2_rddata[0] <= main_a7ddrphy_bitslip0_o[4]; + main_a7ddrphy_dfi_p2_rddata[16] <= main_a7ddrphy_bitslip0_o[5]; + main_a7ddrphy_dfi_p2_rddata[1] <= main_a7ddrphy_bitslip1_o[4]; + main_a7ddrphy_dfi_p2_rddata[17] <= main_a7ddrphy_bitslip1_o[5]; + main_a7ddrphy_dfi_p2_rddata[2] <= main_a7ddrphy_bitslip2_o[4]; + main_a7ddrphy_dfi_p2_rddata[18] <= main_a7ddrphy_bitslip2_o[5]; + main_a7ddrphy_dfi_p2_rddata[3] <= main_a7ddrphy_bitslip3_o[4]; + main_a7ddrphy_dfi_p2_rddata[19] <= main_a7ddrphy_bitslip3_o[5]; + main_a7ddrphy_dfi_p2_rddata[4] <= main_a7ddrphy_bitslip4_o[4]; + main_a7ddrphy_dfi_p2_rddata[20] <= main_a7ddrphy_bitslip4_o[5]; + main_a7ddrphy_dfi_p2_rddata[5] <= main_a7ddrphy_bitslip5_o[4]; + main_a7ddrphy_dfi_p2_rddata[21] <= main_a7ddrphy_bitslip5_o[5]; + main_a7ddrphy_dfi_p2_rddata[6] <= main_a7ddrphy_bitslip6_o[4]; + main_a7ddrphy_dfi_p2_rddata[22] <= main_a7ddrphy_bitslip6_o[5]; + main_a7ddrphy_dfi_p2_rddata[7] <= main_a7ddrphy_bitslip7_o[4]; + main_a7ddrphy_dfi_p2_rddata[23] <= main_a7ddrphy_bitslip7_o[5]; + main_a7ddrphy_dfi_p2_rddata[8] <= main_a7ddrphy_bitslip8_o[4]; + main_a7ddrphy_dfi_p2_rddata[24] <= main_a7ddrphy_bitslip8_o[5]; + main_a7ddrphy_dfi_p2_rddata[9] <= main_a7ddrphy_bitslip9_o[4]; + main_a7ddrphy_dfi_p2_rddata[25] <= main_a7ddrphy_bitslip9_o[5]; + main_a7ddrphy_dfi_p2_rddata[10] <= main_a7ddrphy_bitslip10_o[4]; + main_a7ddrphy_dfi_p2_rddata[26] <= main_a7ddrphy_bitslip10_o[5]; + main_a7ddrphy_dfi_p2_rddata[11] <= main_a7ddrphy_bitslip11_o[4]; + main_a7ddrphy_dfi_p2_rddata[27] <= main_a7ddrphy_bitslip11_o[5]; + main_a7ddrphy_dfi_p2_rddata[12] <= main_a7ddrphy_bitslip12_o[4]; + main_a7ddrphy_dfi_p2_rddata[28] <= main_a7ddrphy_bitslip12_o[5]; + main_a7ddrphy_dfi_p2_rddata[13] <= main_a7ddrphy_bitslip13_o[4]; + main_a7ddrphy_dfi_p2_rddata[29] <= main_a7ddrphy_bitslip13_o[5]; + main_a7ddrphy_dfi_p2_rddata[14] <= main_a7ddrphy_bitslip14_o[4]; + main_a7ddrphy_dfi_p2_rddata[30] <= main_a7ddrphy_bitslip14_o[5]; + main_a7ddrphy_dfi_p2_rddata[15] <= main_a7ddrphy_bitslip15_o[4]; + main_a7ddrphy_dfi_p2_rddata[31] <= main_a7ddrphy_bitslip15_o[5]; +end +always @(*) begin + main_a7ddrphy_dfi_p3_rddata <= 32'd0; + main_a7ddrphy_dfi_p3_rddata[0] <= main_a7ddrphy_bitslip0_o[6]; + main_a7ddrphy_dfi_p3_rddata[16] <= main_a7ddrphy_bitslip0_o[7]; + main_a7ddrphy_dfi_p3_rddata[1] <= main_a7ddrphy_bitslip1_o[6]; + main_a7ddrphy_dfi_p3_rddata[17] <= main_a7ddrphy_bitslip1_o[7]; + main_a7ddrphy_dfi_p3_rddata[2] <= main_a7ddrphy_bitslip2_o[6]; + main_a7ddrphy_dfi_p3_rddata[18] <= main_a7ddrphy_bitslip2_o[7]; + main_a7ddrphy_dfi_p3_rddata[3] <= main_a7ddrphy_bitslip3_o[6]; + main_a7ddrphy_dfi_p3_rddata[19] <= main_a7ddrphy_bitslip3_o[7]; + main_a7ddrphy_dfi_p3_rddata[4] <= main_a7ddrphy_bitslip4_o[6]; + main_a7ddrphy_dfi_p3_rddata[20] <= main_a7ddrphy_bitslip4_o[7]; + main_a7ddrphy_dfi_p3_rddata[5] <= main_a7ddrphy_bitslip5_o[6]; + main_a7ddrphy_dfi_p3_rddata[21] <= main_a7ddrphy_bitslip5_o[7]; + main_a7ddrphy_dfi_p3_rddata[6] <= main_a7ddrphy_bitslip6_o[6]; + main_a7ddrphy_dfi_p3_rddata[22] <= main_a7ddrphy_bitslip6_o[7]; + main_a7ddrphy_dfi_p3_rddata[7] <= main_a7ddrphy_bitslip7_o[6]; + main_a7ddrphy_dfi_p3_rddata[23] <= main_a7ddrphy_bitslip7_o[7]; + main_a7ddrphy_dfi_p3_rddata[8] <= main_a7ddrphy_bitslip8_o[6]; + main_a7ddrphy_dfi_p3_rddata[24] <= main_a7ddrphy_bitslip8_o[7]; + main_a7ddrphy_dfi_p3_rddata[9] <= main_a7ddrphy_bitslip9_o[6]; + main_a7ddrphy_dfi_p3_rddata[25] <= main_a7ddrphy_bitslip9_o[7]; + main_a7ddrphy_dfi_p3_rddata[10] <= main_a7ddrphy_bitslip10_o[6]; + main_a7ddrphy_dfi_p3_rddata[26] <= main_a7ddrphy_bitslip10_o[7]; + main_a7ddrphy_dfi_p3_rddata[11] <= main_a7ddrphy_bitslip11_o[6]; + main_a7ddrphy_dfi_p3_rddata[27] <= main_a7ddrphy_bitslip11_o[7]; + main_a7ddrphy_dfi_p3_rddata[12] <= main_a7ddrphy_bitslip12_o[6]; + main_a7ddrphy_dfi_p3_rddata[28] <= main_a7ddrphy_bitslip12_o[7]; + main_a7ddrphy_dfi_p3_rddata[13] <= main_a7ddrphy_bitslip13_o[6]; + main_a7ddrphy_dfi_p3_rddata[29] <= main_a7ddrphy_bitslip13_o[7]; + main_a7ddrphy_dfi_p3_rddata[14] <= main_a7ddrphy_bitslip14_o[6]; + main_a7ddrphy_dfi_p3_rddata[30] <= main_a7ddrphy_bitslip14_o[7]; + main_a7ddrphy_dfi_p3_rddata[15] <= main_a7ddrphy_bitslip15_o[6]; + main_a7ddrphy_dfi_p3_rddata[31] <= main_a7ddrphy_bitslip15_o[7]; +end +assign main_a7ddrphy_oe = ((main_a7ddrphy_last_wrdata_en[1] | main_a7ddrphy_last_wrdata_en[2]) | main_a7ddrphy_last_wrdata_en[3]); +assign main_a7ddrphy_dqs_preamble = (main_a7ddrphy_last_wrdata_en[1] & (~main_a7ddrphy_last_wrdata_en[2])); +assign main_a7ddrphy_dqs_postamble = (main_a7ddrphy_last_wrdata_en[3] & (~main_a7ddrphy_last_wrdata_en[2])); +assign main_a7ddrphy_dfi_p0_address = main_sdram_master_p0_address; +assign main_a7ddrphy_dfi_p0_bank = main_sdram_master_p0_bank; +assign main_a7ddrphy_dfi_p0_cas_n = main_sdram_master_p0_cas_n; +assign main_a7ddrphy_dfi_p0_cs_n = main_sdram_master_p0_cs_n; +assign main_a7ddrphy_dfi_p0_ras_n = main_sdram_master_p0_ras_n; +assign main_a7ddrphy_dfi_p0_we_n = main_sdram_master_p0_we_n; +assign main_a7ddrphy_dfi_p0_cke = main_sdram_master_p0_cke; +assign main_a7ddrphy_dfi_p0_odt = main_sdram_master_p0_odt; +assign main_a7ddrphy_dfi_p0_reset_n = main_sdram_master_p0_reset_n; +assign main_a7ddrphy_dfi_p0_act_n = main_sdram_master_p0_act_n; +assign main_a7ddrphy_dfi_p0_wrdata = main_sdram_master_p0_wrdata; +assign main_a7ddrphy_dfi_p0_wrdata_en = main_sdram_master_p0_wrdata_en; +assign main_a7ddrphy_dfi_p0_wrdata_mask = main_sdram_master_p0_wrdata_mask; +assign main_a7ddrphy_dfi_p0_rddata_en = main_sdram_master_p0_rddata_en; +assign main_sdram_master_p0_rddata = main_a7ddrphy_dfi_p0_rddata; +assign main_sdram_master_p0_rddata_valid = main_a7ddrphy_dfi_p0_rddata_valid; +assign main_a7ddrphy_dfi_p1_address = main_sdram_master_p1_address; +assign main_a7ddrphy_dfi_p1_bank = main_sdram_master_p1_bank; +assign main_a7ddrphy_dfi_p1_cas_n = main_sdram_master_p1_cas_n; +assign main_a7ddrphy_dfi_p1_cs_n = main_sdram_master_p1_cs_n; +assign main_a7ddrphy_dfi_p1_ras_n = main_sdram_master_p1_ras_n; +assign main_a7ddrphy_dfi_p1_we_n = main_sdram_master_p1_we_n; +assign main_a7ddrphy_dfi_p1_cke = main_sdram_master_p1_cke; +assign main_a7ddrphy_dfi_p1_odt = main_sdram_master_p1_odt; +assign main_a7ddrphy_dfi_p1_reset_n = main_sdram_master_p1_reset_n; +assign main_a7ddrphy_dfi_p1_act_n = main_sdram_master_p1_act_n; +assign main_a7ddrphy_dfi_p1_wrdata = main_sdram_master_p1_wrdata; +assign main_a7ddrphy_dfi_p1_wrdata_en = main_sdram_master_p1_wrdata_en; +assign main_a7ddrphy_dfi_p1_wrdata_mask = main_sdram_master_p1_wrdata_mask; +assign main_a7ddrphy_dfi_p1_rddata_en = main_sdram_master_p1_rddata_en; +assign main_sdram_master_p1_rddata = main_a7ddrphy_dfi_p1_rddata; +assign main_sdram_master_p1_rddata_valid = main_a7ddrphy_dfi_p1_rddata_valid; +assign main_a7ddrphy_dfi_p2_address = main_sdram_master_p2_address; +assign main_a7ddrphy_dfi_p2_bank = main_sdram_master_p2_bank; +assign main_a7ddrphy_dfi_p2_cas_n = main_sdram_master_p2_cas_n; +assign main_a7ddrphy_dfi_p2_cs_n = main_sdram_master_p2_cs_n; +assign main_a7ddrphy_dfi_p2_ras_n = main_sdram_master_p2_ras_n; +assign main_a7ddrphy_dfi_p2_we_n = main_sdram_master_p2_we_n; +assign main_a7ddrphy_dfi_p2_cke = main_sdram_master_p2_cke; +assign main_a7ddrphy_dfi_p2_odt = main_sdram_master_p2_odt; +assign main_a7ddrphy_dfi_p2_reset_n = main_sdram_master_p2_reset_n; +assign main_a7ddrphy_dfi_p2_act_n = main_sdram_master_p2_act_n; +assign main_a7ddrphy_dfi_p2_wrdata = main_sdram_master_p2_wrdata; +assign main_a7ddrphy_dfi_p2_wrdata_en = main_sdram_master_p2_wrdata_en; +assign main_a7ddrphy_dfi_p2_wrdata_mask = main_sdram_master_p2_wrdata_mask; +assign main_a7ddrphy_dfi_p2_rddata_en = main_sdram_master_p2_rddata_en; +assign main_sdram_master_p2_rddata = main_a7ddrphy_dfi_p2_rddata; +assign main_sdram_master_p2_rddata_valid = main_a7ddrphy_dfi_p2_rddata_valid; +assign main_a7ddrphy_dfi_p3_address = main_sdram_master_p3_address; +assign main_a7ddrphy_dfi_p3_bank = main_sdram_master_p3_bank; +assign main_a7ddrphy_dfi_p3_cas_n = main_sdram_master_p3_cas_n; +assign main_a7ddrphy_dfi_p3_cs_n = main_sdram_master_p3_cs_n; +assign main_a7ddrphy_dfi_p3_ras_n = main_sdram_master_p3_ras_n; +assign main_a7ddrphy_dfi_p3_we_n = main_sdram_master_p3_we_n; +assign main_a7ddrphy_dfi_p3_cke = main_sdram_master_p3_cke; +assign main_a7ddrphy_dfi_p3_odt = main_sdram_master_p3_odt; +assign main_a7ddrphy_dfi_p3_reset_n = main_sdram_master_p3_reset_n; +assign main_a7ddrphy_dfi_p3_act_n = main_sdram_master_p3_act_n; +assign main_a7ddrphy_dfi_p3_wrdata = main_sdram_master_p3_wrdata; +assign main_a7ddrphy_dfi_p3_wrdata_en = main_sdram_master_p3_wrdata_en; +assign main_a7ddrphy_dfi_p3_wrdata_mask = main_sdram_master_p3_wrdata_mask; +assign main_a7ddrphy_dfi_p3_rddata_en = main_sdram_master_p3_rddata_en; +assign main_sdram_master_p3_rddata = main_a7ddrphy_dfi_p3_rddata; +assign main_sdram_master_p3_rddata_valid = main_a7ddrphy_dfi_p3_rddata_valid; +assign main_sdram_slave_p0_address = main_sdram_dfi_p0_address; +assign main_sdram_slave_p0_bank = main_sdram_dfi_p0_bank; +assign main_sdram_slave_p0_cas_n = main_sdram_dfi_p0_cas_n; +assign main_sdram_slave_p0_cs_n = main_sdram_dfi_p0_cs_n; +assign main_sdram_slave_p0_ras_n = main_sdram_dfi_p0_ras_n; +assign main_sdram_slave_p0_we_n = main_sdram_dfi_p0_we_n; +assign main_sdram_slave_p0_cke = main_sdram_dfi_p0_cke; +assign main_sdram_slave_p0_odt = main_sdram_dfi_p0_odt; +assign main_sdram_slave_p0_reset_n = main_sdram_dfi_p0_reset_n; +assign main_sdram_slave_p0_act_n = main_sdram_dfi_p0_act_n; +assign main_sdram_slave_p0_wrdata = main_sdram_dfi_p0_wrdata; +assign main_sdram_slave_p0_wrdata_en = main_sdram_dfi_p0_wrdata_en; +assign main_sdram_slave_p0_wrdata_mask = main_sdram_dfi_p0_wrdata_mask; +assign main_sdram_slave_p0_rddata_en = main_sdram_dfi_p0_rddata_en; +assign main_sdram_dfi_p0_rddata = main_sdram_slave_p0_rddata; +assign main_sdram_dfi_p0_rddata_valid = main_sdram_slave_p0_rddata_valid; +assign main_sdram_slave_p1_address = main_sdram_dfi_p1_address; +assign main_sdram_slave_p1_bank = main_sdram_dfi_p1_bank; +assign main_sdram_slave_p1_cas_n = main_sdram_dfi_p1_cas_n; +assign main_sdram_slave_p1_cs_n = main_sdram_dfi_p1_cs_n; +assign main_sdram_slave_p1_ras_n = main_sdram_dfi_p1_ras_n; +assign main_sdram_slave_p1_we_n = main_sdram_dfi_p1_we_n; +assign main_sdram_slave_p1_cke = main_sdram_dfi_p1_cke; +assign main_sdram_slave_p1_odt = main_sdram_dfi_p1_odt; +assign main_sdram_slave_p1_reset_n = main_sdram_dfi_p1_reset_n; +assign main_sdram_slave_p1_act_n = main_sdram_dfi_p1_act_n; +assign main_sdram_slave_p1_wrdata = main_sdram_dfi_p1_wrdata; +assign main_sdram_slave_p1_wrdata_en = main_sdram_dfi_p1_wrdata_en; +assign main_sdram_slave_p1_wrdata_mask = main_sdram_dfi_p1_wrdata_mask; +assign main_sdram_slave_p1_rddata_en = main_sdram_dfi_p1_rddata_en; +assign main_sdram_dfi_p1_rddata = main_sdram_slave_p1_rddata; +assign main_sdram_dfi_p1_rddata_valid = main_sdram_slave_p1_rddata_valid; +assign main_sdram_slave_p2_address = main_sdram_dfi_p2_address; +assign main_sdram_slave_p2_bank = main_sdram_dfi_p2_bank; +assign main_sdram_slave_p2_cas_n = main_sdram_dfi_p2_cas_n; +assign main_sdram_slave_p2_cs_n = main_sdram_dfi_p2_cs_n; +assign main_sdram_slave_p2_ras_n = main_sdram_dfi_p2_ras_n; +assign main_sdram_slave_p2_we_n = main_sdram_dfi_p2_we_n; +assign main_sdram_slave_p2_cke = main_sdram_dfi_p2_cke; +assign main_sdram_slave_p2_odt = main_sdram_dfi_p2_odt; +assign main_sdram_slave_p2_reset_n = main_sdram_dfi_p2_reset_n; +assign main_sdram_slave_p2_act_n = main_sdram_dfi_p2_act_n; +assign main_sdram_slave_p2_wrdata = main_sdram_dfi_p2_wrdata; +assign main_sdram_slave_p2_wrdata_en = main_sdram_dfi_p2_wrdata_en; +assign main_sdram_slave_p2_wrdata_mask = main_sdram_dfi_p2_wrdata_mask; +assign main_sdram_slave_p2_rddata_en = main_sdram_dfi_p2_rddata_en; +assign main_sdram_dfi_p2_rddata = main_sdram_slave_p2_rddata; +assign main_sdram_dfi_p2_rddata_valid = main_sdram_slave_p2_rddata_valid; +assign main_sdram_slave_p3_address = main_sdram_dfi_p3_address; +assign main_sdram_slave_p3_bank = main_sdram_dfi_p3_bank; +assign main_sdram_slave_p3_cas_n = main_sdram_dfi_p3_cas_n; +assign main_sdram_slave_p3_cs_n = main_sdram_dfi_p3_cs_n; +assign main_sdram_slave_p3_ras_n = main_sdram_dfi_p3_ras_n; +assign main_sdram_slave_p3_we_n = main_sdram_dfi_p3_we_n; +assign main_sdram_slave_p3_cke = main_sdram_dfi_p3_cke; +assign main_sdram_slave_p3_odt = main_sdram_dfi_p3_odt; +assign main_sdram_slave_p3_reset_n = main_sdram_dfi_p3_reset_n; +assign main_sdram_slave_p3_act_n = main_sdram_dfi_p3_act_n; +assign main_sdram_slave_p3_wrdata = main_sdram_dfi_p3_wrdata; +assign main_sdram_slave_p3_wrdata_en = main_sdram_dfi_p3_wrdata_en; +assign main_sdram_slave_p3_wrdata_mask = main_sdram_dfi_p3_wrdata_mask; +assign main_sdram_slave_p3_rddata_en = main_sdram_dfi_p3_rddata_en; +assign main_sdram_dfi_p3_rddata = main_sdram_slave_p3_rddata; +assign main_sdram_dfi_p3_rddata_valid = main_sdram_slave_p3_rddata_valid; +always @(*) begin + main_sdram_slave_p2_rddata <= 32'd0; + main_sdram_slave_p2_rddata_valid <= 1'd0; + main_sdram_slave_p3_rddata <= 32'd0; + main_sdram_slave_p3_rddata_valid <= 1'd0; + main_sdram_inti_p0_rddata <= 32'd0; + main_sdram_inti_p0_rddata_valid <= 1'd0; + main_sdram_master_p0_address <= 14'd0; + main_sdram_master_p0_bank <= 3'd0; + main_sdram_master_p0_cas_n <= 1'd1; + main_sdram_master_p0_cs_n <= 1'd1; + main_sdram_master_p0_ras_n <= 1'd1; + main_sdram_master_p0_we_n <= 1'd1; + main_sdram_master_p0_cke <= 1'd0; + main_sdram_master_p0_odt <= 1'd0; + main_sdram_master_p0_reset_n <= 1'd0; + main_sdram_master_p0_act_n <= 1'd1; + main_sdram_master_p0_wrdata <= 32'd0; + main_sdram_inti_p1_rddata <= 32'd0; + main_sdram_master_p0_wrdata_en <= 1'd0; + main_sdram_inti_p1_rddata_valid <= 1'd0; + main_sdram_master_p0_wrdata_mask <= 4'd0; + main_sdram_master_p0_rddata_en <= 1'd0; + main_sdram_master_p1_address <= 14'd0; + main_sdram_master_p1_bank <= 3'd0; + main_sdram_master_p1_cas_n <= 1'd1; + main_sdram_master_p1_cs_n <= 1'd1; + main_sdram_master_p1_ras_n <= 1'd1; + main_sdram_master_p1_we_n <= 1'd1; + main_sdram_master_p1_cke <= 1'd0; + main_sdram_master_p1_odt <= 1'd0; + main_sdram_master_p1_reset_n <= 1'd0; + main_sdram_master_p1_act_n <= 1'd1; + main_sdram_master_p1_wrdata <= 32'd0; + main_sdram_inti_p2_rddata <= 32'd0; + main_sdram_master_p1_wrdata_en <= 1'd0; + main_sdram_inti_p2_rddata_valid <= 1'd0; + main_sdram_master_p1_wrdata_mask <= 4'd0; + main_sdram_master_p1_rddata_en <= 1'd0; + main_sdram_master_p2_address <= 14'd0; + main_sdram_master_p2_bank <= 3'd0; + main_sdram_master_p2_cas_n <= 1'd1; + main_sdram_master_p2_cs_n <= 1'd1; + main_sdram_master_p2_ras_n <= 1'd1; + main_sdram_master_p2_we_n <= 1'd1; + main_sdram_master_p2_cke <= 1'd0; + main_sdram_master_p2_odt <= 1'd0; + main_sdram_master_p2_reset_n <= 1'd0; + main_sdram_master_p2_act_n <= 1'd1; + main_sdram_master_p2_wrdata <= 32'd0; + main_sdram_inti_p3_rddata <= 32'd0; + main_sdram_master_p2_wrdata_en <= 1'd0; + main_sdram_inti_p3_rddata_valid <= 1'd0; + main_sdram_master_p2_wrdata_mask <= 4'd0; + main_sdram_master_p2_rddata_en <= 1'd0; + main_sdram_master_p3_address <= 14'd0; + main_sdram_master_p3_bank <= 3'd0; + main_sdram_master_p3_cas_n <= 1'd1; + main_sdram_master_p3_cs_n <= 1'd1; + main_sdram_master_p3_ras_n <= 1'd1; + main_sdram_master_p3_we_n <= 1'd1; + main_sdram_master_p3_cke <= 1'd0; + main_sdram_master_p3_odt <= 1'd0; + main_sdram_master_p3_reset_n <= 1'd0; + main_sdram_master_p3_act_n <= 1'd1; + main_sdram_master_p3_wrdata <= 32'd0; + main_sdram_master_p3_wrdata_en <= 1'd0; + main_sdram_master_p3_wrdata_mask <= 4'd0; + main_sdram_master_p3_rddata_en <= 1'd0; + main_sdram_slave_p0_rddata <= 32'd0; + main_sdram_slave_p0_rddata_valid <= 1'd0; + main_sdram_slave_p1_rddata <= 32'd0; + main_sdram_slave_p1_rddata_valid <= 1'd0; + if (main_sdram_storage[0]) begin + main_sdram_master_p0_address <= main_sdram_slave_p0_address; + main_sdram_master_p0_bank <= main_sdram_slave_p0_bank; + main_sdram_master_p0_cas_n <= main_sdram_slave_p0_cas_n; + main_sdram_master_p0_cs_n <= main_sdram_slave_p0_cs_n; + main_sdram_master_p0_ras_n <= main_sdram_slave_p0_ras_n; + main_sdram_master_p0_we_n <= main_sdram_slave_p0_we_n; + main_sdram_master_p0_cke <= main_sdram_slave_p0_cke; + main_sdram_master_p0_odt <= main_sdram_slave_p0_odt; + main_sdram_master_p0_reset_n <= main_sdram_slave_p0_reset_n; + main_sdram_master_p0_act_n <= main_sdram_slave_p0_act_n; + main_sdram_master_p0_wrdata <= main_sdram_slave_p0_wrdata; + main_sdram_master_p0_wrdata_en <= main_sdram_slave_p0_wrdata_en; + main_sdram_master_p0_wrdata_mask <= main_sdram_slave_p0_wrdata_mask; + main_sdram_master_p0_rddata_en <= main_sdram_slave_p0_rddata_en; + main_sdram_slave_p0_rddata <= main_sdram_master_p0_rddata; + main_sdram_slave_p0_rddata_valid <= main_sdram_master_p0_rddata_valid; + main_sdram_master_p1_address <= main_sdram_slave_p1_address; + main_sdram_master_p1_bank <= main_sdram_slave_p1_bank; + main_sdram_master_p1_cas_n <= main_sdram_slave_p1_cas_n; + main_sdram_master_p1_cs_n <= main_sdram_slave_p1_cs_n; + main_sdram_master_p1_ras_n <= main_sdram_slave_p1_ras_n; + main_sdram_master_p1_we_n <= main_sdram_slave_p1_we_n; + main_sdram_master_p1_cke <= main_sdram_slave_p1_cke; + main_sdram_master_p1_odt <= main_sdram_slave_p1_odt; + main_sdram_master_p1_reset_n <= main_sdram_slave_p1_reset_n; + main_sdram_master_p1_act_n <= main_sdram_slave_p1_act_n; + main_sdram_master_p1_wrdata <= main_sdram_slave_p1_wrdata; + main_sdram_master_p1_wrdata_en <= main_sdram_slave_p1_wrdata_en; + main_sdram_master_p1_wrdata_mask <= main_sdram_slave_p1_wrdata_mask; + main_sdram_master_p1_rddata_en <= main_sdram_slave_p1_rddata_en; + main_sdram_slave_p1_rddata <= main_sdram_master_p1_rddata; + main_sdram_slave_p1_rddata_valid <= main_sdram_master_p1_rddata_valid; + main_sdram_master_p2_address <= main_sdram_slave_p2_address; + main_sdram_master_p2_bank <= main_sdram_slave_p2_bank; + main_sdram_master_p2_cas_n <= main_sdram_slave_p2_cas_n; + main_sdram_master_p2_cs_n <= main_sdram_slave_p2_cs_n; + main_sdram_master_p2_ras_n <= main_sdram_slave_p2_ras_n; + main_sdram_master_p2_we_n <= main_sdram_slave_p2_we_n; + main_sdram_master_p2_cke <= main_sdram_slave_p2_cke; + main_sdram_master_p2_odt <= main_sdram_slave_p2_odt; + main_sdram_master_p2_reset_n <= main_sdram_slave_p2_reset_n; + main_sdram_master_p2_act_n <= main_sdram_slave_p2_act_n; + main_sdram_master_p2_wrdata <= main_sdram_slave_p2_wrdata; + main_sdram_master_p2_wrdata_en <= main_sdram_slave_p2_wrdata_en; + main_sdram_master_p2_wrdata_mask <= main_sdram_slave_p2_wrdata_mask; + main_sdram_master_p2_rddata_en <= main_sdram_slave_p2_rddata_en; + main_sdram_slave_p2_rddata <= main_sdram_master_p2_rddata; + main_sdram_slave_p2_rddata_valid <= main_sdram_master_p2_rddata_valid; + main_sdram_master_p3_address <= main_sdram_slave_p3_address; + main_sdram_master_p3_bank <= main_sdram_slave_p3_bank; + main_sdram_master_p3_cas_n <= main_sdram_slave_p3_cas_n; + main_sdram_master_p3_cs_n <= main_sdram_slave_p3_cs_n; + main_sdram_master_p3_ras_n <= main_sdram_slave_p3_ras_n; + main_sdram_master_p3_we_n <= main_sdram_slave_p3_we_n; + main_sdram_master_p3_cke <= main_sdram_slave_p3_cke; + main_sdram_master_p3_odt <= main_sdram_slave_p3_odt; + main_sdram_master_p3_reset_n <= main_sdram_slave_p3_reset_n; + main_sdram_master_p3_act_n <= main_sdram_slave_p3_act_n; + main_sdram_master_p3_wrdata <= main_sdram_slave_p3_wrdata; + main_sdram_master_p3_wrdata_en <= main_sdram_slave_p3_wrdata_en; + main_sdram_master_p3_wrdata_mask <= main_sdram_slave_p3_wrdata_mask; + main_sdram_master_p3_rddata_en <= main_sdram_slave_p3_rddata_en; + main_sdram_slave_p3_rddata <= main_sdram_master_p3_rddata; + main_sdram_slave_p3_rddata_valid <= main_sdram_master_p3_rddata_valid; + end else begin + main_sdram_master_p0_address <= main_sdram_inti_p0_address; + main_sdram_master_p0_bank <= main_sdram_inti_p0_bank; + main_sdram_master_p0_cas_n <= main_sdram_inti_p0_cas_n; + main_sdram_master_p0_cs_n <= main_sdram_inti_p0_cs_n; + main_sdram_master_p0_ras_n <= main_sdram_inti_p0_ras_n; + main_sdram_master_p0_we_n <= main_sdram_inti_p0_we_n; + main_sdram_master_p0_cke <= main_sdram_inti_p0_cke; + main_sdram_master_p0_odt <= main_sdram_inti_p0_odt; + main_sdram_master_p0_reset_n <= main_sdram_inti_p0_reset_n; + main_sdram_master_p0_act_n <= main_sdram_inti_p0_act_n; + main_sdram_master_p0_wrdata <= main_sdram_inti_p0_wrdata; + main_sdram_master_p0_wrdata_en <= main_sdram_inti_p0_wrdata_en; + main_sdram_master_p0_wrdata_mask <= main_sdram_inti_p0_wrdata_mask; + main_sdram_master_p0_rddata_en <= main_sdram_inti_p0_rddata_en; + main_sdram_inti_p0_rddata <= main_sdram_master_p0_rddata; + main_sdram_inti_p0_rddata_valid <= main_sdram_master_p0_rddata_valid; + main_sdram_master_p1_address <= main_sdram_inti_p1_address; + main_sdram_master_p1_bank <= main_sdram_inti_p1_bank; + main_sdram_master_p1_cas_n <= main_sdram_inti_p1_cas_n; + main_sdram_master_p1_cs_n <= main_sdram_inti_p1_cs_n; + main_sdram_master_p1_ras_n <= main_sdram_inti_p1_ras_n; + main_sdram_master_p1_we_n <= main_sdram_inti_p1_we_n; + main_sdram_master_p1_cke <= main_sdram_inti_p1_cke; + main_sdram_master_p1_odt <= main_sdram_inti_p1_odt; + main_sdram_master_p1_reset_n <= main_sdram_inti_p1_reset_n; + main_sdram_master_p1_act_n <= main_sdram_inti_p1_act_n; + main_sdram_master_p1_wrdata <= main_sdram_inti_p1_wrdata; + main_sdram_master_p1_wrdata_en <= main_sdram_inti_p1_wrdata_en; + main_sdram_master_p1_wrdata_mask <= main_sdram_inti_p1_wrdata_mask; + main_sdram_master_p1_rddata_en <= main_sdram_inti_p1_rddata_en; + main_sdram_inti_p1_rddata <= main_sdram_master_p1_rddata; + main_sdram_inti_p1_rddata_valid <= main_sdram_master_p1_rddata_valid; + main_sdram_master_p2_address <= main_sdram_inti_p2_address; + main_sdram_master_p2_bank <= main_sdram_inti_p2_bank; + main_sdram_master_p2_cas_n <= main_sdram_inti_p2_cas_n; + main_sdram_master_p2_cs_n <= main_sdram_inti_p2_cs_n; + main_sdram_master_p2_ras_n <= main_sdram_inti_p2_ras_n; + main_sdram_master_p2_we_n <= main_sdram_inti_p2_we_n; + main_sdram_master_p2_cke <= main_sdram_inti_p2_cke; + main_sdram_master_p2_odt <= main_sdram_inti_p2_odt; + main_sdram_master_p2_reset_n <= main_sdram_inti_p2_reset_n; + main_sdram_master_p2_act_n <= main_sdram_inti_p2_act_n; + main_sdram_master_p2_wrdata <= main_sdram_inti_p2_wrdata; + main_sdram_master_p2_wrdata_en <= main_sdram_inti_p2_wrdata_en; + main_sdram_master_p2_wrdata_mask <= main_sdram_inti_p2_wrdata_mask; + main_sdram_master_p2_rddata_en <= main_sdram_inti_p2_rddata_en; + main_sdram_inti_p2_rddata <= main_sdram_master_p2_rddata; + main_sdram_inti_p2_rddata_valid <= main_sdram_master_p2_rddata_valid; + main_sdram_master_p3_address <= main_sdram_inti_p3_address; + main_sdram_master_p3_bank <= main_sdram_inti_p3_bank; + main_sdram_master_p3_cas_n <= main_sdram_inti_p3_cas_n; + main_sdram_master_p3_cs_n <= main_sdram_inti_p3_cs_n; + main_sdram_master_p3_ras_n <= main_sdram_inti_p3_ras_n; + main_sdram_master_p3_we_n <= main_sdram_inti_p3_we_n; + main_sdram_master_p3_cke <= main_sdram_inti_p3_cke; + main_sdram_master_p3_odt <= main_sdram_inti_p3_odt; + main_sdram_master_p3_reset_n <= main_sdram_inti_p3_reset_n; + main_sdram_master_p3_act_n <= main_sdram_inti_p3_act_n; + main_sdram_master_p3_wrdata <= main_sdram_inti_p3_wrdata; + main_sdram_master_p3_wrdata_en <= main_sdram_inti_p3_wrdata_en; + main_sdram_master_p3_wrdata_mask <= main_sdram_inti_p3_wrdata_mask; + main_sdram_master_p3_rddata_en <= main_sdram_inti_p3_rddata_en; + main_sdram_inti_p3_rddata <= main_sdram_master_p3_rddata; + main_sdram_inti_p3_rddata_valid <= main_sdram_master_p3_rddata_valid; + end +end +assign main_sdram_inti_p0_cke = main_sdram_storage[1]; +assign main_sdram_inti_p1_cke = main_sdram_storage[1]; +assign main_sdram_inti_p2_cke = main_sdram_storage[1]; +assign main_sdram_inti_p3_cke = main_sdram_storage[1]; +assign main_sdram_inti_p0_odt = main_sdram_storage[2]; +assign main_sdram_inti_p1_odt = main_sdram_storage[2]; +assign main_sdram_inti_p2_odt = main_sdram_storage[2]; +assign main_sdram_inti_p3_odt = main_sdram_storage[2]; +assign main_sdram_inti_p0_reset_n = main_sdram_storage[3]; +assign main_sdram_inti_p1_reset_n = main_sdram_storage[3]; +assign main_sdram_inti_p2_reset_n = main_sdram_storage[3]; +assign main_sdram_inti_p3_reset_n = main_sdram_storage[3]; +always @(*) begin + main_sdram_inti_p0_cs_n <= 1'd1; + main_sdram_inti_p0_ras_n <= 1'd1; + main_sdram_inti_p0_we_n <= 1'd1; + main_sdram_inti_p0_cas_n <= 1'd1; + if (main_sdram_phaseinjector0_command_issue_re) begin + main_sdram_inti_p0_cs_n <= {1{(~main_sdram_phaseinjector0_command_storage[0])}}; + main_sdram_inti_p0_we_n <= (~main_sdram_phaseinjector0_command_storage[1]); + main_sdram_inti_p0_cas_n <= (~main_sdram_phaseinjector0_command_storage[2]); + main_sdram_inti_p0_ras_n <= (~main_sdram_phaseinjector0_command_storage[3]); + end else begin + main_sdram_inti_p0_cs_n <= {1{1'd1}}; + main_sdram_inti_p0_we_n <= 1'd1; + main_sdram_inti_p0_cas_n <= 1'd1; + main_sdram_inti_p0_ras_n <= 1'd1; + end +end +assign main_sdram_inti_p0_address = main_sdram_phaseinjector0_address_storage; +assign main_sdram_inti_p0_bank = main_sdram_phaseinjector0_baddress_storage; +assign main_sdram_inti_p0_wrdata_en = (main_sdram_phaseinjector0_command_issue_re & main_sdram_phaseinjector0_command_storage[4]); +assign main_sdram_inti_p0_rddata_en = (main_sdram_phaseinjector0_command_issue_re & main_sdram_phaseinjector0_command_storage[5]); +assign main_sdram_inti_p0_wrdata = main_sdram_phaseinjector0_wrdata_storage; +assign main_sdram_inti_p0_wrdata_mask = 1'd0; +always @(*) begin + main_sdram_inti_p1_cs_n <= 1'd1; + main_sdram_inti_p1_ras_n <= 1'd1; + main_sdram_inti_p1_we_n <= 1'd1; + main_sdram_inti_p1_cas_n <= 1'd1; + if (main_sdram_phaseinjector1_command_issue_re) begin + main_sdram_inti_p1_cs_n <= {1{(~main_sdram_phaseinjector1_command_storage[0])}}; + main_sdram_inti_p1_we_n <= (~main_sdram_phaseinjector1_command_storage[1]); + main_sdram_inti_p1_cas_n <= (~main_sdram_phaseinjector1_command_storage[2]); + main_sdram_inti_p1_ras_n <= (~main_sdram_phaseinjector1_command_storage[3]); + end else begin + main_sdram_inti_p1_cs_n <= {1{1'd1}}; + main_sdram_inti_p1_we_n <= 1'd1; + main_sdram_inti_p1_cas_n <= 1'd1; + main_sdram_inti_p1_ras_n <= 1'd1; + end +end +assign main_sdram_inti_p1_address = main_sdram_phaseinjector1_address_storage; +assign main_sdram_inti_p1_bank = main_sdram_phaseinjector1_baddress_storage; +assign main_sdram_inti_p1_wrdata_en = (main_sdram_phaseinjector1_command_issue_re & main_sdram_phaseinjector1_command_storage[4]); +assign main_sdram_inti_p1_rddata_en = (main_sdram_phaseinjector1_command_issue_re & main_sdram_phaseinjector1_command_storage[5]); +assign main_sdram_inti_p1_wrdata = main_sdram_phaseinjector1_wrdata_storage; +assign main_sdram_inti_p1_wrdata_mask = 1'd0; +always @(*) begin + main_sdram_inti_p2_cs_n <= 1'd1; + main_sdram_inti_p2_ras_n <= 1'd1; + main_sdram_inti_p2_we_n <= 1'd1; + main_sdram_inti_p2_cas_n <= 1'd1; + if (main_sdram_phaseinjector2_command_issue_re) begin + main_sdram_inti_p2_cs_n <= {1{(~main_sdram_phaseinjector2_command_storage[0])}}; + main_sdram_inti_p2_we_n <= (~main_sdram_phaseinjector2_command_storage[1]); + main_sdram_inti_p2_cas_n <= (~main_sdram_phaseinjector2_command_storage[2]); + main_sdram_inti_p2_ras_n <= (~main_sdram_phaseinjector2_command_storage[3]); + end else begin + main_sdram_inti_p2_cs_n <= {1{1'd1}}; + main_sdram_inti_p2_we_n <= 1'd1; + main_sdram_inti_p2_cas_n <= 1'd1; + main_sdram_inti_p2_ras_n <= 1'd1; + end +end +assign main_sdram_inti_p2_address = main_sdram_phaseinjector2_address_storage; +assign main_sdram_inti_p2_bank = main_sdram_phaseinjector2_baddress_storage; +assign main_sdram_inti_p2_wrdata_en = (main_sdram_phaseinjector2_command_issue_re & main_sdram_phaseinjector2_command_storage[4]); +assign main_sdram_inti_p2_rddata_en = (main_sdram_phaseinjector2_command_issue_re & main_sdram_phaseinjector2_command_storage[5]); +assign main_sdram_inti_p2_wrdata = main_sdram_phaseinjector2_wrdata_storage; +assign main_sdram_inti_p2_wrdata_mask = 1'd0; +always @(*) begin + main_sdram_inti_p3_cs_n <= 1'd1; + main_sdram_inti_p3_ras_n <= 1'd1; + main_sdram_inti_p3_we_n <= 1'd1; + main_sdram_inti_p3_cas_n <= 1'd1; + if (main_sdram_phaseinjector3_command_issue_re) begin + main_sdram_inti_p3_cs_n <= {1{(~main_sdram_phaseinjector3_command_storage[0])}}; + main_sdram_inti_p3_we_n <= (~main_sdram_phaseinjector3_command_storage[1]); + main_sdram_inti_p3_cas_n <= (~main_sdram_phaseinjector3_command_storage[2]); + main_sdram_inti_p3_ras_n <= (~main_sdram_phaseinjector3_command_storage[3]); + end else begin + main_sdram_inti_p3_cs_n <= {1{1'd1}}; + main_sdram_inti_p3_we_n <= 1'd1; + main_sdram_inti_p3_cas_n <= 1'd1; + main_sdram_inti_p3_ras_n <= 1'd1; + end +end +assign main_sdram_inti_p3_address = main_sdram_phaseinjector3_address_storage; +assign main_sdram_inti_p3_bank = main_sdram_phaseinjector3_baddress_storage; +assign main_sdram_inti_p3_wrdata_en = (main_sdram_phaseinjector3_command_issue_re & main_sdram_phaseinjector3_command_storage[4]); +assign main_sdram_inti_p3_rddata_en = (main_sdram_phaseinjector3_command_issue_re & main_sdram_phaseinjector3_command_storage[5]); +assign main_sdram_inti_p3_wrdata = main_sdram_phaseinjector3_wrdata_storage; +assign main_sdram_inti_p3_wrdata_mask = 1'd0; +assign main_sdram_bankmachine0_req_valid = main_sdram_interface_bank0_valid; +assign main_sdram_interface_bank0_ready = main_sdram_bankmachine0_req_ready; +assign main_sdram_bankmachine0_req_we = main_sdram_interface_bank0_we; +assign main_sdram_bankmachine0_req_addr = main_sdram_interface_bank0_addr; +assign main_sdram_interface_bank0_lock = main_sdram_bankmachine0_req_lock; +assign main_sdram_interface_bank0_wdata_ready = main_sdram_bankmachine0_req_wdata_ready; +assign main_sdram_interface_bank0_rdata_valid = main_sdram_bankmachine0_req_rdata_valid; +assign main_sdram_bankmachine1_req_valid = main_sdram_interface_bank1_valid; +assign main_sdram_interface_bank1_ready = main_sdram_bankmachine1_req_ready; +assign main_sdram_bankmachine1_req_we = main_sdram_interface_bank1_we; +assign main_sdram_bankmachine1_req_addr = main_sdram_interface_bank1_addr; +assign main_sdram_interface_bank1_lock = main_sdram_bankmachine1_req_lock; +assign main_sdram_interface_bank1_wdata_ready = main_sdram_bankmachine1_req_wdata_ready; +assign main_sdram_interface_bank1_rdata_valid = main_sdram_bankmachine1_req_rdata_valid; +assign main_sdram_bankmachine2_req_valid = main_sdram_interface_bank2_valid; +assign main_sdram_interface_bank2_ready = main_sdram_bankmachine2_req_ready; +assign main_sdram_bankmachine2_req_we = main_sdram_interface_bank2_we; +assign main_sdram_bankmachine2_req_addr = main_sdram_interface_bank2_addr; +assign main_sdram_interface_bank2_lock = main_sdram_bankmachine2_req_lock; +assign main_sdram_interface_bank2_wdata_ready = main_sdram_bankmachine2_req_wdata_ready; +assign main_sdram_interface_bank2_rdata_valid = main_sdram_bankmachine2_req_rdata_valid; +assign main_sdram_bankmachine3_req_valid = main_sdram_interface_bank3_valid; +assign main_sdram_interface_bank3_ready = main_sdram_bankmachine3_req_ready; +assign main_sdram_bankmachine3_req_we = main_sdram_interface_bank3_we; +assign main_sdram_bankmachine3_req_addr = main_sdram_interface_bank3_addr; +assign main_sdram_interface_bank3_lock = main_sdram_bankmachine3_req_lock; +assign main_sdram_interface_bank3_wdata_ready = main_sdram_bankmachine3_req_wdata_ready; +assign main_sdram_interface_bank3_rdata_valid = main_sdram_bankmachine3_req_rdata_valid; +assign main_sdram_bankmachine4_req_valid = main_sdram_interface_bank4_valid; +assign main_sdram_interface_bank4_ready = main_sdram_bankmachine4_req_ready; +assign main_sdram_bankmachine4_req_we = main_sdram_interface_bank4_we; +assign main_sdram_bankmachine4_req_addr = main_sdram_interface_bank4_addr; +assign main_sdram_interface_bank4_lock = main_sdram_bankmachine4_req_lock; +assign main_sdram_interface_bank4_wdata_ready = main_sdram_bankmachine4_req_wdata_ready; +assign main_sdram_interface_bank4_rdata_valid = main_sdram_bankmachine4_req_rdata_valid; +assign main_sdram_bankmachine5_req_valid = main_sdram_interface_bank5_valid; +assign main_sdram_interface_bank5_ready = main_sdram_bankmachine5_req_ready; +assign main_sdram_bankmachine5_req_we = main_sdram_interface_bank5_we; +assign main_sdram_bankmachine5_req_addr = main_sdram_interface_bank5_addr; +assign main_sdram_interface_bank5_lock = main_sdram_bankmachine5_req_lock; +assign main_sdram_interface_bank5_wdata_ready = main_sdram_bankmachine5_req_wdata_ready; +assign main_sdram_interface_bank5_rdata_valid = main_sdram_bankmachine5_req_rdata_valid; +assign main_sdram_bankmachine6_req_valid = main_sdram_interface_bank6_valid; +assign main_sdram_interface_bank6_ready = main_sdram_bankmachine6_req_ready; +assign main_sdram_bankmachine6_req_we = main_sdram_interface_bank6_we; +assign main_sdram_bankmachine6_req_addr = main_sdram_interface_bank6_addr; +assign main_sdram_interface_bank6_lock = main_sdram_bankmachine6_req_lock; +assign main_sdram_interface_bank6_wdata_ready = main_sdram_bankmachine6_req_wdata_ready; +assign main_sdram_interface_bank6_rdata_valid = main_sdram_bankmachine6_req_rdata_valid; +assign main_sdram_bankmachine7_req_valid = main_sdram_interface_bank7_valid; +assign main_sdram_interface_bank7_ready = main_sdram_bankmachine7_req_ready; +assign main_sdram_bankmachine7_req_we = main_sdram_interface_bank7_we; +assign main_sdram_bankmachine7_req_addr = main_sdram_interface_bank7_addr; +assign main_sdram_interface_bank7_lock = main_sdram_bankmachine7_req_lock; +assign main_sdram_interface_bank7_wdata_ready = main_sdram_bankmachine7_req_wdata_ready; +assign main_sdram_interface_bank7_rdata_valid = main_sdram_bankmachine7_req_rdata_valid; +assign main_sdram_timer_wait = (~main_sdram_timer_done0); +assign main_sdram_postponer_req_i = main_sdram_timer_done0; +assign main_sdram_wants_refresh = main_sdram_postponer_req_o; +assign main_sdram_wants_zqcs = main_sdram_zqcs_timer_done0; +assign main_sdram_zqcs_timer_wait = (~main_sdram_zqcs_executer_done); +assign main_sdram_timer_done1 = (main_sdram_timer_count1 == 1'd0); +assign main_sdram_timer_done0 = main_sdram_timer_done1; +assign main_sdram_timer_count0 = main_sdram_timer_count1; +assign main_sdram_sequencer_start1 = (main_sdram_sequencer_start0 | (main_sdram_sequencer_count != 1'd0)); +assign main_sdram_sequencer_done0 = (main_sdram_sequencer_done1 & (main_sdram_sequencer_count == 1'd0)); +assign main_sdram_zqcs_timer_done1 = (main_sdram_zqcs_timer_count1 == 1'd0); +assign main_sdram_zqcs_timer_done0 = main_sdram_zqcs_timer_done1; +assign main_sdram_zqcs_timer_count0 = main_sdram_zqcs_timer_count1; +always @(*) begin + main_sdram_zqcs_executer_start <= 1'd0; + main_sdram_cmd_last <= 1'd0; + main_sdram_sequencer_start0 <= 1'd0; + builder_refresher_next_state <= 2'd0; + main_sdram_cmd_valid <= 1'd0; + builder_refresher_next_state <= builder_refresher_state; + case (builder_refresher_state) + 1'd1: begin + main_sdram_cmd_valid <= 1'd1; + if (main_sdram_cmd_ready) begin + main_sdram_sequencer_start0 <= 1'd1; + builder_refresher_next_state <= 2'd2; + end + end + 2'd2: begin + main_sdram_cmd_valid <= 1'd1; + if (main_sdram_sequencer_done0) begin + if (main_sdram_wants_zqcs) begin + main_sdram_zqcs_executer_start <= 1'd1; + builder_refresher_next_state <= 2'd3; + end else begin + main_sdram_cmd_valid <= 1'd0; + main_sdram_cmd_last <= 1'd1; + builder_refresher_next_state <= 1'd0; + end + end + end + 2'd3: begin + main_sdram_cmd_valid <= 1'd1; + if (main_sdram_zqcs_executer_done) begin + main_sdram_cmd_valid <= 1'd0; + main_sdram_cmd_last <= 1'd1; + builder_refresher_next_state <= 1'd0; + end + end + default: begin + if (1'd1) begin + if (main_sdram_wants_refresh) begin + builder_refresher_next_state <= 1'd1; + end + end + end + endcase +end +assign main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine0_req_valid; +assign main_sdram_bankmachine0_req_ready = main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready; +assign main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine0_req_we; +assign main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine0_req_addr; +assign main_sdram_bankmachine0_cmd_buffer_sink_valid = main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid; +assign main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine0_cmd_buffer_sink_ready; +assign main_sdram_bankmachine0_cmd_buffer_sink_first = main_sdram_bankmachine0_cmd_buffer_lookahead_source_first; +assign main_sdram_bankmachine0_cmd_buffer_sink_last = main_sdram_bankmachine0_cmd_buffer_lookahead_source_last; +assign main_sdram_bankmachine0_cmd_buffer_sink_payload_we = main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we; +assign main_sdram_bankmachine0_cmd_buffer_sink_payload_addr = main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr; +assign main_sdram_bankmachine0_cmd_buffer_source_ready = (main_sdram_bankmachine0_req_wdata_ready | main_sdram_bankmachine0_req_rdata_valid); +assign main_sdram_bankmachine0_req_lock = (main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine0_cmd_buffer_source_valid); +assign main_sdram_bankmachine0_row_hit = (main_sdram_bankmachine0_row == main_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7]); +assign main_sdram_bankmachine0_cmd_payload_ba = 1'd0; +always @(*) begin + main_sdram_bankmachine0_cmd_payload_a <= 14'd0; + if (main_sdram_bankmachine0_row_col_n_addr_sel) begin + main_sdram_bankmachine0_cmd_payload_a <= main_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7]; + end else begin + main_sdram_bankmachine0_cmd_payload_a <= ((main_sdram_bankmachine0_auto_precharge <<< 4'd10) | {main_sdram_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_sdram_bankmachine0_twtpcon_valid = ((main_sdram_bankmachine0_cmd_valid & main_sdram_bankmachine0_cmd_ready) & main_sdram_bankmachine0_cmd_payload_is_write); +assign main_sdram_bankmachine0_trccon_valid = ((main_sdram_bankmachine0_cmd_valid & main_sdram_bankmachine0_cmd_ready) & main_sdram_bankmachine0_row_open); +assign main_sdram_bankmachine0_trascon_valid = ((main_sdram_bankmachine0_cmd_valid & main_sdram_bankmachine0_cmd_ready) & main_sdram_bankmachine0_row_open); +always @(*) begin + main_sdram_bankmachine0_auto_precharge <= 1'd0; + if ((main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine0_cmd_buffer_source_valid)) begin + if ((main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != main_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin + main_sdram_bankmachine0_auto_precharge <= (main_sdram_bankmachine0_row_close == 1'd0); + end + end +end +assign main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last, main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first, main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout; +assign main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable; +assign main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid; +assign main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first; +assign main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last; +assign main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we; +assign main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr; +assign main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable; +assign main_sdram_bankmachine0_cmd_buffer_lookahead_source_first = main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first; +assign main_sdram_bankmachine0_cmd_buffer_lookahead_source_last = main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last; +assign main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready; +always @(*) begin + main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 3'd0; + if (main_sdram_bankmachine0_cmd_buffer_lookahead_replace) begin + main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine0_cmd_buffer_lookahead_produce - 1'd1); + end else begin + main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine0_cmd_buffer_lookahead_produce; + end +end +assign main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din; +assign main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | main_sdram_bankmachine0_cmd_buffer_lookahead_replace)); +assign main_sdram_bankmachine0_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re); +assign main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine0_cmd_buffer_lookahead_consume; +assign main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r; +assign main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (main_sdram_bankmachine0_cmd_buffer_lookahead_level != 4'd8); +assign main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (main_sdram_bankmachine0_cmd_buffer_lookahead_level != 1'd0); +assign main_sdram_bankmachine0_cmd_buffer_pipe_ce = (main_sdram_bankmachine0_cmd_buffer_source_ready | (~main_sdram_bankmachine0_cmd_buffer_valid_n)); +assign main_sdram_bankmachine0_cmd_buffer_sink_ready = main_sdram_bankmachine0_cmd_buffer_pipe_ce; +assign main_sdram_bankmachine0_cmd_buffer_source_valid = main_sdram_bankmachine0_cmd_buffer_valid_n; +assign main_sdram_bankmachine0_cmd_buffer_busy = (1'd0 | main_sdram_bankmachine0_cmd_buffer_valid_n); +assign main_sdram_bankmachine0_cmd_buffer_source_first = main_sdram_bankmachine0_cmd_buffer_first_n; +assign main_sdram_bankmachine0_cmd_buffer_source_last = main_sdram_bankmachine0_cmd_buffer_last_n; +always @(*) begin + main_sdram_bankmachine0_row_col_n_addr_sel <= 1'd0; + main_sdram_bankmachine0_refresh_gnt <= 1'd0; + main_sdram_bankmachine0_cmd_valid <= 1'd0; + main_sdram_bankmachine0_cmd_payload_cas <= 1'd0; + main_sdram_bankmachine0_cmd_payload_ras <= 1'd0; + main_sdram_bankmachine0_cmd_payload_we <= 1'd0; + main_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd0; + main_sdram_bankmachine0_row_open <= 1'd0; + main_sdram_bankmachine0_cmd_payload_is_read <= 1'd0; + main_sdram_bankmachine0_row_close <= 1'd0; + main_sdram_bankmachine0_cmd_payload_is_write <= 1'd0; + builder_bankmachine0_next_state <= 3'd0; + main_sdram_bankmachine0_req_wdata_ready <= 1'd0; + main_sdram_bankmachine0_req_rdata_valid <= 1'd0; + builder_bankmachine0_next_state <= builder_bankmachine0_state; + case (builder_bankmachine0_state) + 1'd1: begin + if ((main_sdram_bankmachine0_twtpcon_ready & main_sdram_bankmachine0_trascon_ready)) begin + main_sdram_bankmachine0_cmd_valid <= 1'd1; + if (main_sdram_bankmachine0_cmd_ready) begin + builder_bankmachine0_next_state <= 3'd5; + end + main_sdram_bankmachine0_cmd_payload_ras <= 1'd1; + main_sdram_bankmachine0_cmd_payload_we <= 1'd1; + main_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1; + end + main_sdram_bankmachine0_row_close <= 1'd1; + end + 2'd2: begin + if ((main_sdram_bankmachine0_twtpcon_ready & main_sdram_bankmachine0_trascon_ready)) begin + builder_bankmachine0_next_state <= 3'd5; + end + main_sdram_bankmachine0_row_close <= 1'd1; + end + 2'd3: begin + if (main_sdram_bankmachine0_trccon_ready) begin + main_sdram_bankmachine0_row_col_n_addr_sel <= 1'd1; + main_sdram_bankmachine0_row_open <= 1'd1; + main_sdram_bankmachine0_cmd_valid <= 1'd1; + main_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1; + if (main_sdram_bankmachine0_cmd_ready) begin + builder_bankmachine0_next_state <= 3'd6; + end + main_sdram_bankmachine0_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + if (main_sdram_bankmachine0_twtpcon_ready) begin + main_sdram_bankmachine0_refresh_gnt <= 1'd1; + end + main_sdram_bankmachine0_row_close <= 1'd1; + main_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1; + if ((~main_sdram_bankmachine0_refresh_req)) begin + builder_bankmachine0_next_state <= 1'd0; + end + end + 3'd5: begin + builder_bankmachine0_next_state <= 2'd3; + end + 3'd6: begin + builder_bankmachine0_next_state <= 1'd0; + end + default: begin + if (main_sdram_bankmachine0_refresh_req) begin + builder_bankmachine0_next_state <= 3'd4; + end else begin + if (main_sdram_bankmachine0_cmd_buffer_source_valid) begin + if (main_sdram_bankmachine0_row_opened) begin + if (main_sdram_bankmachine0_row_hit) begin + main_sdram_bankmachine0_cmd_valid <= 1'd1; + if (main_sdram_bankmachine0_cmd_buffer_source_payload_we) begin + main_sdram_bankmachine0_req_wdata_ready <= main_sdram_bankmachine0_cmd_ready; + main_sdram_bankmachine0_cmd_payload_is_write <= 1'd1; + main_sdram_bankmachine0_cmd_payload_we <= 1'd1; + end else begin + main_sdram_bankmachine0_req_rdata_valid <= main_sdram_bankmachine0_cmd_ready; + main_sdram_bankmachine0_cmd_payload_is_read <= 1'd1; + end + main_sdram_bankmachine0_cmd_payload_cas <= 1'd1; + if ((main_sdram_bankmachine0_cmd_ready & main_sdram_bankmachine0_auto_precharge)) begin + builder_bankmachine0_next_state <= 2'd2; + end + end else begin + builder_bankmachine0_next_state <= 1'd1; + end + end else begin + builder_bankmachine0_next_state <= 2'd3; + end + end + end + end + endcase +end +assign main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine1_req_valid; +assign main_sdram_bankmachine1_req_ready = main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready; +assign main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine1_req_we; +assign main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine1_req_addr; +assign main_sdram_bankmachine1_cmd_buffer_sink_valid = main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid; +assign main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine1_cmd_buffer_sink_ready; +assign main_sdram_bankmachine1_cmd_buffer_sink_first = main_sdram_bankmachine1_cmd_buffer_lookahead_source_first; +assign main_sdram_bankmachine1_cmd_buffer_sink_last = main_sdram_bankmachine1_cmd_buffer_lookahead_source_last; +assign main_sdram_bankmachine1_cmd_buffer_sink_payload_we = main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we; +assign main_sdram_bankmachine1_cmd_buffer_sink_payload_addr = main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr; +assign main_sdram_bankmachine1_cmd_buffer_source_ready = (main_sdram_bankmachine1_req_wdata_ready | main_sdram_bankmachine1_req_rdata_valid); +assign main_sdram_bankmachine1_req_lock = (main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine1_cmd_buffer_source_valid); +assign main_sdram_bankmachine1_row_hit = (main_sdram_bankmachine1_row == main_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7]); +assign main_sdram_bankmachine1_cmd_payload_ba = 1'd1; +always @(*) begin + main_sdram_bankmachine1_cmd_payload_a <= 14'd0; + if (main_sdram_bankmachine1_row_col_n_addr_sel) begin + main_sdram_bankmachine1_cmd_payload_a <= main_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7]; + end else begin + main_sdram_bankmachine1_cmd_payload_a <= ((main_sdram_bankmachine1_auto_precharge <<< 4'd10) | {main_sdram_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_sdram_bankmachine1_twtpcon_valid = ((main_sdram_bankmachine1_cmd_valid & main_sdram_bankmachine1_cmd_ready) & main_sdram_bankmachine1_cmd_payload_is_write); +assign main_sdram_bankmachine1_trccon_valid = ((main_sdram_bankmachine1_cmd_valid & main_sdram_bankmachine1_cmd_ready) & main_sdram_bankmachine1_row_open); +assign main_sdram_bankmachine1_trascon_valid = ((main_sdram_bankmachine1_cmd_valid & main_sdram_bankmachine1_cmd_ready) & main_sdram_bankmachine1_row_open); +always @(*) begin + main_sdram_bankmachine1_auto_precharge <= 1'd0; + if ((main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine1_cmd_buffer_source_valid)) begin + if ((main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != main_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin + main_sdram_bankmachine1_auto_precharge <= (main_sdram_bankmachine1_row_close == 1'd0); + end + end +end +assign main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last, main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first, main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout; +assign main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable; +assign main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid; +assign main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first; +assign main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last; +assign main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we; +assign main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr; +assign main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable; +assign main_sdram_bankmachine1_cmd_buffer_lookahead_source_first = main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first; +assign main_sdram_bankmachine1_cmd_buffer_lookahead_source_last = main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last; +assign main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready; +always @(*) begin + main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 3'd0; + if (main_sdram_bankmachine1_cmd_buffer_lookahead_replace) begin + main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine1_cmd_buffer_lookahead_produce - 1'd1); + end else begin + main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine1_cmd_buffer_lookahead_produce; + end +end +assign main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din; +assign main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | main_sdram_bankmachine1_cmd_buffer_lookahead_replace)); +assign main_sdram_bankmachine1_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re); +assign main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine1_cmd_buffer_lookahead_consume; +assign main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r; +assign main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (main_sdram_bankmachine1_cmd_buffer_lookahead_level != 4'd8); +assign main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (main_sdram_bankmachine1_cmd_buffer_lookahead_level != 1'd0); +assign main_sdram_bankmachine1_cmd_buffer_pipe_ce = (main_sdram_bankmachine1_cmd_buffer_source_ready | (~main_sdram_bankmachine1_cmd_buffer_valid_n)); +assign main_sdram_bankmachine1_cmd_buffer_sink_ready = main_sdram_bankmachine1_cmd_buffer_pipe_ce; +assign main_sdram_bankmachine1_cmd_buffer_source_valid = main_sdram_bankmachine1_cmd_buffer_valid_n; +assign main_sdram_bankmachine1_cmd_buffer_busy = (1'd0 | main_sdram_bankmachine1_cmd_buffer_valid_n); +assign main_sdram_bankmachine1_cmd_buffer_source_first = main_sdram_bankmachine1_cmd_buffer_first_n; +assign main_sdram_bankmachine1_cmd_buffer_source_last = main_sdram_bankmachine1_cmd_buffer_last_n; +always @(*) begin + main_sdram_bankmachine1_cmd_payload_we <= 1'd0; + main_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd0; + main_sdram_bankmachine1_row_open <= 1'd0; + main_sdram_bankmachine1_cmd_payload_is_read <= 1'd0; + main_sdram_bankmachine1_row_close <= 1'd0; + main_sdram_bankmachine1_cmd_payload_is_write <= 1'd0; + main_sdram_bankmachine1_req_wdata_ready <= 1'd0; + main_sdram_bankmachine1_req_rdata_valid <= 1'd0; + main_sdram_bankmachine1_row_col_n_addr_sel <= 1'd0; + main_sdram_bankmachine1_refresh_gnt <= 1'd0; + main_sdram_bankmachine1_cmd_valid <= 1'd0; + builder_bankmachine1_next_state <= 3'd0; + main_sdram_bankmachine1_cmd_payload_cas <= 1'd0; + main_sdram_bankmachine1_cmd_payload_ras <= 1'd0; + builder_bankmachine1_next_state <= builder_bankmachine1_state; + case (builder_bankmachine1_state) + 1'd1: begin + if ((main_sdram_bankmachine1_twtpcon_ready & main_sdram_bankmachine1_trascon_ready)) begin + main_sdram_bankmachine1_cmd_valid <= 1'd1; + if (main_sdram_bankmachine1_cmd_ready) begin + builder_bankmachine1_next_state <= 3'd5; + end + main_sdram_bankmachine1_cmd_payload_ras <= 1'd1; + main_sdram_bankmachine1_cmd_payload_we <= 1'd1; + main_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1; + end + main_sdram_bankmachine1_row_close <= 1'd1; + end + 2'd2: begin + if ((main_sdram_bankmachine1_twtpcon_ready & main_sdram_bankmachine1_trascon_ready)) begin + builder_bankmachine1_next_state <= 3'd5; + end + main_sdram_bankmachine1_row_close <= 1'd1; + end + 2'd3: begin + if (main_sdram_bankmachine1_trccon_ready) begin + main_sdram_bankmachine1_row_col_n_addr_sel <= 1'd1; + main_sdram_bankmachine1_row_open <= 1'd1; + main_sdram_bankmachine1_cmd_valid <= 1'd1; + main_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1; + if (main_sdram_bankmachine1_cmd_ready) begin + builder_bankmachine1_next_state <= 3'd6; + end + main_sdram_bankmachine1_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + if (main_sdram_bankmachine1_twtpcon_ready) begin + main_sdram_bankmachine1_refresh_gnt <= 1'd1; + end + main_sdram_bankmachine1_row_close <= 1'd1; + main_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1; + if ((~main_sdram_bankmachine1_refresh_req)) begin + builder_bankmachine1_next_state <= 1'd0; + end + end + 3'd5: begin + builder_bankmachine1_next_state <= 2'd3; + end + 3'd6: begin + builder_bankmachine1_next_state <= 1'd0; + end + default: begin + if (main_sdram_bankmachine1_refresh_req) begin + builder_bankmachine1_next_state <= 3'd4; + end else begin + if (main_sdram_bankmachine1_cmd_buffer_source_valid) begin + if (main_sdram_bankmachine1_row_opened) begin + if (main_sdram_bankmachine1_row_hit) begin + main_sdram_bankmachine1_cmd_valid <= 1'd1; + if (main_sdram_bankmachine1_cmd_buffer_source_payload_we) begin + main_sdram_bankmachine1_req_wdata_ready <= main_sdram_bankmachine1_cmd_ready; + main_sdram_bankmachine1_cmd_payload_is_write <= 1'd1; + main_sdram_bankmachine1_cmd_payload_we <= 1'd1; + end else begin + main_sdram_bankmachine1_req_rdata_valid <= main_sdram_bankmachine1_cmd_ready; + main_sdram_bankmachine1_cmd_payload_is_read <= 1'd1; + end + main_sdram_bankmachine1_cmd_payload_cas <= 1'd1; + if ((main_sdram_bankmachine1_cmd_ready & main_sdram_bankmachine1_auto_precharge)) begin + builder_bankmachine1_next_state <= 2'd2; + end + end else begin + builder_bankmachine1_next_state <= 1'd1; + end + end else begin + builder_bankmachine1_next_state <= 2'd3; + end + end + end + end + endcase +end +assign main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine2_req_valid; +assign main_sdram_bankmachine2_req_ready = main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready; +assign main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine2_req_we; +assign main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine2_req_addr; +assign main_sdram_bankmachine2_cmd_buffer_sink_valid = main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid; +assign main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine2_cmd_buffer_sink_ready; +assign main_sdram_bankmachine2_cmd_buffer_sink_first = main_sdram_bankmachine2_cmd_buffer_lookahead_source_first; +assign main_sdram_bankmachine2_cmd_buffer_sink_last = main_sdram_bankmachine2_cmd_buffer_lookahead_source_last; +assign main_sdram_bankmachine2_cmd_buffer_sink_payload_we = main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we; +assign main_sdram_bankmachine2_cmd_buffer_sink_payload_addr = main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr; +assign main_sdram_bankmachine2_cmd_buffer_source_ready = (main_sdram_bankmachine2_req_wdata_ready | main_sdram_bankmachine2_req_rdata_valid); +assign main_sdram_bankmachine2_req_lock = (main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine2_cmd_buffer_source_valid); +assign main_sdram_bankmachine2_row_hit = (main_sdram_bankmachine2_row == main_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7]); +assign main_sdram_bankmachine2_cmd_payload_ba = 2'd2; +always @(*) begin + main_sdram_bankmachine2_cmd_payload_a <= 14'd0; + if (main_sdram_bankmachine2_row_col_n_addr_sel) begin + main_sdram_bankmachine2_cmd_payload_a <= main_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7]; + end else begin + main_sdram_bankmachine2_cmd_payload_a <= ((main_sdram_bankmachine2_auto_precharge <<< 4'd10) | {main_sdram_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_sdram_bankmachine2_twtpcon_valid = ((main_sdram_bankmachine2_cmd_valid & main_sdram_bankmachine2_cmd_ready) & main_sdram_bankmachine2_cmd_payload_is_write); +assign main_sdram_bankmachine2_trccon_valid = ((main_sdram_bankmachine2_cmd_valid & main_sdram_bankmachine2_cmd_ready) & main_sdram_bankmachine2_row_open); +assign main_sdram_bankmachine2_trascon_valid = ((main_sdram_bankmachine2_cmd_valid & main_sdram_bankmachine2_cmd_ready) & main_sdram_bankmachine2_row_open); +always @(*) begin + main_sdram_bankmachine2_auto_precharge <= 1'd0; + if ((main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine2_cmd_buffer_source_valid)) begin + if ((main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != main_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin + main_sdram_bankmachine2_auto_precharge <= (main_sdram_bankmachine2_row_close == 1'd0); + end + end +end +assign main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last, main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first, main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout; +assign main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable; +assign main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid; +assign main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first; +assign main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last; +assign main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we; +assign main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr; +assign main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable; +assign main_sdram_bankmachine2_cmd_buffer_lookahead_source_first = main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first; +assign main_sdram_bankmachine2_cmd_buffer_lookahead_source_last = main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last; +assign main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready; +always @(*) begin + main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 3'd0; + if (main_sdram_bankmachine2_cmd_buffer_lookahead_replace) begin + main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine2_cmd_buffer_lookahead_produce - 1'd1); + end else begin + main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine2_cmd_buffer_lookahead_produce; + end +end +assign main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din; +assign main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | main_sdram_bankmachine2_cmd_buffer_lookahead_replace)); +assign main_sdram_bankmachine2_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re); +assign main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine2_cmd_buffer_lookahead_consume; +assign main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r; +assign main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (main_sdram_bankmachine2_cmd_buffer_lookahead_level != 4'd8); +assign main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (main_sdram_bankmachine2_cmd_buffer_lookahead_level != 1'd0); +assign main_sdram_bankmachine2_cmd_buffer_pipe_ce = (main_sdram_bankmachine2_cmd_buffer_source_ready | (~main_sdram_bankmachine2_cmd_buffer_valid_n)); +assign main_sdram_bankmachine2_cmd_buffer_sink_ready = main_sdram_bankmachine2_cmd_buffer_pipe_ce; +assign main_sdram_bankmachine2_cmd_buffer_source_valid = main_sdram_bankmachine2_cmd_buffer_valid_n; +assign main_sdram_bankmachine2_cmd_buffer_busy = (1'd0 | main_sdram_bankmachine2_cmd_buffer_valid_n); +assign main_sdram_bankmachine2_cmd_buffer_source_first = main_sdram_bankmachine2_cmd_buffer_first_n; +assign main_sdram_bankmachine2_cmd_buffer_source_last = main_sdram_bankmachine2_cmd_buffer_last_n; +always @(*) begin + main_sdram_bankmachine2_cmd_payload_cas <= 1'd0; + main_sdram_bankmachine2_cmd_payload_ras <= 1'd0; + main_sdram_bankmachine2_cmd_payload_we <= 1'd0; + main_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd0; + main_sdram_bankmachine2_row_open <= 1'd0; + main_sdram_bankmachine2_cmd_payload_is_read <= 1'd0; + main_sdram_bankmachine2_row_close <= 1'd0; + main_sdram_bankmachine2_cmd_payload_is_write <= 1'd0; + builder_bankmachine2_next_state <= 3'd0; + main_sdram_bankmachine2_req_wdata_ready <= 1'd0; + main_sdram_bankmachine2_req_rdata_valid <= 1'd0; + main_sdram_bankmachine2_row_col_n_addr_sel <= 1'd0; + main_sdram_bankmachine2_refresh_gnt <= 1'd0; + main_sdram_bankmachine2_cmd_valid <= 1'd0; + builder_bankmachine2_next_state <= builder_bankmachine2_state; + case (builder_bankmachine2_state) + 1'd1: begin + if ((main_sdram_bankmachine2_twtpcon_ready & main_sdram_bankmachine2_trascon_ready)) begin + main_sdram_bankmachine2_cmd_valid <= 1'd1; + if (main_sdram_bankmachine2_cmd_ready) begin + builder_bankmachine2_next_state <= 3'd5; + end + main_sdram_bankmachine2_cmd_payload_ras <= 1'd1; + main_sdram_bankmachine2_cmd_payload_we <= 1'd1; + main_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1; + end + main_sdram_bankmachine2_row_close <= 1'd1; + end + 2'd2: begin + if ((main_sdram_bankmachine2_twtpcon_ready & main_sdram_bankmachine2_trascon_ready)) begin + builder_bankmachine2_next_state <= 3'd5; + end + main_sdram_bankmachine2_row_close <= 1'd1; + end + 2'd3: begin + if (main_sdram_bankmachine2_trccon_ready) begin + main_sdram_bankmachine2_row_col_n_addr_sel <= 1'd1; + main_sdram_bankmachine2_row_open <= 1'd1; + main_sdram_bankmachine2_cmd_valid <= 1'd1; + main_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1; + if (main_sdram_bankmachine2_cmd_ready) begin + builder_bankmachine2_next_state <= 3'd6; + end + main_sdram_bankmachine2_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + if (main_sdram_bankmachine2_twtpcon_ready) begin + main_sdram_bankmachine2_refresh_gnt <= 1'd1; + end + main_sdram_bankmachine2_row_close <= 1'd1; + main_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1; + if ((~main_sdram_bankmachine2_refresh_req)) begin + builder_bankmachine2_next_state <= 1'd0; + end + end + 3'd5: begin + builder_bankmachine2_next_state <= 2'd3; + end + 3'd6: begin + builder_bankmachine2_next_state <= 1'd0; + end + default: begin + if (main_sdram_bankmachine2_refresh_req) begin + builder_bankmachine2_next_state <= 3'd4; + end else begin + if (main_sdram_bankmachine2_cmd_buffer_source_valid) begin + if (main_sdram_bankmachine2_row_opened) begin + if (main_sdram_bankmachine2_row_hit) begin + main_sdram_bankmachine2_cmd_valid <= 1'd1; + if (main_sdram_bankmachine2_cmd_buffer_source_payload_we) begin + main_sdram_bankmachine2_req_wdata_ready <= main_sdram_bankmachine2_cmd_ready; + main_sdram_bankmachine2_cmd_payload_is_write <= 1'd1; + main_sdram_bankmachine2_cmd_payload_we <= 1'd1; + end else begin + main_sdram_bankmachine2_req_rdata_valid <= main_sdram_bankmachine2_cmd_ready; + main_sdram_bankmachine2_cmd_payload_is_read <= 1'd1; + end + main_sdram_bankmachine2_cmd_payload_cas <= 1'd1; + if ((main_sdram_bankmachine2_cmd_ready & main_sdram_bankmachine2_auto_precharge)) begin + builder_bankmachine2_next_state <= 2'd2; + end + end else begin + builder_bankmachine2_next_state <= 1'd1; + end + end else begin + builder_bankmachine2_next_state <= 2'd3; + end + end + end + end + endcase +end +assign main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine3_req_valid; +assign main_sdram_bankmachine3_req_ready = main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready; +assign main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine3_req_we; +assign main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine3_req_addr; +assign main_sdram_bankmachine3_cmd_buffer_sink_valid = main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid; +assign main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine3_cmd_buffer_sink_ready; +assign main_sdram_bankmachine3_cmd_buffer_sink_first = main_sdram_bankmachine3_cmd_buffer_lookahead_source_first; +assign main_sdram_bankmachine3_cmd_buffer_sink_last = main_sdram_bankmachine3_cmd_buffer_lookahead_source_last; +assign main_sdram_bankmachine3_cmd_buffer_sink_payload_we = main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we; +assign main_sdram_bankmachine3_cmd_buffer_sink_payload_addr = main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr; +assign main_sdram_bankmachine3_cmd_buffer_source_ready = (main_sdram_bankmachine3_req_wdata_ready | main_sdram_bankmachine3_req_rdata_valid); +assign main_sdram_bankmachine3_req_lock = (main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine3_cmd_buffer_source_valid); +assign main_sdram_bankmachine3_row_hit = (main_sdram_bankmachine3_row == main_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7]); +assign main_sdram_bankmachine3_cmd_payload_ba = 2'd3; +always @(*) begin + main_sdram_bankmachine3_cmd_payload_a <= 14'd0; + if (main_sdram_bankmachine3_row_col_n_addr_sel) begin + main_sdram_bankmachine3_cmd_payload_a <= main_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7]; + end else begin + main_sdram_bankmachine3_cmd_payload_a <= ((main_sdram_bankmachine3_auto_precharge <<< 4'd10) | {main_sdram_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_sdram_bankmachine3_twtpcon_valid = ((main_sdram_bankmachine3_cmd_valid & main_sdram_bankmachine3_cmd_ready) & main_sdram_bankmachine3_cmd_payload_is_write); +assign main_sdram_bankmachine3_trccon_valid = ((main_sdram_bankmachine3_cmd_valid & main_sdram_bankmachine3_cmd_ready) & main_sdram_bankmachine3_row_open); +assign main_sdram_bankmachine3_trascon_valid = ((main_sdram_bankmachine3_cmd_valid & main_sdram_bankmachine3_cmd_ready) & main_sdram_bankmachine3_row_open); +always @(*) begin + main_sdram_bankmachine3_auto_precharge <= 1'd0; + if ((main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine3_cmd_buffer_source_valid)) begin + if ((main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != main_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin + main_sdram_bankmachine3_auto_precharge <= (main_sdram_bankmachine3_row_close == 1'd0); + end + end +end +assign main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last, main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first, main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout; +assign main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable; +assign main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid; +assign main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first; +assign main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last; +assign main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we; +assign main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr; +assign main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable; +assign main_sdram_bankmachine3_cmd_buffer_lookahead_source_first = main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first; +assign main_sdram_bankmachine3_cmd_buffer_lookahead_source_last = main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last; +assign main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready; +always @(*) begin + main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 3'd0; + if (main_sdram_bankmachine3_cmd_buffer_lookahead_replace) begin + main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine3_cmd_buffer_lookahead_produce - 1'd1); + end else begin + main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine3_cmd_buffer_lookahead_produce; + end +end +assign main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din; +assign main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | main_sdram_bankmachine3_cmd_buffer_lookahead_replace)); +assign main_sdram_bankmachine3_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re); +assign main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine3_cmd_buffer_lookahead_consume; +assign main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r; +assign main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (main_sdram_bankmachine3_cmd_buffer_lookahead_level != 4'd8); +assign main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (main_sdram_bankmachine3_cmd_buffer_lookahead_level != 1'd0); +assign main_sdram_bankmachine3_cmd_buffer_pipe_ce = (main_sdram_bankmachine3_cmd_buffer_source_ready | (~main_sdram_bankmachine3_cmd_buffer_valid_n)); +assign main_sdram_bankmachine3_cmd_buffer_sink_ready = main_sdram_bankmachine3_cmd_buffer_pipe_ce; +assign main_sdram_bankmachine3_cmd_buffer_source_valid = main_sdram_bankmachine3_cmd_buffer_valid_n; +assign main_sdram_bankmachine3_cmd_buffer_busy = (1'd0 | main_sdram_bankmachine3_cmd_buffer_valid_n); +assign main_sdram_bankmachine3_cmd_buffer_source_first = main_sdram_bankmachine3_cmd_buffer_first_n; +assign main_sdram_bankmachine3_cmd_buffer_source_last = main_sdram_bankmachine3_cmd_buffer_last_n; +always @(*) begin + main_sdram_bankmachine3_req_wdata_ready <= 1'd0; + main_sdram_bankmachine3_req_rdata_valid <= 1'd0; + main_sdram_bankmachine3_row_col_n_addr_sel <= 1'd0; + main_sdram_bankmachine3_refresh_gnt <= 1'd0; + main_sdram_bankmachine3_cmd_valid <= 1'd0; + builder_bankmachine3_next_state <= 3'd0; + main_sdram_bankmachine3_cmd_payload_cas <= 1'd0; + main_sdram_bankmachine3_cmd_payload_ras <= 1'd0; + main_sdram_bankmachine3_cmd_payload_we <= 1'd0; + main_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd0; + main_sdram_bankmachine3_row_open <= 1'd0; + main_sdram_bankmachine3_cmd_payload_is_read <= 1'd0; + main_sdram_bankmachine3_row_close <= 1'd0; + main_sdram_bankmachine3_cmd_payload_is_write <= 1'd0; + builder_bankmachine3_next_state <= builder_bankmachine3_state; + case (builder_bankmachine3_state) + 1'd1: begin + if ((main_sdram_bankmachine3_twtpcon_ready & main_sdram_bankmachine3_trascon_ready)) begin + main_sdram_bankmachine3_cmd_valid <= 1'd1; + if (main_sdram_bankmachine3_cmd_ready) begin + builder_bankmachine3_next_state <= 3'd5; + end + main_sdram_bankmachine3_cmd_payload_ras <= 1'd1; + main_sdram_bankmachine3_cmd_payload_we <= 1'd1; + main_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1; + end + main_sdram_bankmachine3_row_close <= 1'd1; + end + 2'd2: begin + if ((main_sdram_bankmachine3_twtpcon_ready & main_sdram_bankmachine3_trascon_ready)) begin + builder_bankmachine3_next_state <= 3'd5; + end + main_sdram_bankmachine3_row_close <= 1'd1; + end + 2'd3: begin + if (main_sdram_bankmachine3_trccon_ready) begin + main_sdram_bankmachine3_row_col_n_addr_sel <= 1'd1; + main_sdram_bankmachine3_row_open <= 1'd1; + main_sdram_bankmachine3_cmd_valid <= 1'd1; + main_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1; + if (main_sdram_bankmachine3_cmd_ready) begin + builder_bankmachine3_next_state <= 3'd6; + end + main_sdram_bankmachine3_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + if (main_sdram_bankmachine3_twtpcon_ready) begin + main_sdram_bankmachine3_refresh_gnt <= 1'd1; + end + main_sdram_bankmachine3_row_close <= 1'd1; + main_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1; + if ((~main_sdram_bankmachine3_refresh_req)) begin + builder_bankmachine3_next_state <= 1'd0; + end + end + 3'd5: begin + builder_bankmachine3_next_state <= 2'd3; + end + 3'd6: begin + builder_bankmachine3_next_state <= 1'd0; + end + default: begin + if (main_sdram_bankmachine3_refresh_req) begin + builder_bankmachine3_next_state <= 3'd4; + end else begin + if (main_sdram_bankmachine3_cmd_buffer_source_valid) begin + if (main_sdram_bankmachine3_row_opened) begin + if (main_sdram_bankmachine3_row_hit) begin + main_sdram_bankmachine3_cmd_valid <= 1'd1; + if (main_sdram_bankmachine3_cmd_buffer_source_payload_we) begin + main_sdram_bankmachine3_req_wdata_ready <= main_sdram_bankmachine3_cmd_ready; + main_sdram_bankmachine3_cmd_payload_is_write <= 1'd1; + main_sdram_bankmachine3_cmd_payload_we <= 1'd1; + end else begin + main_sdram_bankmachine3_req_rdata_valid <= main_sdram_bankmachine3_cmd_ready; + main_sdram_bankmachine3_cmd_payload_is_read <= 1'd1; + end + main_sdram_bankmachine3_cmd_payload_cas <= 1'd1; + if ((main_sdram_bankmachine3_cmd_ready & main_sdram_bankmachine3_auto_precharge)) begin + builder_bankmachine3_next_state <= 2'd2; + end + end else begin + builder_bankmachine3_next_state <= 1'd1; + end + end else begin + builder_bankmachine3_next_state <= 2'd3; + end + end + end + end + endcase +end +assign main_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine4_req_valid; +assign main_sdram_bankmachine4_req_ready = main_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready; +assign main_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine4_req_we; +assign main_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine4_req_addr; +assign main_sdram_bankmachine4_cmd_buffer_sink_valid = main_sdram_bankmachine4_cmd_buffer_lookahead_source_valid; +assign main_sdram_bankmachine4_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine4_cmd_buffer_sink_ready; +assign main_sdram_bankmachine4_cmd_buffer_sink_first = main_sdram_bankmachine4_cmd_buffer_lookahead_source_first; +assign main_sdram_bankmachine4_cmd_buffer_sink_last = main_sdram_bankmachine4_cmd_buffer_lookahead_source_last; +assign main_sdram_bankmachine4_cmd_buffer_sink_payload_we = main_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we; +assign main_sdram_bankmachine4_cmd_buffer_sink_payload_addr = main_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr; +assign main_sdram_bankmachine4_cmd_buffer_source_ready = (main_sdram_bankmachine4_req_wdata_ready | main_sdram_bankmachine4_req_rdata_valid); +assign main_sdram_bankmachine4_req_lock = (main_sdram_bankmachine4_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine4_cmd_buffer_source_valid); +assign main_sdram_bankmachine4_row_hit = (main_sdram_bankmachine4_row == main_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7]); +assign main_sdram_bankmachine4_cmd_payload_ba = 3'd4; +always @(*) begin + main_sdram_bankmachine4_cmd_payload_a <= 14'd0; + if (main_sdram_bankmachine4_row_col_n_addr_sel) begin + main_sdram_bankmachine4_cmd_payload_a <= main_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7]; + end else begin + main_sdram_bankmachine4_cmd_payload_a <= ((main_sdram_bankmachine4_auto_precharge <<< 4'd10) | {main_sdram_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_sdram_bankmachine4_twtpcon_valid = ((main_sdram_bankmachine4_cmd_valid & main_sdram_bankmachine4_cmd_ready) & main_sdram_bankmachine4_cmd_payload_is_write); +assign main_sdram_bankmachine4_trccon_valid = ((main_sdram_bankmachine4_cmd_valid & main_sdram_bankmachine4_cmd_ready) & main_sdram_bankmachine4_row_open); +assign main_sdram_bankmachine4_trascon_valid = ((main_sdram_bankmachine4_cmd_valid & main_sdram_bankmachine4_cmd_ready) & main_sdram_bankmachine4_row_open); +always @(*) begin + main_sdram_bankmachine4_auto_precharge <= 1'd0; + if ((main_sdram_bankmachine4_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine4_cmd_buffer_source_valid)) begin + if ((main_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != main_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin + main_sdram_bankmachine4_auto_precharge <= (main_sdram_bankmachine4_row_close == 1'd0); + end + end +end +assign main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last, main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first, main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout; +assign main_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable; +assign main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = main_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid; +assign main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine4_cmd_buffer_lookahead_sink_first; +assign main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine4_cmd_buffer_lookahead_sink_last; +assign main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we; +assign main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr; +assign main_sdram_bankmachine4_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable; +assign main_sdram_bankmachine4_cmd_buffer_lookahead_source_first = main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first; +assign main_sdram_bankmachine4_cmd_buffer_lookahead_source_last = main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last; +assign main_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = main_sdram_bankmachine4_cmd_buffer_lookahead_source_ready; +always @(*) begin + main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 3'd0; + if (main_sdram_bankmachine4_cmd_buffer_lookahead_replace) begin + main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine4_cmd_buffer_lookahead_produce - 1'd1); + end else begin + main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine4_cmd_buffer_lookahead_produce; + end +end +assign main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din; +assign main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | main_sdram_bankmachine4_cmd_buffer_lookahead_replace)); +assign main_sdram_bankmachine4_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re); +assign main_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine4_cmd_buffer_lookahead_consume; +assign main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = main_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r; +assign main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (main_sdram_bankmachine4_cmd_buffer_lookahead_level != 4'd8); +assign main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (main_sdram_bankmachine4_cmd_buffer_lookahead_level != 1'd0); +assign main_sdram_bankmachine4_cmd_buffer_pipe_ce = (main_sdram_bankmachine4_cmd_buffer_source_ready | (~main_sdram_bankmachine4_cmd_buffer_valid_n)); +assign main_sdram_bankmachine4_cmd_buffer_sink_ready = main_sdram_bankmachine4_cmd_buffer_pipe_ce; +assign main_sdram_bankmachine4_cmd_buffer_source_valid = main_sdram_bankmachine4_cmd_buffer_valid_n; +assign main_sdram_bankmachine4_cmd_buffer_busy = (1'd0 | main_sdram_bankmachine4_cmd_buffer_valid_n); +assign main_sdram_bankmachine4_cmd_buffer_source_first = main_sdram_bankmachine4_cmd_buffer_first_n; +assign main_sdram_bankmachine4_cmd_buffer_source_last = main_sdram_bankmachine4_cmd_buffer_last_n; +always @(*) begin + main_sdram_bankmachine4_cmd_payload_cas <= 1'd0; + main_sdram_bankmachine4_cmd_payload_ras <= 1'd0; + main_sdram_bankmachine4_cmd_payload_we <= 1'd0; + main_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd0; + main_sdram_bankmachine4_row_open <= 1'd0; + main_sdram_bankmachine4_cmd_payload_is_read <= 1'd0; + main_sdram_bankmachine4_row_close <= 1'd0; + main_sdram_bankmachine4_cmd_payload_is_write <= 1'd0; + builder_bankmachine4_next_state <= 3'd0; + main_sdram_bankmachine4_req_wdata_ready <= 1'd0; + main_sdram_bankmachine4_req_rdata_valid <= 1'd0; + main_sdram_bankmachine4_row_col_n_addr_sel <= 1'd0; + main_sdram_bankmachine4_refresh_gnt <= 1'd0; + main_sdram_bankmachine4_cmd_valid <= 1'd0; + builder_bankmachine4_next_state <= builder_bankmachine4_state; + case (builder_bankmachine4_state) + 1'd1: begin + if ((main_sdram_bankmachine4_twtpcon_ready & main_sdram_bankmachine4_trascon_ready)) begin + main_sdram_bankmachine4_cmd_valid <= 1'd1; + if (main_sdram_bankmachine4_cmd_ready) begin + builder_bankmachine4_next_state <= 3'd5; + end + main_sdram_bankmachine4_cmd_payload_ras <= 1'd1; + main_sdram_bankmachine4_cmd_payload_we <= 1'd1; + main_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1; + end + main_sdram_bankmachine4_row_close <= 1'd1; + end + 2'd2: begin + if ((main_sdram_bankmachine4_twtpcon_ready & main_sdram_bankmachine4_trascon_ready)) begin + builder_bankmachine4_next_state <= 3'd5; + end + main_sdram_bankmachine4_row_close <= 1'd1; + end + 2'd3: begin + if (main_sdram_bankmachine4_trccon_ready) begin + main_sdram_bankmachine4_row_col_n_addr_sel <= 1'd1; + main_sdram_bankmachine4_row_open <= 1'd1; + main_sdram_bankmachine4_cmd_valid <= 1'd1; + main_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1; + if (main_sdram_bankmachine4_cmd_ready) begin + builder_bankmachine4_next_state <= 3'd6; + end + main_sdram_bankmachine4_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + if (main_sdram_bankmachine4_twtpcon_ready) begin + main_sdram_bankmachine4_refresh_gnt <= 1'd1; + end + main_sdram_bankmachine4_row_close <= 1'd1; + main_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1; + if ((~main_sdram_bankmachine4_refresh_req)) begin + builder_bankmachine4_next_state <= 1'd0; + end + end + 3'd5: begin + builder_bankmachine4_next_state <= 2'd3; + end + 3'd6: begin + builder_bankmachine4_next_state <= 1'd0; + end + default: begin + if (main_sdram_bankmachine4_refresh_req) begin + builder_bankmachine4_next_state <= 3'd4; + end else begin + if (main_sdram_bankmachine4_cmd_buffer_source_valid) begin + if (main_sdram_bankmachine4_row_opened) begin + if (main_sdram_bankmachine4_row_hit) begin + main_sdram_bankmachine4_cmd_valid <= 1'd1; + if (main_sdram_bankmachine4_cmd_buffer_source_payload_we) begin + main_sdram_bankmachine4_req_wdata_ready <= main_sdram_bankmachine4_cmd_ready; + main_sdram_bankmachine4_cmd_payload_is_write <= 1'd1; + main_sdram_bankmachine4_cmd_payload_we <= 1'd1; + end else begin + main_sdram_bankmachine4_req_rdata_valid <= main_sdram_bankmachine4_cmd_ready; + main_sdram_bankmachine4_cmd_payload_is_read <= 1'd1; + end + main_sdram_bankmachine4_cmd_payload_cas <= 1'd1; + if ((main_sdram_bankmachine4_cmd_ready & main_sdram_bankmachine4_auto_precharge)) begin + builder_bankmachine4_next_state <= 2'd2; + end + end else begin + builder_bankmachine4_next_state <= 1'd1; + end + end else begin + builder_bankmachine4_next_state <= 2'd3; + end + end + end + end + endcase +end +assign main_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine5_req_valid; +assign main_sdram_bankmachine5_req_ready = main_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready; +assign main_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine5_req_we; +assign main_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine5_req_addr; +assign main_sdram_bankmachine5_cmd_buffer_sink_valid = main_sdram_bankmachine5_cmd_buffer_lookahead_source_valid; +assign main_sdram_bankmachine5_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine5_cmd_buffer_sink_ready; +assign main_sdram_bankmachine5_cmd_buffer_sink_first = main_sdram_bankmachine5_cmd_buffer_lookahead_source_first; +assign main_sdram_bankmachine5_cmd_buffer_sink_last = main_sdram_bankmachine5_cmd_buffer_lookahead_source_last; +assign main_sdram_bankmachine5_cmd_buffer_sink_payload_we = main_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we; +assign main_sdram_bankmachine5_cmd_buffer_sink_payload_addr = main_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr; +assign main_sdram_bankmachine5_cmd_buffer_source_ready = (main_sdram_bankmachine5_req_wdata_ready | main_sdram_bankmachine5_req_rdata_valid); +assign main_sdram_bankmachine5_req_lock = (main_sdram_bankmachine5_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine5_cmd_buffer_source_valid); +assign main_sdram_bankmachine5_row_hit = (main_sdram_bankmachine5_row == main_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7]); +assign main_sdram_bankmachine5_cmd_payload_ba = 3'd5; +always @(*) begin + main_sdram_bankmachine5_cmd_payload_a <= 14'd0; + if (main_sdram_bankmachine5_row_col_n_addr_sel) begin + main_sdram_bankmachine5_cmd_payload_a <= main_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7]; + end else begin + main_sdram_bankmachine5_cmd_payload_a <= ((main_sdram_bankmachine5_auto_precharge <<< 4'd10) | {main_sdram_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_sdram_bankmachine5_twtpcon_valid = ((main_sdram_bankmachine5_cmd_valid & main_sdram_bankmachine5_cmd_ready) & main_sdram_bankmachine5_cmd_payload_is_write); +assign main_sdram_bankmachine5_trccon_valid = ((main_sdram_bankmachine5_cmd_valid & main_sdram_bankmachine5_cmd_ready) & main_sdram_bankmachine5_row_open); +assign main_sdram_bankmachine5_trascon_valid = ((main_sdram_bankmachine5_cmd_valid & main_sdram_bankmachine5_cmd_ready) & main_sdram_bankmachine5_row_open); +always @(*) begin + main_sdram_bankmachine5_auto_precharge <= 1'd0; + if ((main_sdram_bankmachine5_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine5_cmd_buffer_source_valid)) begin + if ((main_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != main_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin + main_sdram_bankmachine5_auto_precharge <= (main_sdram_bankmachine5_row_close == 1'd0); + end + end +end +assign main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last, main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first, main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout; +assign main_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable; +assign main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = main_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid; +assign main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine5_cmd_buffer_lookahead_sink_first; +assign main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine5_cmd_buffer_lookahead_sink_last; +assign main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we; +assign main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr; +assign main_sdram_bankmachine5_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable; +assign main_sdram_bankmachine5_cmd_buffer_lookahead_source_first = main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first; +assign main_sdram_bankmachine5_cmd_buffer_lookahead_source_last = main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last; +assign main_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = main_sdram_bankmachine5_cmd_buffer_lookahead_source_ready; +always @(*) begin + main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 3'd0; + if (main_sdram_bankmachine5_cmd_buffer_lookahead_replace) begin + main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine5_cmd_buffer_lookahead_produce - 1'd1); + end else begin + main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine5_cmd_buffer_lookahead_produce; + end +end +assign main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din; +assign main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | main_sdram_bankmachine5_cmd_buffer_lookahead_replace)); +assign main_sdram_bankmachine5_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re); +assign main_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine5_cmd_buffer_lookahead_consume; +assign main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = main_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r; +assign main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (main_sdram_bankmachine5_cmd_buffer_lookahead_level != 4'd8); +assign main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (main_sdram_bankmachine5_cmd_buffer_lookahead_level != 1'd0); +assign main_sdram_bankmachine5_cmd_buffer_pipe_ce = (main_sdram_bankmachine5_cmd_buffer_source_ready | (~main_sdram_bankmachine5_cmd_buffer_valid_n)); +assign main_sdram_bankmachine5_cmd_buffer_sink_ready = main_sdram_bankmachine5_cmd_buffer_pipe_ce; +assign main_sdram_bankmachine5_cmd_buffer_source_valid = main_sdram_bankmachine5_cmd_buffer_valid_n; +assign main_sdram_bankmachine5_cmd_buffer_busy = (1'd0 | main_sdram_bankmachine5_cmd_buffer_valid_n); +assign main_sdram_bankmachine5_cmd_buffer_source_first = main_sdram_bankmachine5_cmd_buffer_first_n; +assign main_sdram_bankmachine5_cmd_buffer_source_last = main_sdram_bankmachine5_cmd_buffer_last_n; +always @(*) begin + main_sdram_bankmachine5_cmd_valid <= 1'd0; + builder_bankmachine5_next_state <= 3'd0; + main_sdram_bankmachine5_cmd_payload_cas <= 1'd0; + main_sdram_bankmachine5_cmd_payload_ras <= 1'd0; + main_sdram_bankmachine5_cmd_payload_we <= 1'd0; + main_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd0; + main_sdram_bankmachine5_row_open <= 1'd0; + main_sdram_bankmachine5_cmd_payload_is_read <= 1'd0; + main_sdram_bankmachine5_row_close <= 1'd0; + main_sdram_bankmachine5_cmd_payload_is_write <= 1'd0; + main_sdram_bankmachine5_req_wdata_ready <= 1'd0; + main_sdram_bankmachine5_req_rdata_valid <= 1'd0; + main_sdram_bankmachine5_row_col_n_addr_sel <= 1'd0; + main_sdram_bankmachine5_refresh_gnt <= 1'd0; + builder_bankmachine5_next_state <= builder_bankmachine5_state; + case (builder_bankmachine5_state) + 1'd1: begin + if ((main_sdram_bankmachine5_twtpcon_ready & main_sdram_bankmachine5_trascon_ready)) begin + main_sdram_bankmachine5_cmd_valid <= 1'd1; + if (main_sdram_bankmachine5_cmd_ready) begin + builder_bankmachine5_next_state <= 3'd5; + end + main_sdram_bankmachine5_cmd_payload_ras <= 1'd1; + main_sdram_bankmachine5_cmd_payload_we <= 1'd1; + main_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1; + end + main_sdram_bankmachine5_row_close <= 1'd1; + end + 2'd2: begin + if ((main_sdram_bankmachine5_twtpcon_ready & main_sdram_bankmachine5_trascon_ready)) begin + builder_bankmachine5_next_state <= 3'd5; + end + main_sdram_bankmachine5_row_close <= 1'd1; + end + 2'd3: begin + if (main_sdram_bankmachine5_trccon_ready) begin + main_sdram_bankmachine5_row_col_n_addr_sel <= 1'd1; + main_sdram_bankmachine5_row_open <= 1'd1; + main_sdram_bankmachine5_cmd_valid <= 1'd1; + main_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1; + if (main_sdram_bankmachine5_cmd_ready) begin + builder_bankmachine5_next_state <= 3'd6; + end + main_sdram_bankmachine5_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + if (main_sdram_bankmachine5_twtpcon_ready) begin + main_sdram_bankmachine5_refresh_gnt <= 1'd1; + end + main_sdram_bankmachine5_row_close <= 1'd1; + main_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1; + if ((~main_sdram_bankmachine5_refresh_req)) begin + builder_bankmachine5_next_state <= 1'd0; + end + end + 3'd5: begin + builder_bankmachine5_next_state <= 2'd3; + end + 3'd6: begin + builder_bankmachine5_next_state <= 1'd0; + end + default: begin + if (main_sdram_bankmachine5_refresh_req) begin + builder_bankmachine5_next_state <= 3'd4; + end else begin + if (main_sdram_bankmachine5_cmd_buffer_source_valid) begin + if (main_sdram_bankmachine5_row_opened) begin + if (main_sdram_bankmachine5_row_hit) begin + main_sdram_bankmachine5_cmd_valid <= 1'd1; + if (main_sdram_bankmachine5_cmd_buffer_source_payload_we) begin + main_sdram_bankmachine5_req_wdata_ready <= main_sdram_bankmachine5_cmd_ready; + main_sdram_bankmachine5_cmd_payload_is_write <= 1'd1; + main_sdram_bankmachine5_cmd_payload_we <= 1'd1; + end else begin + main_sdram_bankmachine5_req_rdata_valid <= main_sdram_bankmachine5_cmd_ready; + main_sdram_bankmachine5_cmd_payload_is_read <= 1'd1; + end + main_sdram_bankmachine5_cmd_payload_cas <= 1'd1; + if ((main_sdram_bankmachine5_cmd_ready & main_sdram_bankmachine5_auto_precharge)) begin + builder_bankmachine5_next_state <= 2'd2; + end + end else begin + builder_bankmachine5_next_state <= 1'd1; + end + end else begin + builder_bankmachine5_next_state <= 2'd3; + end + end + end + end + endcase +end +assign main_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine6_req_valid; +assign main_sdram_bankmachine6_req_ready = main_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready; +assign main_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine6_req_we; +assign main_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine6_req_addr; +assign main_sdram_bankmachine6_cmd_buffer_sink_valid = main_sdram_bankmachine6_cmd_buffer_lookahead_source_valid; +assign main_sdram_bankmachine6_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine6_cmd_buffer_sink_ready; +assign main_sdram_bankmachine6_cmd_buffer_sink_first = main_sdram_bankmachine6_cmd_buffer_lookahead_source_first; +assign main_sdram_bankmachine6_cmd_buffer_sink_last = main_sdram_bankmachine6_cmd_buffer_lookahead_source_last; +assign main_sdram_bankmachine6_cmd_buffer_sink_payload_we = main_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we; +assign main_sdram_bankmachine6_cmd_buffer_sink_payload_addr = main_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr; +assign main_sdram_bankmachine6_cmd_buffer_source_ready = (main_sdram_bankmachine6_req_wdata_ready | main_sdram_bankmachine6_req_rdata_valid); +assign main_sdram_bankmachine6_req_lock = (main_sdram_bankmachine6_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine6_cmd_buffer_source_valid); +assign main_sdram_bankmachine6_row_hit = (main_sdram_bankmachine6_row == main_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7]); +assign main_sdram_bankmachine6_cmd_payload_ba = 3'd6; +always @(*) begin + main_sdram_bankmachine6_cmd_payload_a <= 14'd0; + if (main_sdram_bankmachine6_row_col_n_addr_sel) begin + main_sdram_bankmachine6_cmd_payload_a <= main_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7]; + end else begin + main_sdram_bankmachine6_cmd_payload_a <= ((main_sdram_bankmachine6_auto_precharge <<< 4'd10) | {main_sdram_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_sdram_bankmachine6_twtpcon_valid = ((main_sdram_bankmachine6_cmd_valid & main_sdram_bankmachine6_cmd_ready) & main_sdram_bankmachine6_cmd_payload_is_write); +assign main_sdram_bankmachine6_trccon_valid = ((main_sdram_bankmachine6_cmd_valid & main_sdram_bankmachine6_cmd_ready) & main_sdram_bankmachine6_row_open); +assign main_sdram_bankmachine6_trascon_valid = ((main_sdram_bankmachine6_cmd_valid & main_sdram_bankmachine6_cmd_ready) & main_sdram_bankmachine6_row_open); +always @(*) begin + main_sdram_bankmachine6_auto_precharge <= 1'd0; + if ((main_sdram_bankmachine6_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine6_cmd_buffer_source_valid)) begin + if ((main_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != main_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin + main_sdram_bankmachine6_auto_precharge <= (main_sdram_bankmachine6_row_close == 1'd0); + end + end +end +assign main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last, main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first, main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout; +assign main_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable; +assign main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = main_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid; +assign main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine6_cmd_buffer_lookahead_sink_first; +assign main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine6_cmd_buffer_lookahead_sink_last; +assign main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we; +assign main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr; +assign main_sdram_bankmachine6_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable; +assign main_sdram_bankmachine6_cmd_buffer_lookahead_source_first = main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first; +assign main_sdram_bankmachine6_cmd_buffer_lookahead_source_last = main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last; +assign main_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = main_sdram_bankmachine6_cmd_buffer_lookahead_source_ready; +always @(*) begin + main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 3'd0; + if (main_sdram_bankmachine6_cmd_buffer_lookahead_replace) begin + main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine6_cmd_buffer_lookahead_produce - 1'd1); + end else begin + main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine6_cmd_buffer_lookahead_produce; + end +end +assign main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din; +assign main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | main_sdram_bankmachine6_cmd_buffer_lookahead_replace)); +assign main_sdram_bankmachine6_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re); +assign main_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine6_cmd_buffer_lookahead_consume; +assign main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = main_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r; +assign main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (main_sdram_bankmachine6_cmd_buffer_lookahead_level != 4'd8); +assign main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (main_sdram_bankmachine6_cmd_buffer_lookahead_level != 1'd0); +assign main_sdram_bankmachine6_cmd_buffer_pipe_ce = (main_sdram_bankmachine6_cmd_buffer_source_ready | (~main_sdram_bankmachine6_cmd_buffer_valid_n)); +assign main_sdram_bankmachine6_cmd_buffer_sink_ready = main_sdram_bankmachine6_cmd_buffer_pipe_ce; +assign main_sdram_bankmachine6_cmd_buffer_source_valid = main_sdram_bankmachine6_cmd_buffer_valid_n; +assign main_sdram_bankmachine6_cmd_buffer_busy = (1'd0 | main_sdram_bankmachine6_cmd_buffer_valid_n); +assign main_sdram_bankmachine6_cmd_buffer_source_first = main_sdram_bankmachine6_cmd_buffer_first_n; +assign main_sdram_bankmachine6_cmd_buffer_source_last = main_sdram_bankmachine6_cmd_buffer_last_n; +always @(*) begin + main_sdram_bankmachine6_row_open <= 1'd0; + main_sdram_bankmachine6_cmd_payload_is_read <= 1'd0; + main_sdram_bankmachine6_row_close <= 1'd0; + main_sdram_bankmachine6_cmd_payload_is_write <= 1'd0; + builder_bankmachine6_next_state <= 3'd0; + main_sdram_bankmachine6_req_wdata_ready <= 1'd0; + main_sdram_bankmachine6_req_rdata_valid <= 1'd0; + main_sdram_bankmachine6_row_col_n_addr_sel <= 1'd0; + main_sdram_bankmachine6_refresh_gnt <= 1'd0; + main_sdram_bankmachine6_cmd_valid <= 1'd0; + main_sdram_bankmachine6_cmd_payload_cas <= 1'd0; + main_sdram_bankmachine6_cmd_payload_ras <= 1'd0; + main_sdram_bankmachine6_cmd_payload_we <= 1'd0; + main_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd0; + builder_bankmachine6_next_state <= builder_bankmachine6_state; + case (builder_bankmachine6_state) + 1'd1: begin + if ((main_sdram_bankmachine6_twtpcon_ready & main_sdram_bankmachine6_trascon_ready)) begin + main_sdram_bankmachine6_cmd_valid <= 1'd1; + if (main_sdram_bankmachine6_cmd_ready) begin + builder_bankmachine6_next_state <= 3'd5; + end + main_sdram_bankmachine6_cmd_payload_ras <= 1'd1; + main_sdram_bankmachine6_cmd_payload_we <= 1'd1; + main_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1; + end + main_sdram_bankmachine6_row_close <= 1'd1; + end + 2'd2: begin + if ((main_sdram_bankmachine6_twtpcon_ready & main_sdram_bankmachine6_trascon_ready)) begin + builder_bankmachine6_next_state <= 3'd5; + end + main_sdram_bankmachine6_row_close <= 1'd1; + end + 2'd3: begin + if (main_sdram_bankmachine6_trccon_ready) begin + main_sdram_bankmachine6_row_col_n_addr_sel <= 1'd1; + main_sdram_bankmachine6_row_open <= 1'd1; + main_sdram_bankmachine6_cmd_valid <= 1'd1; + main_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1; + if (main_sdram_bankmachine6_cmd_ready) begin + builder_bankmachine6_next_state <= 3'd6; + end + main_sdram_bankmachine6_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + if (main_sdram_bankmachine6_twtpcon_ready) begin + main_sdram_bankmachine6_refresh_gnt <= 1'd1; + end + main_sdram_bankmachine6_row_close <= 1'd1; + main_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1; + if ((~main_sdram_bankmachine6_refresh_req)) begin + builder_bankmachine6_next_state <= 1'd0; + end + end + 3'd5: begin + builder_bankmachine6_next_state <= 2'd3; + end + 3'd6: begin + builder_bankmachine6_next_state <= 1'd0; + end + default: begin + if (main_sdram_bankmachine6_refresh_req) begin + builder_bankmachine6_next_state <= 3'd4; + end else begin + if (main_sdram_bankmachine6_cmd_buffer_source_valid) begin + if (main_sdram_bankmachine6_row_opened) begin + if (main_sdram_bankmachine6_row_hit) begin + main_sdram_bankmachine6_cmd_valid <= 1'd1; + if (main_sdram_bankmachine6_cmd_buffer_source_payload_we) begin + main_sdram_bankmachine6_req_wdata_ready <= main_sdram_bankmachine6_cmd_ready; + main_sdram_bankmachine6_cmd_payload_is_write <= 1'd1; + main_sdram_bankmachine6_cmd_payload_we <= 1'd1; + end else begin + main_sdram_bankmachine6_req_rdata_valid <= main_sdram_bankmachine6_cmd_ready; + main_sdram_bankmachine6_cmd_payload_is_read <= 1'd1; + end + main_sdram_bankmachine6_cmd_payload_cas <= 1'd1; + if ((main_sdram_bankmachine6_cmd_ready & main_sdram_bankmachine6_auto_precharge)) begin + builder_bankmachine6_next_state <= 2'd2; + end + end else begin + builder_bankmachine6_next_state <= 1'd1; + end + end else begin + builder_bankmachine6_next_state <= 2'd3; + end + end + end + end + endcase +end +assign main_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid = main_sdram_bankmachine7_req_valid; +assign main_sdram_bankmachine7_req_ready = main_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready; +assign main_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we = main_sdram_bankmachine7_req_we; +assign main_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = main_sdram_bankmachine7_req_addr; +assign main_sdram_bankmachine7_cmd_buffer_sink_valid = main_sdram_bankmachine7_cmd_buffer_lookahead_source_valid; +assign main_sdram_bankmachine7_cmd_buffer_lookahead_source_ready = main_sdram_bankmachine7_cmd_buffer_sink_ready; +assign main_sdram_bankmachine7_cmd_buffer_sink_first = main_sdram_bankmachine7_cmd_buffer_lookahead_source_first; +assign main_sdram_bankmachine7_cmd_buffer_sink_last = main_sdram_bankmachine7_cmd_buffer_lookahead_source_last; +assign main_sdram_bankmachine7_cmd_buffer_sink_payload_we = main_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we; +assign main_sdram_bankmachine7_cmd_buffer_sink_payload_addr = main_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr; +assign main_sdram_bankmachine7_cmd_buffer_source_ready = (main_sdram_bankmachine7_req_wdata_ready | main_sdram_bankmachine7_req_rdata_valid); +assign main_sdram_bankmachine7_req_lock = (main_sdram_bankmachine7_cmd_buffer_lookahead_source_valid | main_sdram_bankmachine7_cmd_buffer_source_valid); +assign main_sdram_bankmachine7_row_hit = (main_sdram_bankmachine7_row == main_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7]); +assign main_sdram_bankmachine7_cmd_payload_ba = 3'd7; +always @(*) begin + main_sdram_bankmachine7_cmd_payload_a <= 14'd0; + if (main_sdram_bankmachine7_row_col_n_addr_sel) begin + main_sdram_bankmachine7_cmd_payload_a <= main_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7]; + end else begin + main_sdram_bankmachine7_cmd_payload_a <= ((main_sdram_bankmachine7_auto_precharge <<< 4'd10) | {main_sdram_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}}); + end +end +assign main_sdram_bankmachine7_twtpcon_valid = ((main_sdram_bankmachine7_cmd_valid & main_sdram_bankmachine7_cmd_ready) & main_sdram_bankmachine7_cmd_payload_is_write); +assign main_sdram_bankmachine7_trccon_valid = ((main_sdram_bankmachine7_cmd_valid & main_sdram_bankmachine7_cmd_ready) & main_sdram_bankmachine7_row_open); +assign main_sdram_bankmachine7_trascon_valid = ((main_sdram_bankmachine7_cmd_valid & main_sdram_bankmachine7_cmd_ready) & main_sdram_bankmachine7_row_open); +always @(*) begin + main_sdram_bankmachine7_auto_precharge <= 1'd0; + if ((main_sdram_bankmachine7_cmd_buffer_lookahead_source_valid & main_sdram_bankmachine7_cmd_buffer_source_valid)) begin + if ((main_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != main_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin + main_sdram_bankmachine7_auto_precharge <= (main_sdram_bankmachine7_row_close == 1'd0); + end + end +end +assign main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last, main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first, main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we}; +assign {main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout; +assign main_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready = main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable; +assign main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = main_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid; +assign main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first = main_sdram_bankmachine7_cmd_buffer_lookahead_sink_first; +assign main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last = main_sdram_bankmachine7_cmd_buffer_lookahead_sink_last; +assign main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = main_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we; +assign main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = main_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr; +assign main_sdram_bankmachine7_cmd_buffer_lookahead_source_valid = main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable; +assign main_sdram_bankmachine7_cmd_buffer_lookahead_source_first = main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first; +assign main_sdram_bankmachine7_cmd_buffer_lookahead_source_last = main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last; +assign main_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we = main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we; +assign main_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr = main_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr; +assign main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = main_sdram_bankmachine7_cmd_buffer_lookahead_source_ready; +always @(*) begin + main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 3'd0; + if (main_sdram_bankmachine7_cmd_buffer_lookahead_replace) begin + main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (main_sdram_bankmachine7_cmd_buffer_lookahead_produce - 1'd1); + end else begin + main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= main_sdram_bankmachine7_cmd_buffer_lookahead_produce; + end +end +assign main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din; +assign main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we = (main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | main_sdram_bankmachine7_cmd_buffer_lookahead_replace)); +assign main_sdram_bankmachine7_cmd_buffer_lookahead_do_read = (main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re); +assign main_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr = main_sdram_bankmachine7_cmd_buffer_lookahead_consume; +assign main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = main_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r; +assign main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (main_sdram_bankmachine7_cmd_buffer_lookahead_level != 4'd8); +assign main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (main_sdram_bankmachine7_cmd_buffer_lookahead_level != 1'd0); +assign main_sdram_bankmachine7_cmd_buffer_pipe_ce = (main_sdram_bankmachine7_cmd_buffer_source_ready | (~main_sdram_bankmachine7_cmd_buffer_valid_n)); +assign main_sdram_bankmachine7_cmd_buffer_sink_ready = main_sdram_bankmachine7_cmd_buffer_pipe_ce; +assign main_sdram_bankmachine7_cmd_buffer_source_valid = main_sdram_bankmachine7_cmd_buffer_valid_n; +assign main_sdram_bankmachine7_cmd_buffer_busy = (1'd0 | main_sdram_bankmachine7_cmd_buffer_valid_n); +assign main_sdram_bankmachine7_cmd_buffer_source_first = main_sdram_bankmachine7_cmd_buffer_first_n; +assign main_sdram_bankmachine7_cmd_buffer_source_last = main_sdram_bankmachine7_cmd_buffer_last_n; +always @(*) begin + builder_bankmachine7_next_state <= 3'd0; + main_sdram_bankmachine7_cmd_payload_cas <= 1'd0; + main_sdram_bankmachine7_cmd_payload_ras <= 1'd0; + main_sdram_bankmachine7_cmd_payload_we <= 1'd0; + main_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd0; + main_sdram_bankmachine7_row_open <= 1'd0; + main_sdram_bankmachine7_cmd_payload_is_read <= 1'd0; + main_sdram_bankmachine7_row_close <= 1'd0; + main_sdram_bankmachine7_cmd_payload_is_write <= 1'd0; + main_sdram_bankmachine7_req_wdata_ready <= 1'd0; + main_sdram_bankmachine7_req_rdata_valid <= 1'd0; + main_sdram_bankmachine7_row_col_n_addr_sel <= 1'd0; + main_sdram_bankmachine7_refresh_gnt <= 1'd0; + main_sdram_bankmachine7_cmd_valid <= 1'd0; + builder_bankmachine7_next_state <= builder_bankmachine7_state; + case (builder_bankmachine7_state) + 1'd1: begin + if ((main_sdram_bankmachine7_twtpcon_ready & main_sdram_bankmachine7_trascon_ready)) begin + main_sdram_bankmachine7_cmd_valid <= 1'd1; + if (main_sdram_bankmachine7_cmd_ready) begin + builder_bankmachine7_next_state <= 3'd5; + end + main_sdram_bankmachine7_cmd_payload_ras <= 1'd1; + main_sdram_bankmachine7_cmd_payload_we <= 1'd1; + main_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1; + end + main_sdram_bankmachine7_row_close <= 1'd1; + end + 2'd2: begin + if ((main_sdram_bankmachine7_twtpcon_ready & main_sdram_bankmachine7_trascon_ready)) begin + builder_bankmachine7_next_state <= 3'd5; + end + main_sdram_bankmachine7_row_close <= 1'd1; + end + 2'd3: begin + if (main_sdram_bankmachine7_trccon_ready) begin + main_sdram_bankmachine7_row_col_n_addr_sel <= 1'd1; + main_sdram_bankmachine7_row_open <= 1'd1; + main_sdram_bankmachine7_cmd_valid <= 1'd1; + main_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1; + if (main_sdram_bankmachine7_cmd_ready) begin + builder_bankmachine7_next_state <= 3'd6; + end + main_sdram_bankmachine7_cmd_payload_ras <= 1'd1; + end + end + 3'd4: begin + if (main_sdram_bankmachine7_twtpcon_ready) begin + main_sdram_bankmachine7_refresh_gnt <= 1'd1; + end + main_sdram_bankmachine7_row_close <= 1'd1; + main_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1; + if ((~main_sdram_bankmachine7_refresh_req)) begin + builder_bankmachine7_next_state <= 1'd0; + end + end + 3'd5: begin + builder_bankmachine7_next_state <= 2'd3; + end + 3'd6: begin + builder_bankmachine7_next_state <= 1'd0; + end + default: begin + if (main_sdram_bankmachine7_refresh_req) begin + builder_bankmachine7_next_state <= 3'd4; + end else begin + if (main_sdram_bankmachine7_cmd_buffer_source_valid) begin + if (main_sdram_bankmachine7_row_opened) begin + if (main_sdram_bankmachine7_row_hit) begin + main_sdram_bankmachine7_cmd_valid <= 1'd1; + if (main_sdram_bankmachine7_cmd_buffer_source_payload_we) begin + main_sdram_bankmachine7_req_wdata_ready <= main_sdram_bankmachine7_cmd_ready; + main_sdram_bankmachine7_cmd_payload_is_write <= 1'd1; + main_sdram_bankmachine7_cmd_payload_we <= 1'd1; + end else begin + main_sdram_bankmachine7_req_rdata_valid <= main_sdram_bankmachine7_cmd_ready; + main_sdram_bankmachine7_cmd_payload_is_read <= 1'd1; + end + main_sdram_bankmachine7_cmd_payload_cas <= 1'd1; + if ((main_sdram_bankmachine7_cmd_ready & main_sdram_bankmachine7_auto_precharge)) begin + builder_bankmachine7_next_state <= 2'd2; + end + end else begin + builder_bankmachine7_next_state <= 1'd1; + end + end else begin + builder_bankmachine7_next_state <= 2'd3; + end + end + end + end + endcase +end +assign main_sdram_trrdcon_valid = ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & ((main_sdram_choose_cmd_cmd_payload_ras & (~main_sdram_choose_cmd_cmd_payload_cas)) & (~main_sdram_choose_cmd_cmd_payload_we))); +assign main_sdram_tfawcon_valid = ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & ((main_sdram_choose_cmd_cmd_payload_ras & (~main_sdram_choose_cmd_cmd_payload_cas)) & (~main_sdram_choose_cmd_cmd_payload_we))); +assign main_sdram_ras_allowed = (main_sdram_trrdcon_ready & main_sdram_tfawcon_ready); +assign main_sdram_tccdcon_valid = ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_cmd_payload_is_write | main_sdram_choose_req_cmd_payload_is_read)); +assign main_sdram_cas_allowed = main_sdram_tccdcon_ready; +assign main_sdram_twtrcon_valid = ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_write); +assign main_sdram_read_available = ((((((((main_sdram_bankmachine0_cmd_valid & main_sdram_bankmachine0_cmd_payload_is_read) | (main_sdram_bankmachine1_cmd_valid & main_sdram_bankmachine1_cmd_payload_is_read)) | (main_sdram_bankmachine2_cmd_valid & main_sdram_bankmachine2_cmd_payload_is_read)) | (main_sdram_bankmachine3_cmd_valid & main_sdram_bankmachine3_cmd_payload_is_read)) | (main_sdram_bankmachine4_cmd_valid & main_sdram_bankmachine4_cmd_payload_is_read)) | (main_sdram_bankmachine5_cmd_valid & main_sdram_bankmachine5_cmd_payload_is_read)) | (main_sdram_bankmachine6_cmd_valid & main_sdram_bankmachine6_cmd_payload_is_read)) | (main_sdram_bankmachine7_cmd_valid & main_sdram_bankmachine7_cmd_payload_is_read)); +assign main_sdram_write_available = ((((((((main_sdram_bankmachine0_cmd_valid & main_sdram_bankmachine0_cmd_payload_is_write) | (main_sdram_bankmachine1_cmd_valid & main_sdram_bankmachine1_cmd_payload_is_write)) | (main_sdram_bankmachine2_cmd_valid & main_sdram_bankmachine2_cmd_payload_is_write)) | (main_sdram_bankmachine3_cmd_valid & main_sdram_bankmachine3_cmd_payload_is_write)) | (main_sdram_bankmachine4_cmd_valid & main_sdram_bankmachine4_cmd_payload_is_write)) | (main_sdram_bankmachine5_cmd_valid & main_sdram_bankmachine5_cmd_payload_is_write)) | (main_sdram_bankmachine6_cmd_valid & main_sdram_bankmachine6_cmd_payload_is_write)) | (main_sdram_bankmachine7_cmd_valid & main_sdram_bankmachine7_cmd_payload_is_write)); +assign main_sdram_max_time0 = (main_sdram_time0 == 1'd0); +assign main_sdram_max_time1 = (main_sdram_time1 == 1'd0); +assign main_sdram_bankmachine0_refresh_req = main_sdram_cmd_valid; +assign main_sdram_bankmachine1_refresh_req = main_sdram_cmd_valid; +assign main_sdram_bankmachine2_refresh_req = main_sdram_cmd_valid; +assign main_sdram_bankmachine3_refresh_req = main_sdram_cmd_valid; +assign main_sdram_bankmachine4_refresh_req = main_sdram_cmd_valid; +assign main_sdram_bankmachine5_refresh_req = main_sdram_cmd_valid; +assign main_sdram_bankmachine6_refresh_req = main_sdram_cmd_valid; +assign main_sdram_bankmachine7_refresh_req = main_sdram_cmd_valid; +assign main_sdram_go_to_refresh = (((((((main_sdram_bankmachine0_refresh_gnt & main_sdram_bankmachine1_refresh_gnt) & main_sdram_bankmachine2_refresh_gnt) & main_sdram_bankmachine3_refresh_gnt) & main_sdram_bankmachine4_refresh_gnt) & main_sdram_bankmachine5_refresh_gnt) & main_sdram_bankmachine6_refresh_gnt) & main_sdram_bankmachine7_refresh_gnt); +assign main_sdram_interface_rdata = {main_sdram_dfi_p3_rddata, main_sdram_dfi_p2_rddata, main_sdram_dfi_p1_rddata, main_sdram_dfi_p0_rddata}; +assign {main_sdram_dfi_p3_wrdata, main_sdram_dfi_p2_wrdata, main_sdram_dfi_p1_wrdata, main_sdram_dfi_p0_wrdata} = main_sdram_interface_wdata; +assign {main_sdram_dfi_p3_wrdata_mask, main_sdram_dfi_p2_wrdata_mask, main_sdram_dfi_p1_wrdata_mask, main_sdram_dfi_p0_wrdata_mask} = (~main_sdram_interface_wdata_we); +always @(*) begin + main_sdram_choose_cmd_valids <= 8'd0; + main_sdram_choose_cmd_valids[0] <= (main_sdram_bankmachine0_cmd_valid & (((main_sdram_bankmachine0_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine0_cmd_payload_ras & (~main_sdram_bankmachine0_cmd_payload_cas)) & (~main_sdram_bankmachine0_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine0_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine0_cmd_payload_is_write == main_sdram_choose_cmd_want_writes)))); + main_sdram_choose_cmd_valids[1] <= (main_sdram_bankmachine1_cmd_valid & (((main_sdram_bankmachine1_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine1_cmd_payload_ras & (~main_sdram_bankmachine1_cmd_payload_cas)) & (~main_sdram_bankmachine1_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine1_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine1_cmd_payload_is_write == main_sdram_choose_cmd_want_writes)))); + main_sdram_choose_cmd_valids[2] <= (main_sdram_bankmachine2_cmd_valid & (((main_sdram_bankmachine2_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine2_cmd_payload_ras & (~main_sdram_bankmachine2_cmd_payload_cas)) & (~main_sdram_bankmachine2_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine2_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine2_cmd_payload_is_write == main_sdram_choose_cmd_want_writes)))); + main_sdram_choose_cmd_valids[3] <= (main_sdram_bankmachine3_cmd_valid & (((main_sdram_bankmachine3_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine3_cmd_payload_ras & (~main_sdram_bankmachine3_cmd_payload_cas)) & (~main_sdram_bankmachine3_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine3_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine3_cmd_payload_is_write == main_sdram_choose_cmd_want_writes)))); + main_sdram_choose_cmd_valids[4] <= (main_sdram_bankmachine4_cmd_valid & (((main_sdram_bankmachine4_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine4_cmd_payload_ras & (~main_sdram_bankmachine4_cmd_payload_cas)) & (~main_sdram_bankmachine4_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine4_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine4_cmd_payload_is_write == main_sdram_choose_cmd_want_writes)))); + main_sdram_choose_cmd_valids[5] <= (main_sdram_bankmachine5_cmd_valid & (((main_sdram_bankmachine5_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine5_cmd_payload_ras & (~main_sdram_bankmachine5_cmd_payload_cas)) & (~main_sdram_bankmachine5_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine5_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine5_cmd_payload_is_write == main_sdram_choose_cmd_want_writes)))); + main_sdram_choose_cmd_valids[6] <= (main_sdram_bankmachine6_cmd_valid & (((main_sdram_bankmachine6_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine6_cmd_payload_ras & (~main_sdram_bankmachine6_cmd_payload_cas)) & (~main_sdram_bankmachine6_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine6_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine6_cmd_payload_is_write == main_sdram_choose_cmd_want_writes)))); + main_sdram_choose_cmd_valids[7] <= (main_sdram_bankmachine7_cmd_valid & (((main_sdram_bankmachine7_cmd_payload_is_cmd & main_sdram_choose_cmd_want_cmds) & ((~((main_sdram_bankmachine7_cmd_payload_ras & (~main_sdram_bankmachine7_cmd_payload_cas)) & (~main_sdram_bankmachine7_cmd_payload_we))) | main_sdram_choose_cmd_want_activates)) | ((main_sdram_bankmachine7_cmd_payload_is_read == main_sdram_choose_cmd_want_reads) & (main_sdram_bankmachine7_cmd_payload_is_write == main_sdram_choose_cmd_want_writes)))); +end +assign main_sdram_choose_cmd_request = main_sdram_choose_cmd_valids; +assign main_sdram_choose_cmd_cmd_valid = builder_rhs_array_muxed0; +assign main_sdram_choose_cmd_cmd_payload_a = builder_rhs_array_muxed1; +assign main_sdram_choose_cmd_cmd_payload_ba = builder_rhs_array_muxed2; +assign main_sdram_choose_cmd_cmd_payload_is_read = builder_rhs_array_muxed3; +assign main_sdram_choose_cmd_cmd_payload_is_write = builder_rhs_array_muxed4; +assign main_sdram_choose_cmd_cmd_payload_is_cmd = builder_rhs_array_muxed5; +always @(*) begin + main_sdram_choose_cmd_cmd_payload_cas <= 1'd0; + if (main_sdram_choose_cmd_cmd_valid) begin + main_sdram_choose_cmd_cmd_payload_cas <= builder_t_array_muxed0; + end +end +always @(*) begin + main_sdram_choose_cmd_cmd_payload_ras <= 1'd0; + if (main_sdram_choose_cmd_cmd_valid) begin + main_sdram_choose_cmd_cmd_payload_ras <= builder_t_array_muxed1; + end +end +always @(*) begin + main_sdram_choose_cmd_cmd_payload_we <= 1'd0; + if (main_sdram_choose_cmd_cmd_valid) begin + main_sdram_choose_cmd_cmd_payload_we <= builder_t_array_muxed2; + end +end +assign main_sdram_choose_cmd_ce = (main_sdram_choose_cmd_cmd_ready | (~main_sdram_choose_cmd_cmd_valid)); +always @(*) begin + main_sdram_choose_req_valids <= 8'd0; + main_sdram_choose_req_valids[0] <= (main_sdram_bankmachine0_cmd_valid & (((main_sdram_bankmachine0_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine0_cmd_payload_ras & (~main_sdram_bankmachine0_cmd_payload_cas)) & (~main_sdram_bankmachine0_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine0_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine0_cmd_payload_is_write == main_sdram_choose_req_want_writes)))); + main_sdram_choose_req_valids[1] <= (main_sdram_bankmachine1_cmd_valid & (((main_sdram_bankmachine1_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine1_cmd_payload_ras & (~main_sdram_bankmachine1_cmd_payload_cas)) & (~main_sdram_bankmachine1_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine1_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine1_cmd_payload_is_write == main_sdram_choose_req_want_writes)))); + main_sdram_choose_req_valids[2] <= (main_sdram_bankmachine2_cmd_valid & (((main_sdram_bankmachine2_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine2_cmd_payload_ras & (~main_sdram_bankmachine2_cmd_payload_cas)) & (~main_sdram_bankmachine2_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine2_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine2_cmd_payload_is_write == main_sdram_choose_req_want_writes)))); + main_sdram_choose_req_valids[3] <= (main_sdram_bankmachine3_cmd_valid & (((main_sdram_bankmachine3_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine3_cmd_payload_ras & (~main_sdram_bankmachine3_cmd_payload_cas)) & (~main_sdram_bankmachine3_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine3_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine3_cmd_payload_is_write == main_sdram_choose_req_want_writes)))); + main_sdram_choose_req_valids[4] <= (main_sdram_bankmachine4_cmd_valid & (((main_sdram_bankmachine4_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine4_cmd_payload_ras & (~main_sdram_bankmachine4_cmd_payload_cas)) & (~main_sdram_bankmachine4_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine4_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine4_cmd_payload_is_write == main_sdram_choose_req_want_writes)))); + main_sdram_choose_req_valids[5] <= (main_sdram_bankmachine5_cmd_valid & (((main_sdram_bankmachine5_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine5_cmd_payload_ras & (~main_sdram_bankmachine5_cmd_payload_cas)) & (~main_sdram_bankmachine5_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine5_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine5_cmd_payload_is_write == main_sdram_choose_req_want_writes)))); + main_sdram_choose_req_valids[6] <= (main_sdram_bankmachine6_cmd_valid & (((main_sdram_bankmachine6_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine6_cmd_payload_ras & (~main_sdram_bankmachine6_cmd_payload_cas)) & (~main_sdram_bankmachine6_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine6_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine6_cmd_payload_is_write == main_sdram_choose_req_want_writes)))); + main_sdram_choose_req_valids[7] <= (main_sdram_bankmachine7_cmd_valid & (((main_sdram_bankmachine7_cmd_payload_is_cmd & main_sdram_choose_req_want_cmds) & ((~((main_sdram_bankmachine7_cmd_payload_ras & (~main_sdram_bankmachine7_cmd_payload_cas)) & (~main_sdram_bankmachine7_cmd_payload_we))) | main_sdram_choose_req_want_activates)) | ((main_sdram_bankmachine7_cmd_payload_is_read == main_sdram_choose_req_want_reads) & (main_sdram_bankmachine7_cmd_payload_is_write == main_sdram_choose_req_want_writes)))); +end +assign main_sdram_choose_req_request = main_sdram_choose_req_valids; +assign main_sdram_choose_req_cmd_valid = builder_rhs_array_muxed6; +assign main_sdram_choose_req_cmd_payload_a = builder_rhs_array_muxed7; +assign main_sdram_choose_req_cmd_payload_ba = builder_rhs_array_muxed8; +assign main_sdram_choose_req_cmd_payload_is_read = builder_rhs_array_muxed9; +assign main_sdram_choose_req_cmd_payload_is_write = builder_rhs_array_muxed10; +assign main_sdram_choose_req_cmd_payload_is_cmd = builder_rhs_array_muxed11; +always @(*) begin + main_sdram_choose_req_cmd_payload_cas <= 1'd0; + if (main_sdram_choose_req_cmd_valid) begin + main_sdram_choose_req_cmd_payload_cas <= builder_t_array_muxed3; + end +end +always @(*) begin + main_sdram_choose_req_cmd_payload_ras <= 1'd0; + if (main_sdram_choose_req_cmd_valid) begin + main_sdram_choose_req_cmd_payload_ras <= builder_t_array_muxed4; + end +end +always @(*) begin + main_sdram_choose_req_cmd_payload_we <= 1'd0; + if (main_sdram_choose_req_cmd_valid) begin + main_sdram_choose_req_cmd_payload_we <= builder_t_array_muxed5; + end +end +always @(*) begin + main_sdram_bankmachine0_cmd_ready <= 1'd0; + if (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 1'd0))) begin + main_sdram_bankmachine0_cmd_ready <= 1'd1; + end + if (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 1'd0))) begin + main_sdram_bankmachine0_cmd_ready <= 1'd1; + end +end +always @(*) begin + main_sdram_bankmachine1_cmd_ready <= 1'd0; + if (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 1'd1))) begin + main_sdram_bankmachine1_cmd_ready <= 1'd1; + end + if (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 1'd1))) begin + main_sdram_bankmachine1_cmd_ready <= 1'd1; + end +end +always @(*) begin + main_sdram_bankmachine2_cmd_ready <= 1'd0; + if (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 2'd2))) begin + main_sdram_bankmachine2_cmd_ready <= 1'd1; + end + if (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 2'd2))) begin + main_sdram_bankmachine2_cmd_ready <= 1'd1; + end +end +always @(*) begin + main_sdram_bankmachine3_cmd_ready <= 1'd0; + if (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 2'd3))) begin + main_sdram_bankmachine3_cmd_ready <= 1'd1; + end + if (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 2'd3))) begin + main_sdram_bankmachine3_cmd_ready <= 1'd1; + end +end +always @(*) begin + main_sdram_bankmachine4_cmd_ready <= 1'd0; + if (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 3'd4))) begin + main_sdram_bankmachine4_cmd_ready <= 1'd1; + end + if (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 3'd4))) begin + main_sdram_bankmachine4_cmd_ready <= 1'd1; + end +end +always @(*) begin + main_sdram_bankmachine5_cmd_ready <= 1'd0; + if (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 3'd5))) begin + main_sdram_bankmachine5_cmd_ready <= 1'd1; + end + if (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 3'd5))) begin + main_sdram_bankmachine5_cmd_ready <= 1'd1; + end +end +always @(*) begin + main_sdram_bankmachine6_cmd_ready <= 1'd0; + if (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 3'd6))) begin + main_sdram_bankmachine6_cmd_ready <= 1'd1; + end + if (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 3'd6))) begin + main_sdram_bankmachine6_cmd_ready <= 1'd1; + end +end +always @(*) begin + main_sdram_bankmachine7_cmd_ready <= 1'd0; + if (((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & (main_sdram_choose_cmd_grant == 3'd7))) begin + main_sdram_bankmachine7_cmd_ready <= 1'd1; + end + if (((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & (main_sdram_choose_req_grant == 3'd7))) begin + main_sdram_bankmachine7_cmd_ready <= 1'd1; + end +end +assign main_sdram_choose_req_ce = (main_sdram_choose_req_cmd_ready | (~main_sdram_choose_req_cmd_valid)); +assign main_sdram_dfi_p0_reset_n = 1'd1; +assign main_sdram_dfi_p0_cke = {1{main_sdram_steerer0}}; +assign main_sdram_dfi_p0_odt = {1{main_sdram_steerer1}}; +assign main_sdram_dfi_p1_reset_n = 1'd1; +assign main_sdram_dfi_p1_cke = {1{main_sdram_steerer2}}; +assign main_sdram_dfi_p1_odt = {1{main_sdram_steerer3}}; +assign main_sdram_dfi_p2_reset_n = 1'd1; +assign main_sdram_dfi_p2_cke = {1{main_sdram_steerer4}}; +assign main_sdram_dfi_p2_odt = {1{main_sdram_steerer5}}; +assign main_sdram_dfi_p3_reset_n = 1'd1; +assign main_sdram_dfi_p3_cke = {1{main_sdram_steerer6}}; +assign main_sdram_dfi_p3_odt = {1{main_sdram_steerer7}}; +assign main_sdram_tfawcon_count = ((main_sdram_tfawcon_window[0] + main_sdram_tfawcon_window[1]) + main_sdram_tfawcon_window[2]); +always @(*) begin + main_sdram_cmd_ready <= 1'd0; + main_sdram_choose_cmd_cmd_ready <= 1'd0; + main_sdram_choose_req_want_reads <= 1'd0; + main_sdram_choose_req_want_writes <= 1'd0; + main_sdram_en1 <= 1'd0; + main_sdram_choose_req_cmd_ready <= 1'd0; + main_sdram_steerer_sel2 <= 2'd0; + main_sdram_steerer_sel0 <= 2'd0; + main_sdram_steerer_sel1 <= 2'd0; + main_sdram_en0 <= 1'd0; + builder_multiplexer_next_state <= 4'd0; + main_sdram_choose_cmd_want_activates <= 1'd0; + main_sdram_steerer_sel3 <= 2'd0; + builder_multiplexer_next_state <= builder_multiplexer_state; + case (builder_multiplexer_state) + 1'd1: begin + main_sdram_en1 <= 1'd1; + main_sdram_choose_req_want_writes <= 1'd1; + if (1'd0) begin + main_sdram_choose_req_cmd_ready <= (main_sdram_cas_allowed & ((~((main_sdram_choose_req_cmd_payload_ras & (~main_sdram_choose_req_cmd_payload_cas)) & (~main_sdram_choose_req_cmd_payload_we))) | main_sdram_ras_allowed)); + end else begin + main_sdram_choose_cmd_want_activates <= main_sdram_ras_allowed; + main_sdram_choose_cmd_cmd_ready <= ((~((main_sdram_choose_cmd_cmd_payload_ras & (~main_sdram_choose_cmd_cmd_payload_cas)) & (~main_sdram_choose_cmd_cmd_payload_we))) | main_sdram_ras_allowed); + main_sdram_choose_req_cmd_ready <= main_sdram_cas_allowed; + end + main_sdram_steerer_sel0 <= 1'd0; + main_sdram_steerer_sel1 <= 1'd0; + main_sdram_steerer_sel2 <= 1'd1; + main_sdram_steerer_sel3 <= 2'd2; + if (main_sdram_read_available) begin + if (((~main_sdram_write_available) | main_sdram_max_time1)) begin + builder_multiplexer_next_state <= 2'd3; + end + end + if (main_sdram_go_to_refresh) begin + builder_multiplexer_next_state <= 2'd2; + end + end + 2'd2: begin + main_sdram_steerer_sel0 <= 2'd3; + main_sdram_cmd_ready <= 1'd1; + if (main_sdram_cmd_last) begin + builder_multiplexer_next_state <= 1'd0; + end + end + 2'd3: begin + if (main_sdram_twtrcon_ready) begin + builder_multiplexer_next_state <= 1'd0; + end + end + 3'd4: begin + builder_multiplexer_next_state <= 3'd5; + end + 3'd5: begin + builder_multiplexer_next_state <= 3'd6; + end + 3'd6: begin + builder_multiplexer_next_state <= 3'd7; + end + 3'd7: begin + builder_multiplexer_next_state <= 4'd8; + end + 4'd8: begin + builder_multiplexer_next_state <= 4'd9; + end + 4'd9: begin + builder_multiplexer_next_state <= 4'd10; + end + 4'd10: begin + builder_multiplexer_next_state <= 4'd11; + end + 4'd11: begin + builder_multiplexer_next_state <= 1'd1; + end + default: begin + main_sdram_en0 <= 1'd1; + main_sdram_choose_req_want_reads <= 1'd1; + if (1'd0) begin + main_sdram_choose_req_cmd_ready <= (main_sdram_cas_allowed & ((~((main_sdram_choose_req_cmd_payload_ras & (~main_sdram_choose_req_cmd_payload_cas)) & (~main_sdram_choose_req_cmd_payload_we))) | main_sdram_ras_allowed)); + end else begin + main_sdram_choose_cmd_want_activates <= main_sdram_ras_allowed; + main_sdram_choose_cmd_cmd_ready <= ((~((main_sdram_choose_cmd_cmd_payload_ras & (~main_sdram_choose_cmd_cmd_payload_cas)) & (~main_sdram_choose_cmd_cmd_payload_we))) | main_sdram_ras_allowed); + main_sdram_choose_req_cmd_ready <= main_sdram_cas_allowed; + end + main_sdram_steerer_sel0 <= 1'd0; + main_sdram_steerer_sel1 <= 1'd1; + main_sdram_steerer_sel2 <= 2'd2; + main_sdram_steerer_sel3 <= 1'd0; + if (main_sdram_write_available) begin + if (((~main_sdram_read_available) | main_sdram_max_time0)) begin + builder_multiplexer_next_state <= 3'd4; + end + end + if (main_sdram_go_to_refresh) begin + builder_multiplexer_next_state <= 2'd2; + end + end + endcase +end +assign builder_roundrobin0_request = {(((main_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid)}; +assign builder_roundrobin0_ce = ((~main_sdram_interface_bank0_valid) & (~main_sdram_interface_bank0_lock)); +assign main_sdram_interface_bank0_addr = builder_rhs_array_muxed12; +assign main_sdram_interface_bank0_we = builder_rhs_array_muxed13; +assign main_sdram_interface_bank0_valid = builder_rhs_array_muxed14; +assign builder_roundrobin1_request = {(((main_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid)}; +assign builder_roundrobin1_ce = ((~main_sdram_interface_bank1_valid) & (~main_sdram_interface_bank1_lock)); +assign main_sdram_interface_bank1_addr = builder_rhs_array_muxed15; +assign main_sdram_interface_bank1_we = builder_rhs_array_muxed16; +assign main_sdram_interface_bank1_valid = builder_rhs_array_muxed17; +assign builder_roundrobin2_request = {(((main_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid)}; +assign builder_roundrobin2_ce = ((~main_sdram_interface_bank2_valid) & (~main_sdram_interface_bank2_lock)); +assign main_sdram_interface_bank2_addr = builder_rhs_array_muxed18; +assign main_sdram_interface_bank2_we = builder_rhs_array_muxed19; +assign main_sdram_interface_bank2_valid = builder_rhs_array_muxed20; +assign builder_roundrobin3_request = {(((main_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid)}; +assign builder_roundrobin3_ce = ((~main_sdram_interface_bank3_valid) & (~main_sdram_interface_bank3_lock)); +assign main_sdram_interface_bank3_addr = builder_rhs_array_muxed21; +assign main_sdram_interface_bank3_we = builder_rhs_array_muxed22; +assign main_sdram_interface_bank3_valid = builder_rhs_array_muxed23; +assign builder_roundrobin4_request = {(((main_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid)}; +assign builder_roundrobin4_ce = ((~main_sdram_interface_bank4_valid) & (~main_sdram_interface_bank4_lock)); +assign main_sdram_interface_bank4_addr = builder_rhs_array_muxed24; +assign main_sdram_interface_bank4_we = builder_rhs_array_muxed25; +assign main_sdram_interface_bank4_valid = builder_rhs_array_muxed26; +assign builder_roundrobin5_request = {(((main_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid)}; +assign builder_roundrobin5_ce = ((~main_sdram_interface_bank5_valid) & (~main_sdram_interface_bank5_lock)); +assign main_sdram_interface_bank5_addr = builder_rhs_array_muxed27; +assign main_sdram_interface_bank5_we = builder_rhs_array_muxed28; +assign main_sdram_interface_bank5_valid = builder_rhs_array_muxed29; +assign builder_roundrobin6_request = {(((main_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid)}; +assign builder_roundrobin6_ce = ((~main_sdram_interface_bank6_valid) & (~main_sdram_interface_bank6_lock)); +assign main_sdram_interface_bank6_addr = builder_rhs_array_muxed30; +assign main_sdram_interface_bank6_we = builder_rhs_array_muxed31; +assign main_sdram_interface_bank6_valid = builder_rhs_array_muxed32; +assign builder_roundrobin7_request = {(((main_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_port_cmd_valid)}; +assign builder_roundrobin7_ce = ((~main_sdram_interface_bank7_valid) & (~main_sdram_interface_bank7_lock)); +assign main_sdram_interface_bank7_addr = builder_rhs_array_muxed33; +assign main_sdram_interface_bank7_we = builder_rhs_array_muxed34; +assign main_sdram_interface_bank7_valid = builder_rhs_array_muxed35; +assign main_port_cmd_ready = ((((((((1'd0 | (((builder_roundrobin0_grant == 1'd0) & ((main_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_sdram_interface_bank0_ready)) | (((builder_roundrobin1_grant == 1'd0) & ((main_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_sdram_interface_bank1_ready)) | (((builder_roundrobin2_grant == 1'd0) & ((main_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_sdram_interface_bank2_ready)) | (((builder_roundrobin3_grant == 1'd0) & ((main_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_sdram_interface_bank3_ready)) | (((builder_roundrobin4_grant == 1'd0) & ((main_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_sdram_interface_bank4_ready)) | (((builder_roundrobin5_grant == 1'd0) & ((main_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_sdram_interface_bank5_ready)) | (((builder_roundrobin6_grant == 1'd0) & ((main_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0)))))) & main_sdram_interface_bank6_ready)) | (((builder_roundrobin7_grant == 1'd0) & ((main_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0)))))) & main_sdram_interface_bank7_ready)); +assign main_port_wdata_ready = builder_new_master_wdata_ready2; +assign main_port_rdata_valid = builder_new_master_rdata_valid9; +always @(*) begin + main_sdram_interface_wdata <= 128'd0; + main_sdram_interface_wdata_we <= 16'd0; + case ({builder_new_master_wdata_ready2}) + 1'd1: begin + main_sdram_interface_wdata <= main_port_wdata_payload_data; + main_sdram_interface_wdata_we <= main_port_wdata_payload_we; + end + default: begin + main_sdram_interface_wdata <= 1'd0; + main_sdram_interface_wdata_we <= 1'd0; + end + endcase +end +assign main_port_rdata_payload_data = main_sdram_interface_rdata; +assign builder_roundrobin0_grant = 1'd0; +assign builder_roundrobin1_grant = 1'd0; +assign builder_roundrobin2_grant = 1'd0; +assign builder_roundrobin3_grant = 1'd0; +assign builder_roundrobin4_grant = 1'd0; +assign builder_roundrobin5_grant = 1'd0; +assign builder_roundrobin6_grant = 1'd0; +assign builder_roundrobin7_grant = 1'd0; +assign main_data_port_adr = main_interface0_wb_sdram_adr[10:2]; +always @(*) begin + main_data_port_dat_w <= 128'd0; + main_data_port_we <= 16'd0; + if (main_write_from_slave) begin + main_data_port_dat_w <= main_dat_r; + main_data_port_we <= {16{1'd1}}; + end else begin + main_data_port_dat_w <= {4{main_interface0_wb_sdram_dat_w}}; + if ((((main_interface0_wb_sdram_cyc & main_interface0_wb_sdram_stb) & main_interface0_wb_sdram_we) & main_interface0_wb_sdram_ack)) begin + main_data_port_we <= {({4{(main_interface0_wb_sdram_adr[1:0] == 1'd0)}} & main_interface0_wb_sdram_sel), ({4{(main_interface0_wb_sdram_adr[1:0] == 1'd1)}} & main_interface0_wb_sdram_sel), ({4{(main_interface0_wb_sdram_adr[1:0] == 2'd2)}} & main_interface0_wb_sdram_sel), ({4{(main_interface0_wb_sdram_adr[1:0] == 2'd3)}} & main_interface0_wb_sdram_sel)}; + end + end +end +assign main_dat_w = main_data_port_dat_r; +assign main_sel = 16'd65535; +always @(*) begin + main_interface0_wb_sdram_dat_r <= 32'd0; + case (main_adr_offset_r) + 1'd0: begin + main_interface0_wb_sdram_dat_r <= main_data_port_dat_r[127:96]; + end + 1'd1: begin + main_interface0_wb_sdram_dat_r <= main_data_port_dat_r[95:64]; + end + 2'd2: begin + main_interface0_wb_sdram_dat_r <= main_data_port_dat_r[63:32]; + end + default: begin + main_interface0_wb_sdram_dat_r <= main_data_port_dat_r[31:0]; + end + endcase +end +assign {main_tag_do_dirty, main_tag_do_tag} = main_tag_port_dat_r; +assign main_tag_port_dat_w = {main_tag_di_dirty, main_tag_di_tag}; +assign main_tag_port_adr = main_interface0_wb_sdram_adr[10:2]; +assign main_tag_di_tag = main_interface0_wb_sdram_adr[29:11]; +assign main_adr = {main_tag_do_tag, main_interface0_wb_sdram_adr[10:2]}; +always @(*) begin + builder_fullmemorywe_next_state <= 3'd0; + main_tag_di_dirty <= 1'd0; + main_word_clr <= 1'd0; + main_interface0_wb_sdram_ack <= 1'd0; + main_word_inc <= 1'd0; + main_write_from_slave <= 1'd0; + main_cyc <= 1'd0; + main_stb <= 1'd0; + main_tag_port_we <= 1'd0; + main_we <= 1'd0; + builder_fullmemorywe_next_state <= builder_fullmemorywe_state; + case (builder_fullmemorywe_state) + 1'd1: begin + main_word_clr <= 1'd1; + if ((main_tag_do_tag == main_interface0_wb_sdram_adr[29:11])) begin + main_interface0_wb_sdram_ack <= 1'd1; + if (main_interface0_wb_sdram_we) begin + main_tag_di_dirty <= 1'd1; + main_tag_port_we <= 1'd1; + end + builder_fullmemorywe_next_state <= 1'd0; + end else begin + if (main_tag_do_dirty) begin + builder_fullmemorywe_next_state <= 2'd2; + end else begin + builder_fullmemorywe_next_state <= 2'd3; + end + end + end + 2'd2: begin + main_stb <= 1'd1; + main_cyc <= 1'd1; + main_we <= 1'd1; + if (main_ack) begin + main_word_inc <= 1'd1; + if (1'd1) begin + builder_fullmemorywe_next_state <= 2'd3; + end + end + end + 2'd3: begin + main_tag_port_we <= 1'd1; + main_word_clr <= 1'd1; + builder_fullmemorywe_next_state <= 3'd4; + end + 3'd4: begin + main_stb <= 1'd1; + main_cyc <= 1'd1; + main_we <= 1'd0; + if (main_ack) begin + main_write_from_slave <= 1'd1; + main_word_inc <= 1'd1; + if (1'd1) begin + builder_fullmemorywe_next_state <= 1'd1; + end else begin + builder_fullmemorywe_next_state <= 3'd4; + end + end + end + default: begin + if ((main_interface0_wb_sdram_cyc & main_interface0_wb_sdram_stb)) begin + builder_fullmemorywe_next_state <= 1'd1; + end + end + endcase +end +assign main_port_cmd_payload_addr = (main_adr - 1'd0); +assign main_port_wdata_payload_we = main_sel; +assign main_port_wdata_payload_data = main_dat_w; +assign main_dat_r = main_port_rdata_payload_data; +always @(*) begin + main_port_rdata_ready <= 1'd0; + main_port_wdata_valid <= 1'd0; + main_port_cmd_valid <= 1'd0; + builder_litedramwishbone2native_next_state <= 2'd0; + main_ack <= 1'd0; + main_port_cmd_payload_we <= 1'd0; + builder_litedramwishbone2native_next_state <= builder_litedramwishbone2native_state; + case (builder_litedramwishbone2native_state) + 1'd1: begin + main_port_wdata_valid <= 1'd1; + if (main_port_wdata_ready) begin + main_ack <= 1'd1; + builder_litedramwishbone2native_next_state <= 1'd0; + end + end + 2'd2: begin + main_port_rdata_ready <= 1'd1; + if (main_port_rdata_valid) begin + main_ack <= 1'd1; + builder_litedramwishbone2native_next_state <= 1'd0; + end + end + default: begin + main_port_cmd_valid <= (main_cyc & main_stb); + main_port_cmd_payload_we <= main_we; + if ((main_port_cmd_valid & main_port_cmd_ready)) begin + if (main_we) begin + builder_litedramwishbone2native_next_state <= 1'd1; + end else begin + builder_litedramwishbone2native_next_state <= 2'd2; + end + end + end + endcase +end +assign main_interface0_wb_sdram_adr = builder_rhs_array_muxed36; +assign main_interface0_wb_sdram_dat_w = builder_rhs_array_muxed37; +assign main_interface0_wb_sdram_sel = builder_rhs_array_muxed38; +assign main_interface0_wb_sdram_cyc = builder_rhs_array_muxed39; +assign main_interface0_wb_sdram_stb = builder_rhs_array_muxed40; +assign main_interface0_wb_sdram_we = builder_rhs_array_muxed41; +assign main_interface0_wb_sdram_cti = builder_rhs_array_muxed42; +assign main_interface0_wb_sdram_bte = builder_rhs_array_muxed43; +assign main_interface1_wb_sdram_dat_r = main_interface0_wb_sdram_dat_r; +assign main_interface1_wb_sdram_ack = (main_interface0_wb_sdram_ack & (builder_wb_sdram_con_grant == 1'd0)); +assign main_interface1_wb_sdram_err = (main_interface0_wb_sdram_err & (builder_wb_sdram_con_grant == 1'd0)); +assign builder_wb_sdram_con_request = {main_interface1_wb_sdram_cyc}; +assign builder_wb_sdram_con_grant = 1'd0; +assign builder_minsoc_shared_adr = builder_rhs_array_muxed44; +assign builder_minsoc_shared_dat_w = builder_rhs_array_muxed45; +assign builder_minsoc_shared_sel = builder_rhs_array_muxed46; +assign builder_minsoc_shared_cyc = builder_rhs_array_muxed47; +assign builder_minsoc_shared_stb = builder_rhs_array_muxed48; +assign builder_minsoc_shared_we = builder_rhs_array_muxed49; +assign builder_minsoc_shared_cti = builder_rhs_array_muxed50; +assign builder_minsoc_shared_bte = builder_rhs_array_muxed51; +assign main_interface0_soc_bus_dat_r = builder_minsoc_shared_dat_r; +assign main_interface1_soc_bus_dat_r = builder_minsoc_shared_dat_r; +assign main_interface0_soc_bus_ack = (builder_minsoc_shared_ack & (builder_minsoc_grant == 1'd0)); +assign main_interface1_soc_bus_ack = (builder_minsoc_shared_ack & (builder_minsoc_grant == 1'd1)); +assign main_interface0_soc_bus_err = (builder_minsoc_shared_err & (builder_minsoc_grant == 1'd0)); +assign main_interface1_soc_bus_err = (builder_minsoc_shared_err & (builder_minsoc_grant == 1'd1)); +assign builder_minsoc_request = {main_interface1_soc_bus_cyc, main_interface0_soc_bus_cyc}; +always @(*) begin + builder_minsoc_slave_sel <= 4'd0; + builder_minsoc_slave_sel[0] <= (builder_minsoc_shared_adr[28:13] == 1'd0); + builder_minsoc_slave_sel[1] <= (builder_minsoc_shared_adr[28:13] == 10'd512); + builder_minsoc_slave_sel[2] <= (builder_minsoc_shared_adr[28:22] == 2'd2); + builder_minsoc_slave_sel[3] <= (builder_minsoc_shared_adr[28:26] == 3'd4); +end +assign main_rom_bus_adr = builder_minsoc_shared_adr; +assign main_rom_bus_dat_w = builder_minsoc_shared_dat_w; +assign main_rom_bus_sel = builder_minsoc_shared_sel; +assign main_rom_bus_stb = builder_minsoc_shared_stb; +assign main_rom_bus_we = builder_minsoc_shared_we; +assign main_rom_bus_cti = builder_minsoc_shared_cti; +assign main_rom_bus_bte = builder_minsoc_shared_bte; +assign main_sram_bus_adr = builder_minsoc_shared_adr; +assign main_sram_bus_dat_w = builder_minsoc_shared_dat_w; +assign main_sram_bus_sel = builder_minsoc_shared_sel; +assign main_sram_bus_stb = builder_minsoc_shared_stb; +assign main_sram_bus_we = builder_minsoc_shared_we; +assign main_sram_bus_cti = builder_minsoc_shared_cti; +assign main_sram_bus_bte = builder_minsoc_shared_bte; +assign main_bus_wishbone_adr = builder_minsoc_shared_adr; +assign main_bus_wishbone_dat_w = builder_minsoc_shared_dat_w; +assign main_bus_wishbone_sel = builder_minsoc_shared_sel; +assign main_bus_wishbone_stb = builder_minsoc_shared_stb; +assign main_bus_wishbone_we = builder_minsoc_shared_we; +assign main_bus_wishbone_cti = builder_minsoc_shared_cti; +assign main_bus_wishbone_bte = builder_minsoc_shared_bte; +assign main_interface1_wb_sdram_adr = builder_minsoc_shared_adr; +assign main_interface1_wb_sdram_dat_w = builder_minsoc_shared_dat_w; +assign main_interface1_wb_sdram_sel = builder_minsoc_shared_sel; +assign main_interface1_wb_sdram_stb = builder_minsoc_shared_stb; +assign main_interface1_wb_sdram_we = builder_minsoc_shared_we; +assign main_interface1_wb_sdram_cti = builder_minsoc_shared_cti; +assign main_interface1_wb_sdram_bte = builder_minsoc_shared_bte; +assign main_rom_bus_cyc = (builder_minsoc_shared_cyc & builder_minsoc_slave_sel[0]); +assign main_sram_bus_cyc = (builder_minsoc_shared_cyc & builder_minsoc_slave_sel[1]); +assign main_bus_wishbone_cyc = (builder_minsoc_shared_cyc & builder_minsoc_slave_sel[2]); +assign main_interface1_wb_sdram_cyc = (builder_minsoc_shared_cyc & builder_minsoc_slave_sel[3]); +assign builder_minsoc_shared_err = (((main_rom_bus_err | main_sram_bus_err) | main_bus_wishbone_err) | main_interface1_wb_sdram_err); +assign builder_minsoc_wait = ((builder_minsoc_shared_stb & builder_minsoc_shared_cyc) & (~builder_minsoc_shared_ack)); +always @(*) begin + builder_minsoc_shared_dat_r <= 32'd0; + builder_minsoc_error <= 1'd0; + builder_minsoc_shared_ack <= 1'd0; + builder_minsoc_shared_ack <= (((main_rom_bus_ack | main_sram_bus_ack) | main_bus_wishbone_ack) | main_interface1_wb_sdram_ack); + builder_minsoc_shared_dat_r <= (((({32{builder_minsoc_slave_sel_r[0]}} & main_rom_bus_dat_r) | ({32{builder_minsoc_slave_sel_r[1]}} & main_sram_bus_dat_r)) | ({32{builder_minsoc_slave_sel_r[2]}} & main_bus_wishbone_dat_r)) | ({32{builder_minsoc_slave_sel_r[3]}} & main_interface1_wb_sdram_dat_r)); + if (builder_minsoc_done) begin + builder_minsoc_shared_dat_r <= 32'd4294967295; + builder_minsoc_shared_ack <= 1'd1; + builder_minsoc_error <= 1'd1; + end +end +assign builder_minsoc_done = (builder_minsoc_count == 1'd0); +assign builder_minsoc_csrbank0_sel = (builder_minsoc_interface0_bank_bus_adr[13:9] == 1'd0); +assign main_ctrl_reset_reset_r = builder_minsoc_interface0_bank_bus_dat_w[0]; +assign main_ctrl_reset_reset_re = ((builder_minsoc_csrbank0_sel & builder_minsoc_interface0_bank_bus_we) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 1'd0)); +assign main_ctrl_reset_reset_we = ((builder_minsoc_csrbank0_sel & (~builder_minsoc_interface0_bank_bus_we)) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 1'd0)); +assign builder_minsoc_csrbank0_scratch3_r = builder_minsoc_interface0_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank0_scratch3_re = ((builder_minsoc_csrbank0_sel & builder_minsoc_interface0_bank_bus_we) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 1'd1)); +assign builder_minsoc_csrbank0_scratch3_we = ((builder_minsoc_csrbank0_sel & (~builder_minsoc_interface0_bank_bus_we)) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 1'd1)); +assign builder_minsoc_csrbank0_scratch2_r = builder_minsoc_interface0_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank0_scratch2_re = ((builder_minsoc_csrbank0_sel & builder_minsoc_interface0_bank_bus_we) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 2'd2)); +assign builder_minsoc_csrbank0_scratch2_we = ((builder_minsoc_csrbank0_sel & (~builder_minsoc_interface0_bank_bus_we)) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 2'd2)); +assign builder_minsoc_csrbank0_scratch1_r = builder_minsoc_interface0_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank0_scratch1_re = ((builder_minsoc_csrbank0_sel & builder_minsoc_interface0_bank_bus_we) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 2'd3)); +assign builder_minsoc_csrbank0_scratch1_we = ((builder_minsoc_csrbank0_sel & (~builder_minsoc_interface0_bank_bus_we)) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 2'd3)); +assign builder_minsoc_csrbank0_scratch0_r = builder_minsoc_interface0_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank0_scratch0_re = ((builder_minsoc_csrbank0_sel & builder_minsoc_interface0_bank_bus_we) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 3'd4)); +assign builder_minsoc_csrbank0_scratch0_we = ((builder_minsoc_csrbank0_sel & (~builder_minsoc_interface0_bank_bus_we)) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 3'd4)); +assign builder_minsoc_csrbank0_bus_errors3_r = builder_minsoc_interface0_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank0_bus_errors3_re = ((builder_minsoc_csrbank0_sel & builder_minsoc_interface0_bank_bus_we) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 3'd5)); +assign builder_minsoc_csrbank0_bus_errors3_we = ((builder_minsoc_csrbank0_sel & (~builder_minsoc_interface0_bank_bus_we)) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 3'd5)); +assign builder_minsoc_csrbank0_bus_errors2_r = builder_minsoc_interface0_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank0_bus_errors2_re = ((builder_minsoc_csrbank0_sel & builder_minsoc_interface0_bank_bus_we) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 3'd6)); +assign builder_minsoc_csrbank0_bus_errors2_we = ((builder_minsoc_csrbank0_sel & (~builder_minsoc_interface0_bank_bus_we)) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 3'd6)); +assign builder_minsoc_csrbank0_bus_errors1_r = builder_minsoc_interface0_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank0_bus_errors1_re = ((builder_minsoc_csrbank0_sel & builder_minsoc_interface0_bank_bus_we) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 3'd7)); +assign builder_minsoc_csrbank0_bus_errors1_we = ((builder_minsoc_csrbank0_sel & (~builder_minsoc_interface0_bank_bus_we)) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 3'd7)); +assign builder_minsoc_csrbank0_bus_errors0_r = builder_minsoc_interface0_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank0_bus_errors0_re = ((builder_minsoc_csrbank0_sel & builder_minsoc_interface0_bank_bus_we) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 4'd8)); +assign builder_minsoc_csrbank0_bus_errors0_we = ((builder_minsoc_csrbank0_sel & (~builder_minsoc_interface0_bank_bus_we)) & (builder_minsoc_interface0_bank_bus_adr[3:0] == 4'd8)); +assign builder_minsoc_csrbank0_scratch3_w = main_ctrl_storage[31:24]; +assign builder_minsoc_csrbank0_scratch2_w = main_ctrl_storage[23:16]; +assign builder_minsoc_csrbank0_scratch1_w = main_ctrl_storage[15:8]; +assign builder_minsoc_csrbank0_scratch0_w = main_ctrl_storage[7:0]; +assign builder_minsoc_csrbank0_bus_errors3_w = main_ctrl_bus_errors_status[31:24]; +assign builder_minsoc_csrbank0_bus_errors2_w = main_ctrl_bus_errors_status[23:16]; +assign builder_minsoc_csrbank0_bus_errors1_w = main_ctrl_bus_errors_status[15:8]; +assign builder_minsoc_csrbank0_bus_errors0_w = main_ctrl_bus_errors_status[7:0]; +assign main_ctrl_bus_errors_we = builder_minsoc_csrbank0_bus_errors0_we; +assign builder_minsoc_csrbank1_sel = (builder_minsoc_interface1_bank_bus_adr[13:9] == 3'd5); +assign builder_minsoc_csrbank1_half_sys8x_taps0_r = builder_minsoc_interface1_bank_bus_dat_w[4:0]; +assign builder_minsoc_csrbank1_half_sys8x_taps0_re = ((builder_minsoc_csrbank1_sel & builder_minsoc_interface1_bank_bus_we) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 1'd0)); +assign builder_minsoc_csrbank1_half_sys8x_taps0_we = ((builder_minsoc_csrbank1_sel & (~builder_minsoc_interface1_bank_bus_we)) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 1'd0)); +assign main_a7ddrphy_cdly_rst_r = builder_minsoc_interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_cdly_rst_re = ((builder_minsoc_csrbank1_sel & builder_minsoc_interface1_bank_bus_we) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 1'd1)); +assign main_a7ddrphy_cdly_rst_we = ((builder_minsoc_csrbank1_sel & (~builder_minsoc_interface1_bank_bus_we)) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 1'd1)); +assign main_a7ddrphy_cdly_inc_r = builder_minsoc_interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_cdly_inc_re = ((builder_minsoc_csrbank1_sel & builder_minsoc_interface1_bank_bus_we) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 2'd2)); +assign main_a7ddrphy_cdly_inc_we = ((builder_minsoc_csrbank1_sel & (~builder_minsoc_interface1_bank_bus_we)) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 2'd2)); +assign builder_minsoc_csrbank1_dly_sel0_r = builder_minsoc_interface1_bank_bus_dat_w[1:0]; +assign builder_minsoc_csrbank1_dly_sel0_re = ((builder_minsoc_csrbank1_sel & builder_minsoc_interface1_bank_bus_we) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 2'd3)); +assign builder_minsoc_csrbank1_dly_sel0_we = ((builder_minsoc_csrbank1_sel & (~builder_minsoc_interface1_bank_bus_we)) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 2'd3)); +assign main_a7ddrphy_rdly_dq_rst_r = builder_minsoc_interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_rdly_dq_rst_re = ((builder_minsoc_csrbank1_sel & builder_minsoc_interface1_bank_bus_we) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 3'd4)); +assign main_a7ddrphy_rdly_dq_rst_we = ((builder_minsoc_csrbank1_sel & (~builder_minsoc_interface1_bank_bus_we)) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 3'd4)); +assign main_a7ddrphy_rdly_dq_inc_r = builder_minsoc_interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_rdly_dq_inc_re = ((builder_minsoc_csrbank1_sel & builder_minsoc_interface1_bank_bus_we) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 3'd5)); +assign main_a7ddrphy_rdly_dq_inc_we = ((builder_minsoc_csrbank1_sel & (~builder_minsoc_interface1_bank_bus_we)) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 3'd5)); +assign main_a7ddrphy_rdly_dq_bitslip_rst_r = builder_minsoc_interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_rdly_dq_bitslip_rst_re = ((builder_minsoc_csrbank1_sel & builder_minsoc_interface1_bank_bus_we) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 3'd6)); +assign main_a7ddrphy_rdly_dq_bitslip_rst_we = ((builder_minsoc_csrbank1_sel & (~builder_minsoc_interface1_bank_bus_we)) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 3'd6)); +assign main_a7ddrphy_rdly_dq_bitslip_r = builder_minsoc_interface1_bank_bus_dat_w[0]; +assign main_a7ddrphy_rdly_dq_bitslip_re = ((builder_minsoc_csrbank1_sel & builder_minsoc_interface1_bank_bus_we) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 3'd7)); +assign main_a7ddrphy_rdly_dq_bitslip_we = ((builder_minsoc_csrbank1_sel & (~builder_minsoc_interface1_bank_bus_we)) & (builder_minsoc_interface1_bank_bus_adr[2:0] == 3'd7)); +assign builder_minsoc_csrbank1_half_sys8x_taps0_w = main_a7ddrphy_half_sys8x_taps_storage[4:0]; +assign builder_minsoc_csrbank1_dly_sel0_w = main_a7ddrphy_dly_sel_storage[1:0]; +assign builder_minsoc_csrbank2_sel = (builder_minsoc_interface2_bank_bus_adr[13:9] == 4'd8); +assign builder_minsoc_csrbank2_dfii_control0_r = builder_minsoc_interface2_bank_bus_dat_w[3:0]; +assign builder_minsoc_csrbank2_dfii_control0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 1'd0)); +assign builder_minsoc_csrbank2_dfii_control0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 1'd0)); +assign builder_minsoc_csrbank2_dfii_pi0_command0_r = builder_minsoc_interface2_bank_bus_dat_w[5:0]; +assign builder_minsoc_csrbank2_dfii_pi0_command0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 1'd1)); +assign builder_minsoc_csrbank2_dfii_pi0_command0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 1'd1)); +assign main_sdram_phaseinjector0_command_issue_r = builder_minsoc_interface2_bank_bus_dat_w[0]; +assign main_sdram_phaseinjector0_command_issue_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 2'd2)); +assign main_sdram_phaseinjector0_command_issue_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 2'd2)); +assign builder_minsoc_csrbank2_dfii_pi0_address1_r = builder_minsoc_interface2_bank_bus_dat_w[5:0]; +assign builder_minsoc_csrbank2_dfii_pi0_address1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 2'd3)); +assign builder_minsoc_csrbank2_dfii_pi0_address1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 2'd3)); +assign builder_minsoc_csrbank2_dfii_pi0_address0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi0_address0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 3'd4)); +assign builder_minsoc_csrbank2_dfii_pi0_address0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 3'd4)); +assign builder_minsoc_csrbank2_dfii_pi0_baddress0_r = builder_minsoc_interface2_bank_bus_dat_w[2:0]; +assign builder_minsoc_csrbank2_dfii_pi0_baddress0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 3'd5)); +assign builder_minsoc_csrbank2_dfii_pi0_baddress0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 3'd5)); +assign builder_minsoc_csrbank2_dfii_pi0_wrdata3_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi0_wrdata3_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 3'd6)); +assign builder_minsoc_csrbank2_dfii_pi0_wrdata3_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 3'd6)); +assign builder_minsoc_csrbank2_dfii_pi0_wrdata2_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi0_wrdata2_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 3'd7)); +assign builder_minsoc_csrbank2_dfii_pi0_wrdata2_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 3'd7)); +assign builder_minsoc_csrbank2_dfii_pi0_wrdata1_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi0_wrdata1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd8)); +assign builder_minsoc_csrbank2_dfii_pi0_wrdata1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd8)); +assign builder_minsoc_csrbank2_dfii_pi0_wrdata0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi0_wrdata0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd9)); +assign builder_minsoc_csrbank2_dfii_pi0_wrdata0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd9)); +assign builder_minsoc_csrbank2_dfii_pi0_rddata3_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi0_rddata3_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd10)); +assign builder_minsoc_csrbank2_dfii_pi0_rddata3_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd10)); +assign builder_minsoc_csrbank2_dfii_pi0_rddata2_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi0_rddata2_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd11)); +assign builder_minsoc_csrbank2_dfii_pi0_rddata2_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd11)); +assign builder_minsoc_csrbank2_dfii_pi0_rddata1_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi0_rddata1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd12)); +assign builder_minsoc_csrbank2_dfii_pi0_rddata1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd12)); +assign builder_minsoc_csrbank2_dfii_pi0_rddata0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi0_rddata0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd13)); +assign builder_minsoc_csrbank2_dfii_pi0_rddata0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd13)); +assign builder_minsoc_csrbank2_dfii_pi1_command0_r = builder_minsoc_interface2_bank_bus_dat_w[5:0]; +assign builder_minsoc_csrbank2_dfii_pi1_command0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd14)); +assign builder_minsoc_csrbank2_dfii_pi1_command0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd14)); +assign main_sdram_phaseinjector1_command_issue_r = builder_minsoc_interface2_bank_bus_dat_w[0]; +assign main_sdram_phaseinjector1_command_issue_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd15)); +assign main_sdram_phaseinjector1_command_issue_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 4'd15)); +assign builder_minsoc_csrbank2_dfii_pi1_address1_r = builder_minsoc_interface2_bank_bus_dat_w[5:0]; +assign builder_minsoc_csrbank2_dfii_pi1_address1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd16)); +assign builder_minsoc_csrbank2_dfii_pi1_address1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd16)); +assign builder_minsoc_csrbank2_dfii_pi1_address0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi1_address0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd17)); +assign builder_minsoc_csrbank2_dfii_pi1_address0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd17)); +assign builder_minsoc_csrbank2_dfii_pi1_baddress0_r = builder_minsoc_interface2_bank_bus_dat_w[2:0]; +assign builder_minsoc_csrbank2_dfii_pi1_baddress0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd18)); +assign builder_minsoc_csrbank2_dfii_pi1_baddress0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd18)); +assign builder_minsoc_csrbank2_dfii_pi1_wrdata3_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi1_wrdata3_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd19)); +assign builder_minsoc_csrbank2_dfii_pi1_wrdata3_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd19)); +assign builder_minsoc_csrbank2_dfii_pi1_wrdata2_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi1_wrdata2_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd20)); +assign builder_minsoc_csrbank2_dfii_pi1_wrdata2_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd20)); +assign builder_minsoc_csrbank2_dfii_pi1_wrdata1_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi1_wrdata1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd21)); +assign builder_minsoc_csrbank2_dfii_pi1_wrdata1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd21)); +assign builder_minsoc_csrbank2_dfii_pi1_wrdata0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi1_wrdata0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd22)); +assign builder_minsoc_csrbank2_dfii_pi1_wrdata0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd22)); +assign builder_minsoc_csrbank2_dfii_pi1_rddata3_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi1_rddata3_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd23)); +assign builder_minsoc_csrbank2_dfii_pi1_rddata3_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd23)); +assign builder_minsoc_csrbank2_dfii_pi1_rddata2_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi1_rddata2_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd24)); +assign builder_minsoc_csrbank2_dfii_pi1_rddata2_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd24)); +assign builder_minsoc_csrbank2_dfii_pi1_rddata1_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi1_rddata1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd25)); +assign builder_minsoc_csrbank2_dfii_pi1_rddata1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd25)); +assign builder_minsoc_csrbank2_dfii_pi1_rddata0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi1_rddata0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd26)); +assign builder_minsoc_csrbank2_dfii_pi1_rddata0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd26)); +assign builder_minsoc_csrbank2_dfii_pi2_command0_r = builder_minsoc_interface2_bank_bus_dat_w[5:0]; +assign builder_minsoc_csrbank2_dfii_pi2_command0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd27)); +assign builder_minsoc_csrbank2_dfii_pi2_command0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd27)); +assign main_sdram_phaseinjector2_command_issue_r = builder_minsoc_interface2_bank_bus_dat_w[0]; +assign main_sdram_phaseinjector2_command_issue_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd28)); +assign main_sdram_phaseinjector2_command_issue_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd28)); +assign builder_minsoc_csrbank2_dfii_pi2_address1_r = builder_minsoc_interface2_bank_bus_dat_w[5:0]; +assign builder_minsoc_csrbank2_dfii_pi2_address1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd29)); +assign builder_minsoc_csrbank2_dfii_pi2_address1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd29)); +assign builder_minsoc_csrbank2_dfii_pi2_address0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi2_address0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd30)); +assign builder_minsoc_csrbank2_dfii_pi2_address0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd30)); +assign builder_minsoc_csrbank2_dfii_pi2_baddress0_r = builder_minsoc_interface2_bank_bus_dat_w[2:0]; +assign builder_minsoc_csrbank2_dfii_pi2_baddress0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd31)); +assign builder_minsoc_csrbank2_dfii_pi2_baddress0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 5'd31)); +assign builder_minsoc_csrbank2_dfii_pi2_wrdata3_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi2_wrdata3_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd32)); +assign builder_minsoc_csrbank2_dfii_pi2_wrdata3_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd32)); +assign builder_minsoc_csrbank2_dfii_pi2_wrdata2_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi2_wrdata2_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd33)); +assign builder_minsoc_csrbank2_dfii_pi2_wrdata2_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd33)); +assign builder_minsoc_csrbank2_dfii_pi2_wrdata1_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi2_wrdata1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd34)); +assign builder_minsoc_csrbank2_dfii_pi2_wrdata1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd34)); +assign builder_minsoc_csrbank2_dfii_pi2_wrdata0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi2_wrdata0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd35)); +assign builder_minsoc_csrbank2_dfii_pi2_wrdata0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd35)); +assign builder_minsoc_csrbank2_dfii_pi2_rddata3_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi2_rddata3_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd36)); +assign builder_minsoc_csrbank2_dfii_pi2_rddata3_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd36)); +assign builder_minsoc_csrbank2_dfii_pi2_rddata2_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi2_rddata2_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd37)); +assign builder_minsoc_csrbank2_dfii_pi2_rddata2_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd37)); +assign builder_minsoc_csrbank2_dfii_pi2_rddata1_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi2_rddata1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd38)); +assign builder_minsoc_csrbank2_dfii_pi2_rddata1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd38)); +assign builder_minsoc_csrbank2_dfii_pi2_rddata0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi2_rddata0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd39)); +assign builder_minsoc_csrbank2_dfii_pi2_rddata0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd39)); +assign builder_minsoc_csrbank2_dfii_pi3_command0_r = builder_minsoc_interface2_bank_bus_dat_w[5:0]; +assign builder_minsoc_csrbank2_dfii_pi3_command0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd40)); +assign builder_minsoc_csrbank2_dfii_pi3_command0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd40)); +assign main_sdram_phaseinjector3_command_issue_r = builder_minsoc_interface2_bank_bus_dat_w[0]; +assign main_sdram_phaseinjector3_command_issue_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd41)); +assign main_sdram_phaseinjector3_command_issue_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd41)); +assign builder_minsoc_csrbank2_dfii_pi3_address1_r = builder_minsoc_interface2_bank_bus_dat_w[5:0]; +assign builder_minsoc_csrbank2_dfii_pi3_address1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd42)); +assign builder_minsoc_csrbank2_dfii_pi3_address1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd42)); +assign builder_minsoc_csrbank2_dfii_pi3_address0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi3_address0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd43)); +assign builder_minsoc_csrbank2_dfii_pi3_address0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd43)); +assign builder_minsoc_csrbank2_dfii_pi3_baddress0_r = builder_minsoc_interface2_bank_bus_dat_w[2:0]; +assign builder_minsoc_csrbank2_dfii_pi3_baddress0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd44)); +assign builder_minsoc_csrbank2_dfii_pi3_baddress0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd44)); +assign builder_minsoc_csrbank2_dfii_pi3_wrdata3_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi3_wrdata3_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd45)); +assign builder_minsoc_csrbank2_dfii_pi3_wrdata3_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd45)); +assign builder_minsoc_csrbank2_dfii_pi3_wrdata2_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi3_wrdata2_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd46)); +assign builder_minsoc_csrbank2_dfii_pi3_wrdata2_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd46)); +assign builder_minsoc_csrbank2_dfii_pi3_wrdata1_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi3_wrdata1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd47)); +assign builder_minsoc_csrbank2_dfii_pi3_wrdata1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd47)); +assign builder_minsoc_csrbank2_dfii_pi3_wrdata0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi3_wrdata0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd48)); +assign builder_minsoc_csrbank2_dfii_pi3_wrdata0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd48)); +assign builder_minsoc_csrbank2_dfii_pi3_rddata3_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi3_rddata3_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd49)); +assign builder_minsoc_csrbank2_dfii_pi3_rddata3_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd49)); +assign builder_minsoc_csrbank2_dfii_pi3_rddata2_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi3_rddata2_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd50)); +assign builder_minsoc_csrbank2_dfii_pi3_rddata2_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd50)); +assign builder_minsoc_csrbank2_dfii_pi3_rddata1_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi3_rddata1_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd51)); +assign builder_minsoc_csrbank2_dfii_pi3_rddata1_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd51)); +assign builder_minsoc_csrbank2_dfii_pi3_rddata0_r = builder_minsoc_interface2_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank2_dfii_pi3_rddata0_re = ((builder_minsoc_csrbank2_sel & builder_minsoc_interface2_bank_bus_we) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd52)); +assign builder_minsoc_csrbank2_dfii_pi3_rddata0_we = ((builder_minsoc_csrbank2_sel & (~builder_minsoc_interface2_bank_bus_we)) & (builder_minsoc_interface2_bank_bus_adr[5:0] == 6'd52)); +assign builder_minsoc_csrbank2_dfii_control0_w = main_sdram_storage[3:0]; +assign builder_minsoc_csrbank2_dfii_pi0_command0_w = main_sdram_phaseinjector0_command_storage[5:0]; +assign builder_minsoc_csrbank2_dfii_pi0_address1_w = main_sdram_phaseinjector0_address_storage[13:8]; +assign builder_minsoc_csrbank2_dfii_pi0_address0_w = main_sdram_phaseinjector0_address_storage[7:0]; +assign builder_minsoc_csrbank2_dfii_pi0_baddress0_w = main_sdram_phaseinjector0_baddress_storage[2:0]; +assign builder_minsoc_csrbank2_dfii_pi0_wrdata3_w = main_sdram_phaseinjector0_wrdata_storage[31:24]; +assign builder_minsoc_csrbank2_dfii_pi0_wrdata2_w = main_sdram_phaseinjector0_wrdata_storage[23:16]; +assign builder_minsoc_csrbank2_dfii_pi0_wrdata1_w = main_sdram_phaseinjector0_wrdata_storage[15:8]; +assign builder_minsoc_csrbank2_dfii_pi0_wrdata0_w = main_sdram_phaseinjector0_wrdata_storage[7:0]; +assign builder_minsoc_csrbank2_dfii_pi0_rddata3_w = main_sdram_phaseinjector0_status[31:24]; +assign builder_minsoc_csrbank2_dfii_pi0_rddata2_w = main_sdram_phaseinjector0_status[23:16]; +assign builder_minsoc_csrbank2_dfii_pi0_rddata1_w = main_sdram_phaseinjector0_status[15:8]; +assign builder_minsoc_csrbank2_dfii_pi0_rddata0_w = main_sdram_phaseinjector0_status[7:0]; +assign main_sdram_phaseinjector0_we = builder_minsoc_csrbank2_dfii_pi0_rddata0_we; +assign builder_minsoc_csrbank2_dfii_pi1_command0_w = main_sdram_phaseinjector1_command_storage[5:0]; +assign builder_minsoc_csrbank2_dfii_pi1_address1_w = main_sdram_phaseinjector1_address_storage[13:8]; +assign builder_minsoc_csrbank2_dfii_pi1_address0_w = main_sdram_phaseinjector1_address_storage[7:0]; +assign builder_minsoc_csrbank2_dfii_pi1_baddress0_w = main_sdram_phaseinjector1_baddress_storage[2:0]; +assign builder_minsoc_csrbank2_dfii_pi1_wrdata3_w = main_sdram_phaseinjector1_wrdata_storage[31:24]; +assign builder_minsoc_csrbank2_dfii_pi1_wrdata2_w = main_sdram_phaseinjector1_wrdata_storage[23:16]; +assign builder_minsoc_csrbank2_dfii_pi1_wrdata1_w = main_sdram_phaseinjector1_wrdata_storage[15:8]; +assign builder_minsoc_csrbank2_dfii_pi1_wrdata0_w = main_sdram_phaseinjector1_wrdata_storage[7:0]; +assign builder_minsoc_csrbank2_dfii_pi1_rddata3_w = main_sdram_phaseinjector1_status[31:24]; +assign builder_minsoc_csrbank2_dfii_pi1_rddata2_w = main_sdram_phaseinjector1_status[23:16]; +assign builder_minsoc_csrbank2_dfii_pi1_rddata1_w = main_sdram_phaseinjector1_status[15:8]; +assign builder_minsoc_csrbank2_dfii_pi1_rddata0_w = main_sdram_phaseinjector1_status[7:0]; +assign main_sdram_phaseinjector1_we = builder_minsoc_csrbank2_dfii_pi1_rddata0_we; +assign builder_minsoc_csrbank2_dfii_pi2_command0_w = main_sdram_phaseinjector2_command_storage[5:0]; +assign builder_minsoc_csrbank2_dfii_pi2_address1_w = main_sdram_phaseinjector2_address_storage[13:8]; +assign builder_minsoc_csrbank2_dfii_pi2_address0_w = main_sdram_phaseinjector2_address_storage[7:0]; +assign builder_minsoc_csrbank2_dfii_pi2_baddress0_w = main_sdram_phaseinjector2_baddress_storage[2:0]; +assign builder_minsoc_csrbank2_dfii_pi2_wrdata3_w = main_sdram_phaseinjector2_wrdata_storage[31:24]; +assign builder_minsoc_csrbank2_dfii_pi2_wrdata2_w = main_sdram_phaseinjector2_wrdata_storage[23:16]; +assign builder_minsoc_csrbank2_dfii_pi2_wrdata1_w = main_sdram_phaseinjector2_wrdata_storage[15:8]; +assign builder_minsoc_csrbank2_dfii_pi2_wrdata0_w = main_sdram_phaseinjector2_wrdata_storage[7:0]; +assign builder_minsoc_csrbank2_dfii_pi2_rddata3_w = main_sdram_phaseinjector2_status[31:24]; +assign builder_minsoc_csrbank2_dfii_pi2_rddata2_w = main_sdram_phaseinjector2_status[23:16]; +assign builder_minsoc_csrbank2_dfii_pi2_rddata1_w = main_sdram_phaseinjector2_status[15:8]; +assign builder_minsoc_csrbank2_dfii_pi2_rddata0_w = main_sdram_phaseinjector2_status[7:0]; +assign main_sdram_phaseinjector2_we = builder_minsoc_csrbank2_dfii_pi2_rddata0_we; +assign builder_minsoc_csrbank2_dfii_pi3_command0_w = main_sdram_phaseinjector3_command_storage[5:0]; +assign builder_minsoc_csrbank2_dfii_pi3_address1_w = main_sdram_phaseinjector3_address_storage[13:8]; +assign builder_minsoc_csrbank2_dfii_pi3_address0_w = main_sdram_phaseinjector3_address_storage[7:0]; +assign builder_minsoc_csrbank2_dfii_pi3_baddress0_w = main_sdram_phaseinjector3_baddress_storage[2:0]; +assign builder_minsoc_csrbank2_dfii_pi3_wrdata3_w = main_sdram_phaseinjector3_wrdata_storage[31:24]; +assign builder_minsoc_csrbank2_dfii_pi3_wrdata2_w = main_sdram_phaseinjector3_wrdata_storage[23:16]; +assign builder_minsoc_csrbank2_dfii_pi3_wrdata1_w = main_sdram_phaseinjector3_wrdata_storage[15:8]; +assign builder_minsoc_csrbank2_dfii_pi3_wrdata0_w = main_sdram_phaseinjector3_wrdata_storage[7:0]; +assign builder_minsoc_csrbank2_dfii_pi3_rddata3_w = main_sdram_phaseinjector3_status[31:24]; +assign builder_minsoc_csrbank2_dfii_pi3_rddata2_w = main_sdram_phaseinjector3_status[23:16]; +assign builder_minsoc_csrbank2_dfii_pi3_rddata1_w = main_sdram_phaseinjector3_status[15:8]; +assign builder_minsoc_csrbank2_dfii_pi3_rddata0_w = main_sdram_phaseinjector3_status[7:0]; +assign main_sdram_phaseinjector3_we = builder_minsoc_csrbank2_dfii_pi3_rddata0_we; +assign builder_minsoc_csrbank3_sel = (builder_minsoc_interface3_bank_bus_adr[13:9] == 3'd4); +assign builder_minsoc_csrbank3_load3_r = builder_minsoc_interface3_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank3_load3_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 1'd0)); +assign builder_minsoc_csrbank3_load3_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 1'd0)); +assign builder_minsoc_csrbank3_load2_r = builder_minsoc_interface3_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank3_load2_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 1'd1)); +assign builder_minsoc_csrbank3_load2_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 1'd1)); +assign builder_minsoc_csrbank3_load1_r = builder_minsoc_interface3_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank3_load1_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 2'd2)); +assign builder_minsoc_csrbank3_load1_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 2'd2)); +assign builder_minsoc_csrbank3_load0_r = builder_minsoc_interface3_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank3_load0_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 2'd3)); +assign builder_minsoc_csrbank3_load0_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 2'd3)); +assign builder_minsoc_csrbank3_reload3_r = builder_minsoc_interface3_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank3_reload3_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 3'd4)); +assign builder_minsoc_csrbank3_reload3_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 3'd4)); +assign builder_minsoc_csrbank3_reload2_r = builder_minsoc_interface3_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank3_reload2_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 3'd5)); +assign builder_minsoc_csrbank3_reload2_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 3'd5)); +assign builder_minsoc_csrbank3_reload1_r = builder_minsoc_interface3_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank3_reload1_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 3'd6)); +assign builder_minsoc_csrbank3_reload1_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 3'd6)); +assign builder_minsoc_csrbank3_reload0_r = builder_minsoc_interface3_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank3_reload0_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 3'd7)); +assign builder_minsoc_csrbank3_reload0_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 3'd7)); +assign builder_minsoc_csrbank3_en0_r = builder_minsoc_interface3_bank_bus_dat_w[0]; +assign builder_minsoc_csrbank3_en0_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd8)); +assign builder_minsoc_csrbank3_en0_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd8)); +assign builder_minsoc_csrbank3_update_value0_r = builder_minsoc_interface3_bank_bus_dat_w[0]; +assign builder_minsoc_csrbank3_update_value0_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd9)); +assign builder_minsoc_csrbank3_update_value0_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd9)); +assign builder_minsoc_csrbank3_value3_r = builder_minsoc_interface3_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank3_value3_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd10)); +assign builder_minsoc_csrbank3_value3_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd10)); +assign builder_minsoc_csrbank3_value2_r = builder_minsoc_interface3_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank3_value2_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd11)); +assign builder_minsoc_csrbank3_value2_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd11)); +assign builder_minsoc_csrbank3_value1_r = builder_minsoc_interface3_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank3_value1_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd12)); +assign builder_minsoc_csrbank3_value1_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd12)); +assign builder_minsoc_csrbank3_value0_r = builder_minsoc_interface3_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank3_value0_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd13)); +assign builder_minsoc_csrbank3_value0_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd13)); +assign main_timer0_eventmanager_status_r = builder_minsoc_interface3_bank_bus_dat_w[0]; +assign main_timer0_eventmanager_status_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd14)); +assign main_timer0_eventmanager_status_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd14)); +assign main_timer0_eventmanager_pending_r = builder_minsoc_interface3_bank_bus_dat_w[0]; +assign main_timer0_eventmanager_pending_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd15)); +assign main_timer0_eventmanager_pending_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 4'd15)); +assign builder_minsoc_csrbank3_ev_enable0_r = builder_minsoc_interface3_bank_bus_dat_w[0]; +assign builder_minsoc_csrbank3_ev_enable0_re = ((builder_minsoc_csrbank3_sel & builder_minsoc_interface3_bank_bus_we) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 5'd16)); +assign builder_minsoc_csrbank3_ev_enable0_we = ((builder_minsoc_csrbank3_sel & (~builder_minsoc_interface3_bank_bus_we)) & (builder_minsoc_interface3_bank_bus_adr[4:0] == 5'd16)); +assign builder_minsoc_csrbank3_load3_w = main_timer0_load_storage[31:24]; +assign builder_minsoc_csrbank3_load2_w = main_timer0_load_storage[23:16]; +assign builder_minsoc_csrbank3_load1_w = main_timer0_load_storage[15:8]; +assign builder_minsoc_csrbank3_load0_w = main_timer0_load_storage[7:0]; +assign builder_minsoc_csrbank3_reload3_w = main_timer0_reload_storage[31:24]; +assign builder_minsoc_csrbank3_reload2_w = main_timer0_reload_storage[23:16]; +assign builder_minsoc_csrbank3_reload1_w = main_timer0_reload_storage[15:8]; +assign builder_minsoc_csrbank3_reload0_w = main_timer0_reload_storage[7:0]; +assign builder_minsoc_csrbank3_en0_w = main_timer0_en_storage; +assign builder_minsoc_csrbank3_update_value0_w = main_timer0_update_value_storage; +assign builder_minsoc_csrbank3_value3_w = main_timer0_value_status[31:24]; +assign builder_minsoc_csrbank3_value2_w = main_timer0_value_status[23:16]; +assign builder_minsoc_csrbank3_value1_w = main_timer0_value_status[15:8]; +assign builder_minsoc_csrbank3_value0_w = main_timer0_value_status[7:0]; +assign main_timer0_value_we = builder_minsoc_csrbank3_value0_we; +assign builder_minsoc_csrbank3_ev_enable0_w = main_timer0_eventmanager_storage; +assign builder_minsoc_csrbank4_sel = (builder_minsoc_interface4_bank_bus_adr[13:9] == 2'd3); +assign main_uart_rxtx_r = builder_minsoc_interface4_bank_bus_dat_w[7:0]; +assign main_uart_rxtx_re = ((builder_minsoc_csrbank4_sel & builder_minsoc_interface4_bank_bus_we) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 1'd0)); +assign main_uart_rxtx_we = ((builder_minsoc_csrbank4_sel & (~builder_minsoc_interface4_bank_bus_we)) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 1'd0)); +assign builder_minsoc_csrbank4_txfull_r = builder_minsoc_interface4_bank_bus_dat_w[0]; +assign builder_minsoc_csrbank4_txfull_re = ((builder_minsoc_csrbank4_sel & builder_minsoc_interface4_bank_bus_we) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 1'd1)); +assign builder_minsoc_csrbank4_txfull_we = ((builder_minsoc_csrbank4_sel & (~builder_minsoc_interface4_bank_bus_we)) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 1'd1)); +assign builder_minsoc_csrbank4_rxempty_r = builder_minsoc_interface4_bank_bus_dat_w[0]; +assign builder_minsoc_csrbank4_rxempty_re = ((builder_minsoc_csrbank4_sel & builder_minsoc_interface4_bank_bus_we) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 2'd2)); +assign builder_minsoc_csrbank4_rxempty_we = ((builder_minsoc_csrbank4_sel & (~builder_minsoc_interface4_bank_bus_we)) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 2'd2)); +assign main_uart_eventmanager_status_r = builder_minsoc_interface4_bank_bus_dat_w[1:0]; +assign main_uart_eventmanager_status_re = ((builder_minsoc_csrbank4_sel & builder_minsoc_interface4_bank_bus_we) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 2'd3)); +assign main_uart_eventmanager_status_we = ((builder_minsoc_csrbank4_sel & (~builder_minsoc_interface4_bank_bus_we)) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 2'd3)); +assign main_uart_eventmanager_pending_r = builder_minsoc_interface4_bank_bus_dat_w[1:0]; +assign main_uart_eventmanager_pending_re = ((builder_minsoc_csrbank4_sel & builder_minsoc_interface4_bank_bus_we) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 3'd4)); +assign main_uart_eventmanager_pending_we = ((builder_minsoc_csrbank4_sel & (~builder_minsoc_interface4_bank_bus_we)) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 3'd4)); +assign builder_minsoc_csrbank4_ev_enable0_r = builder_minsoc_interface4_bank_bus_dat_w[1:0]; +assign builder_minsoc_csrbank4_ev_enable0_re = ((builder_minsoc_csrbank4_sel & builder_minsoc_interface4_bank_bus_we) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 3'd5)); +assign builder_minsoc_csrbank4_ev_enable0_we = ((builder_minsoc_csrbank4_sel & (~builder_minsoc_interface4_bank_bus_we)) & (builder_minsoc_interface4_bank_bus_adr[2:0] == 3'd5)); +assign builder_minsoc_csrbank4_txfull_w = main_uart_txfull_status; +assign main_uart_txfull_we = builder_minsoc_csrbank4_txfull_we; +assign builder_minsoc_csrbank4_rxempty_w = main_uart_rxempty_status; +assign main_uart_rxempty_we = builder_minsoc_csrbank4_rxempty_we; +assign builder_minsoc_csrbank4_ev_enable0_w = main_uart_eventmanager_storage[1:0]; +assign builder_minsoc_csrbank5_sel = (builder_minsoc_interface5_bank_bus_adr[13:9] == 2'd2); +assign builder_minsoc_csrbank5_tuning_word3_r = builder_minsoc_interface5_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank5_tuning_word3_re = ((builder_minsoc_csrbank5_sel & builder_minsoc_interface5_bank_bus_we) & (builder_minsoc_interface5_bank_bus_adr[1:0] == 1'd0)); +assign builder_minsoc_csrbank5_tuning_word3_we = ((builder_minsoc_csrbank5_sel & (~builder_minsoc_interface5_bank_bus_we)) & (builder_minsoc_interface5_bank_bus_adr[1:0] == 1'd0)); +assign builder_minsoc_csrbank5_tuning_word2_r = builder_minsoc_interface5_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank5_tuning_word2_re = ((builder_minsoc_csrbank5_sel & builder_minsoc_interface5_bank_bus_we) & (builder_minsoc_interface5_bank_bus_adr[1:0] == 1'd1)); +assign builder_minsoc_csrbank5_tuning_word2_we = ((builder_minsoc_csrbank5_sel & (~builder_minsoc_interface5_bank_bus_we)) & (builder_minsoc_interface5_bank_bus_adr[1:0] == 1'd1)); +assign builder_minsoc_csrbank5_tuning_word1_r = builder_minsoc_interface5_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank5_tuning_word1_re = ((builder_minsoc_csrbank5_sel & builder_minsoc_interface5_bank_bus_we) & (builder_minsoc_interface5_bank_bus_adr[1:0] == 2'd2)); +assign builder_minsoc_csrbank5_tuning_word1_we = ((builder_minsoc_csrbank5_sel & (~builder_minsoc_interface5_bank_bus_we)) & (builder_minsoc_interface5_bank_bus_adr[1:0] == 2'd2)); +assign builder_minsoc_csrbank5_tuning_word0_r = builder_minsoc_interface5_bank_bus_dat_w[7:0]; +assign builder_minsoc_csrbank5_tuning_word0_re = ((builder_minsoc_csrbank5_sel & builder_minsoc_interface5_bank_bus_we) & (builder_minsoc_interface5_bank_bus_adr[1:0] == 2'd3)); +assign builder_minsoc_csrbank5_tuning_word0_we = ((builder_minsoc_csrbank5_sel & (~builder_minsoc_interface5_bank_bus_we)) & (builder_minsoc_interface5_bank_bus_adr[1:0] == 2'd3)); +assign builder_minsoc_csrbank5_tuning_word3_w = main_uart_phy_storage[31:24]; +assign builder_minsoc_csrbank5_tuning_word2_w = main_uart_phy_storage[23:16]; +assign builder_minsoc_csrbank5_tuning_word1_w = main_uart_phy_storage[15:8]; +assign builder_minsoc_csrbank5_tuning_word0_w = main_uart_phy_storage[7:0]; +assign builder_minsoc_adr = main_interface_adr; +assign builder_minsoc_we = main_interface_we; +assign builder_minsoc_dat_w = main_interface_dat_w; +assign main_interface_dat_r = builder_minsoc_dat_r; +assign builder_minsoc_interface0_bank_bus_adr = builder_minsoc_adr; +assign builder_minsoc_interface1_bank_bus_adr = builder_minsoc_adr; +assign builder_minsoc_interface2_bank_bus_adr = builder_minsoc_adr; +assign builder_minsoc_interface3_bank_bus_adr = builder_minsoc_adr; +assign builder_minsoc_interface4_bank_bus_adr = builder_minsoc_adr; +assign builder_minsoc_interface5_bank_bus_adr = builder_minsoc_adr; +assign builder_minsoc_interface0_bank_bus_we = builder_minsoc_we; +assign builder_minsoc_interface1_bank_bus_we = builder_minsoc_we; +assign builder_minsoc_interface2_bank_bus_we = builder_minsoc_we; +assign builder_minsoc_interface3_bank_bus_we = builder_minsoc_we; +assign builder_minsoc_interface4_bank_bus_we = builder_minsoc_we; +assign builder_minsoc_interface5_bank_bus_we = builder_minsoc_we; +assign builder_minsoc_interface0_bank_bus_dat_w = builder_minsoc_dat_w; +assign builder_minsoc_interface1_bank_bus_dat_w = builder_minsoc_dat_w; +assign builder_minsoc_interface2_bank_bus_dat_w = builder_minsoc_dat_w; +assign builder_minsoc_interface3_bank_bus_dat_w = builder_minsoc_dat_w; +assign builder_minsoc_interface4_bank_bus_dat_w = builder_minsoc_dat_w; +assign builder_minsoc_interface5_bank_bus_dat_w = builder_minsoc_dat_w; +assign builder_minsoc_dat_r = (((((builder_minsoc_interface0_bank_bus_dat_r | builder_minsoc_interface1_bank_bus_dat_r) | builder_minsoc_interface2_bank_bus_dat_r) | builder_minsoc_interface3_bank_bus_dat_r) | builder_minsoc_interface4_bank_bus_dat_r) | builder_minsoc_interface5_bank_bus_dat_r); +always @(*) begin + builder_rhs_array_muxed0 <= 1'd0; + case (main_sdram_choose_cmd_grant) + 1'd0: begin + builder_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[0]; + end + 1'd1: begin + builder_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[1]; + end + 2'd2: begin + builder_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[2]; + end + 2'd3: begin + builder_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[3]; + end + 3'd4: begin + builder_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[4]; + end + 3'd5: begin + builder_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[5]; + end + 3'd6: begin + builder_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[6]; + end + default: begin + builder_rhs_array_muxed0 <= main_sdram_choose_cmd_valids[7]; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed1 <= 14'd0; + case (main_sdram_choose_cmd_grant) + 1'd0: begin + builder_rhs_array_muxed1 <= main_sdram_bankmachine0_cmd_payload_a; + end + 1'd1: begin + builder_rhs_array_muxed1 <= main_sdram_bankmachine1_cmd_payload_a; + end + 2'd2: begin + builder_rhs_array_muxed1 <= main_sdram_bankmachine2_cmd_payload_a; + end + 2'd3: begin + builder_rhs_array_muxed1 <= main_sdram_bankmachine3_cmd_payload_a; + end + 3'd4: begin + builder_rhs_array_muxed1 <= main_sdram_bankmachine4_cmd_payload_a; + end + 3'd5: begin + builder_rhs_array_muxed1 <= main_sdram_bankmachine5_cmd_payload_a; + end + 3'd6: begin + builder_rhs_array_muxed1 <= main_sdram_bankmachine6_cmd_payload_a; + end + default: begin + builder_rhs_array_muxed1 <= main_sdram_bankmachine7_cmd_payload_a; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed2 <= 3'd0; + case (main_sdram_choose_cmd_grant) + 1'd0: begin + builder_rhs_array_muxed2 <= main_sdram_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + builder_rhs_array_muxed2 <= main_sdram_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + builder_rhs_array_muxed2 <= main_sdram_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + builder_rhs_array_muxed2 <= main_sdram_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + builder_rhs_array_muxed2 <= main_sdram_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + builder_rhs_array_muxed2 <= main_sdram_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + builder_rhs_array_muxed2 <= main_sdram_bankmachine6_cmd_payload_ba; + end + default: begin + builder_rhs_array_muxed2 <= main_sdram_bankmachine7_cmd_payload_ba; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed3 <= 1'd0; + case (main_sdram_choose_cmd_grant) + 1'd0: begin + builder_rhs_array_muxed3 <= main_sdram_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + builder_rhs_array_muxed3 <= main_sdram_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + builder_rhs_array_muxed3 <= main_sdram_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + builder_rhs_array_muxed3 <= main_sdram_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + builder_rhs_array_muxed3 <= main_sdram_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + builder_rhs_array_muxed3 <= main_sdram_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + builder_rhs_array_muxed3 <= main_sdram_bankmachine6_cmd_payload_is_read; + end + default: begin + builder_rhs_array_muxed3 <= main_sdram_bankmachine7_cmd_payload_is_read; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed4 <= 1'd0; + case (main_sdram_choose_cmd_grant) + 1'd0: begin + builder_rhs_array_muxed4 <= main_sdram_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + builder_rhs_array_muxed4 <= main_sdram_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + builder_rhs_array_muxed4 <= main_sdram_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + builder_rhs_array_muxed4 <= main_sdram_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + builder_rhs_array_muxed4 <= main_sdram_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + builder_rhs_array_muxed4 <= main_sdram_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + builder_rhs_array_muxed4 <= main_sdram_bankmachine6_cmd_payload_is_write; + end + default: begin + builder_rhs_array_muxed4 <= main_sdram_bankmachine7_cmd_payload_is_write; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed5 <= 1'd0; + case (main_sdram_choose_cmd_grant) + 1'd0: begin + builder_rhs_array_muxed5 <= main_sdram_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + builder_rhs_array_muxed5 <= main_sdram_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + builder_rhs_array_muxed5 <= main_sdram_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + builder_rhs_array_muxed5 <= main_sdram_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + builder_rhs_array_muxed5 <= main_sdram_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + builder_rhs_array_muxed5 <= main_sdram_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + builder_rhs_array_muxed5 <= main_sdram_bankmachine6_cmd_payload_is_cmd; + end + default: begin + builder_rhs_array_muxed5 <= main_sdram_bankmachine7_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + builder_t_array_muxed0 <= 1'd0; + case (main_sdram_choose_cmd_grant) + 1'd0: begin + builder_t_array_muxed0 <= main_sdram_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + builder_t_array_muxed0 <= main_sdram_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + builder_t_array_muxed0 <= main_sdram_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + builder_t_array_muxed0 <= main_sdram_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + builder_t_array_muxed0 <= main_sdram_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + builder_t_array_muxed0 <= main_sdram_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + builder_t_array_muxed0 <= main_sdram_bankmachine6_cmd_payload_cas; + end + default: begin + builder_t_array_muxed0 <= main_sdram_bankmachine7_cmd_payload_cas; + end + endcase +end +always @(*) begin + builder_t_array_muxed1 <= 1'd0; + case (main_sdram_choose_cmd_grant) + 1'd0: begin + builder_t_array_muxed1 <= main_sdram_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + builder_t_array_muxed1 <= main_sdram_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + builder_t_array_muxed1 <= main_sdram_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + builder_t_array_muxed1 <= main_sdram_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + builder_t_array_muxed1 <= main_sdram_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + builder_t_array_muxed1 <= main_sdram_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + builder_t_array_muxed1 <= main_sdram_bankmachine6_cmd_payload_ras; + end + default: begin + builder_t_array_muxed1 <= main_sdram_bankmachine7_cmd_payload_ras; + end + endcase +end +always @(*) begin + builder_t_array_muxed2 <= 1'd0; + case (main_sdram_choose_cmd_grant) + 1'd0: begin + builder_t_array_muxed2 <= main_sdram_bankmachine0_cmd_payload_we; + end + 1'd1: begin + builder_t_array_muxed2 <= main_sdram_bankmachine1_cmd_payload_we; + end + 2'd2: begin + builder_t_array_muxed2 <= main_sdram_bankmachine2_cmd_payload_we; + end + 2'd3: begin + builder_t_array_muxed2 <= main_sdram_bankmachine3_cmd_payload_we; + end + 3'd4: begin + builder_t_array_muxed2 <= main_sdram_bankmachine4_cmd_payload_we; + end + 3'd5: begin + builder_t_array_muxed2 <= main_sdram_bankmachine5_cmd_payload_we; + end + 3'd6: begin + builder_t_array_muxed2 <= main_sdram_bankmachine6_cmd_payload_we; + end + default: begin + builder_t_array_muxed2 <= main_sdram_bankmachine7_cmd_payload_we; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed6 <= 1'd0; + case (main_sdram_choose_req_grant) + 1'd0: begin + builder_rhs_array_muxed6 <= main_sdram_choose_req_valids[0]; + end + 1'd1: begin + builder_rhs_array_muxed6 <= main_sdram_choose_req_valids[1]; + end + 2'd2: begin + builder_rhs_array_muxed6 <= main_sdram_choose_req_valids[2]; + end + 2'd3: begin + builder_rhs_array_muxed6 <= main_sdram_choose_req_valids[3]; + end + 3'd4: begin + builder_rhs_array_muxed6 <= main_sdram_choose_req_valids[4]; + end + 3'd5: begin + builder_rhs_array_muxed6 <= main_sdram_choose_req_valids[5]; + end + 3'd6: begin + builder_rhs_array_muxed6 <= main_sdram_choose_req_valids[6]; + end + default: begin + builder_rhs_array_muxed6 <= main_sdram_choose_req_valids[7]; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed7 <= 14'd0; + case (main_sdram_choose_req_grant) + 1'd0: begin + builder_rhs_array_muxed7 <= main_sdram_bankmachine0_cmd_payload_a; + end + 1'd1: begin + builder_rhs_array_muxed7 <= main_sdram_bankmachine1_cmd_payload_a; + end + 2'd2: begin + builder_rhs_array_muxed7 <= main_sdram_bankmachine2_cmd_payload_a; + end + 2'd3: begin + builder_rhs_array_muxed7 <= main_sdram_bankmachine3_cmd_payload_a; + end + 3'd4: begin + builder_rhs_array_muxed7 <= main_sdram_bankmachine4_cmd_payload_a; + end + 3'd5: begin + builder_rhs_array_muxed7 <= main_sdram_bankmachine5_cmd_payload_a; + end + 3'd6: begin + builder_rhs_array_muxed7 <= main_sdram_bankmachine6_cmd_payload_a; + end + default: begin + builder_rhs_array_muxed7 <= main_sdram_bankmachine7_cmd_payload_a; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed8 <= 3'd0; + case (main_sdram_choose_req_grant) + 1'd0: begin + builder_rhs_array_muxed8 <= main_sdram_bankmachine0_cmd_payload_ba; + end + 1'd1: begin + builder_rhs_array_muxed8 <= main_sdram_bankmachine1_cmd_payload_ba; + end + 2'd2: begin + builder_rhs_array_muxed8 <= main_sdram_bankmachine2_cmd_payload_ba; + end + 2'd3: begin + builder_rhs_array_muxed8 <= main_sdram_bankmachine3_cmd_payload_ba; + end + 3'd4: begin + builder_rhs_array_muxed8 <= main_sdram_bankmachine4_cmd_payload_ba; + end + 3'd5: begin + builder_rhs_array_muxed8 <= main_sdram_bankmachine5_cmd_payload_ba; + end + 3'd6: begin + builder_rhs_array_muxed8 <= main_sdram_bankmachine6_cmd_payload_ba; + end + default: begin + builder_rhs_array_muxed8 <= main_sdram_bankmachine7_cmd_payload_ba; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed9 <= 1'd0; + case (main_sdram_choose_req_grant) + 1'd0: begin + builder_rhs_array_muxed9 <= main_sdram_bankmachine0_cmd_payload_is_read; + end + 1'd1: begin + builder_rhs_array_muxed9 <= main_sdram_bankmachine1_cmd_payload_is_read; + end + 2'd2: begin + builder_rhs_array_muxed9 <= main_sdram_bankmachine2_cmd_payload_is_read; + end + 2'd3: begin + builder_rhs_array_muxed9 <= main_sdram_bankmachine3_cmd_payload_is_read; + end + 3'd4: begin + builder_rhs_array_muxed9 <= main_sdram_bankmachine4_cmd_payload_is_read; + end + 3'd5: begin + builder_rhs_array_muxed9 <= main_sdram_bankmachine5_cmd_payload_is_read; + end + 3'd6: begin + builder_rhs_array_muxed9 <= main_sdram_bankmachine6_cmd_payload_is_read; + end + default: begin + builder_rhs_array_muxed9 <= main_sdram_bankmachine7_cmd_payload_is_read; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed10 <= 1'd0; + case (main_sdram_choose_req_grant) + 1'd0: begin + builder_rhs_array_muxed10 <= main_sdram_bankmachine0_cmd_payload_is_write; + end + 1'd1: begin + builder_rhs_array_muxed10 <= main_sdram_bankmachine1_cmd_payload_is_write; + end + 2'd2: begin + builder_rhs_array_muxed10 <= main_sdram_bankmachine2_cmd_payload_is_write; + end + 2'd3: begin + builder_rhs_array_muxed10 <= main_sdram_bankmachine3_cmd_payload_is_write; + end + 3'd4: begin + builder_rhs_array_muxed10 <= main_sdram_bankmachine4_cmd_payload_is_write; + end + 3'd5: begin + builder_rhs_array_muxed10 <= main_sdram_bankmachine5_cmd_payload_is_write; + end + 3'd6: begin + builder_rhs_array_muxed10 <= main_sdram_bankmachine6_cmd_payload_is_write; + end + default: begin + builder_rhs_array_muxed10 <= main_sdram_bankmachine7_cmd_payload_is_write; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed11 <= 1'd0; + case (main_sdram_choose_req_grant) + 1'd0: begin + builder_rhs_array_muxed11 <= main_sdram_bankmachine0_cmd_payload_is_cmd; + end + 1'd1: begin + builder_rhs_array_muxed11 <= main_sdram_bankmachine1_cmd_payload_is_cmd; + end + 2'd2: begin + builder_rhs_array_muxed11 <= main_sdram_bankmachine2_cmd_payload_is_cmd; + end + 2'd3: begin + builder_rhs_array_muxed11 <= main_sdram_bankmachine3_cmd_payload_is_cmd; + end + 3'd4: begin + builder_rhs_array_muxed11 <= main_sdram_bankmachine4_cmd_payload_is_cmd; + end + 3'd5: begin + builder_rhs_array_muxed11 <= main_sdram_bankmachine5_cmd_payload_is_cmd; + end + 3'd6: begin + builder_rhs_array_muxed11 <= main_sdram_bankmachine6_cmd_payload_is_cmd; + end + default: begin + builder_rhs_array_muxed11 <= main_sdram_bankmachine7_cmd_payload_is_cmd; + end + endcase +end +always @(*) begin + builder_t_array_muxed3 <= 1'd0; + case (main_sdram_choose_req_grant) + 1'd0: begin + builder_t_array_muxed3 <= main_sdram_bankmachine0_cmd_payload_cas; + end + 1'd1: begin + builder_t_array_muxed3 <= main_sdram_bankmachine1_cmd_payload_cas; + end + 2'd2: begin + builder_t_array_muxed3 <= main_sdram_bankmachine2_cmd_payload_cas; + end + 2'd3: begin + builder_t_array_muxed3 <= main_sdram_bankmachine3_cmd_payload_cas; + end + 3'd4: begin + builder_t_array_muxed3 <= main_sdram_bankmachine4_cmd_payload_cas; + end + 3'd5: begin + builder_t_array_muxed3 <= main_sdram_bankmachine5_cmd_payload_cas; + end + 3'd6: begin + builder_t_array_muxed3 <= main_sdram_bankmachine6_cmd_payload_cas; + end + default: begin + builder_t_array_muxed3 <= main_sdram_bankmachine7_cmd_payload_cas; + end + endcase +end +always @(*) begin + builder_t_array_muxed4 <= 1'd0; + case (main_sdram_choose_req_grant) + 1'd0: begin + builder_t_array_muxed4 <= main_sdram_bankmachine0_cmd_payload_ras; + end + 1'd1: begin + builder_t_array_muxed4 <= main_sdram_bankmachine1_cmd_payload_ras; + end + 2'd2: begin + builder_t_array_muxed4 <= main_sdram_bankmachine2_cmd_payload_ras; + end + 2'd3: begin + builder_t_array_muxed4 <= main_sdram_bankmachine3_cmd_payload_ras; + end + 3'd4: begin + builder_t_array_muxed4 <= main_sdram_bankmachine4_cmd_payload_ras; + end + 3'd5: begin + builder_t_array_muxed4 <= main_sdram_bankmachine5_cmd_payload_ras; + end + 3'd6: begin + builder_t_array_muxed4 <= main_sdram_bankmachine6_cmd_payload_ras; + end + default: begin + builder_t_array_muxed4 <= main_sdram_bankmachine7_cmd_payload_ras; + end + endcase +end +always @(*) begin + builder_t_array_muxed5 <= 1'd0; + case (main_sdram_choose_req_grant) + 1'd0: begin + builder_t_array_muxed5 <= main_sdram_bankmachine0_cmd_payload_we; + end + 1'd1: begin + builder_t_array_muxed5 <= main_sdram_bankmachine1_cmd_payload_we; + end + 2'd2: begin + builder_t_array_muxed5 <= main_sdram_bankmachine2_cmd_payload_we; + end + 2'd3: begin + builder_t_array_muxed5 <= main_sdram_bankmachine3_cmd_payload_we; + end + 3'd4: begin + builder_t_array_muxed5 <= main_sdram_bankmachine4_cmd_payload_we; + end + 3'd5: begin + builder_t_array_muxed5 <= main_sdram_bankmachine5_cmd_payload_we; + end + 3'd6: begin + builder_t_array_muxed5 <= main_sdram_bankmachine6_cmd_payload_we; + end + default: begin + builder_t_array_muxed5 <= main_sdram_bankmachine7_cmd_payload_we; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed12 <= 21'd0; + case (builder_roundrobin0_grant) + default: begin + builder_rhs_array_muxed12 <= {main_port_cmd_payload_addr[23:10], main_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed13 <= 1'd0; + case (builder_roundrobin0_grant) + default: begin + builder_rhs_array_muxed13 <= main_port_cmd_payload_we; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed14 <= 1'd0; + case (builder_roundrobin0_grant) + default: begin + builder_rhs_array_muxed14 <= (((main_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((builder_locked0 | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid); + end + endcase +end +always @(*) begin + builder_rhs_array_muxed15 <= 21'd0; + case (builder_roundrobin1_grant) + default: begin + builder_rhs_array_muxed15 <= {main_port_cmd_payload_addr[23:10], main_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed16 <= 1'd0; + case (builder_roundrobin1_grant) + default: begin + builder_rhs_array_muxed16 <= main_port_cmd_payload_we; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed17 <= 1'd0; + case (builder_roundrobin1_grant) + default: begin + builder_rhs_array_muxed17 <= (((main_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((builder_locked1 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid); + end + endcase +end +always @(*) begin + builder_rhs_array_muxed18 <= 21'd0; + case (builder_roundrobin2_grant) + default: begin + builder_rhs_array_muxed18 <= {main_port_cmd_payload_addr[23:10], main_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed19 <= 1'd0; + case (builder_roundrobin2_grant) + default: begin + builder_rhs_array_muxed19 <= main_port_cmd_payload_we; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed20 <= 1'd0; + case (builder_roundrobin2_grant) + default: begin + builder_rhs_array_muxed20 <= (((main_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((builder_locked2 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid); + end + endcase +end +always @(*) begin + builder_rhs_array_muxed21 <= 21'd0; + case (builder_roundrobin3_grant) + default: begin + builder_rhs_array_muxed21 <= {main_port_cmd_payload_addr[23:10], main_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed22 <= 1'd0; + case (builder_roundrobin3_grant) + default: begin + builder_rhs_array_muxed22 <= main_port_cmd_payload_we; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed23 <= 1'd0; + case (builder_roundrobin3_grant) + default: begin + builder_rhs_array_muxed23 <= (((main_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((builder_locked3 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid); + end + endcase +end +always @(*) begin + builder_rhs_array_muxed24 <= 21'd0; + case (builder_roundrobin4_grant) + default: begin + builder_rhs_array_muxed24 <= {main_port_cmd_payload_addr[23:10], main_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed25 <= 1'd0; + case (builder_roundrobin4_grant) + default: begin + builder_rhs_array_muxed25 <= main_port_cmd_payload_we; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed26 <= 1'd0; + case (builder_roundrobin4_grant) + default: begin + builder_rhs_array_muxed26 <= (((main_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((builder_locked4 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid); + end + endcase +end +always @(*) begin + builder_rhs_array_muxed27 <= 21'd0; + case (builder_roundrobin5_grant) + default: begin + builder_rhs_array_muxed27 <= {main_port_cmd_payload_addr[23:10], main_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed28 <= 1'd0; + case (builder_roundrobin5_grant) + default: begin + builder_rhs_array_muxed28 <= main_port_cmd_payload_we; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed29 <= 1'd0; + case (builder_roundrobin5_grant) + default: begin + builder_rhs_array_muxed29 <= (((main_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((builder_locked5 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid); + end + endcase +end +always @(*) begin + builder_rhs_array_muxed30 <= 21'd0; + case (builder_roundrobin6_grant) + default: begin + builder_rhs_array_muxed30 <= {main_port_cmd_payload_addr[23:10], main_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed31 <= 1'd0; + case (builder_roundrobin6_grant) + default: begin + builder_rhs_array_muxed31 <= main_port_cmd_payload_we; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed32 <= 1'd0; + case (builder_roundrobin6_grant) + default: begin + builder_rhs_array_muxed32 <= (((main_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((builder_locked6 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank7_lock & (builder_roundrobin7_grant == 1'd0))))) & main_port_cmd_valid); + end + endcase +end +always @(*) begin + builder_rhs_array_muxed33 <= 21'd0; + case (builder_roundrobin7_grant) + default: begin + builder_rhs_array_muxed33 <= {main_port_cmd_payload_addr[23:10], main_port_cmd_payload_addr[6:0]}; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed34 <= 1'd0; + case (builder_roundrobin7_grant) + default: begin + builder_rhs_array_muxed34 <= main_port_cmd_payload_we; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed35 <= 1'd0; + case (builder_roundrobin7_grant) + default: begin + builder_rhs_array_muxed35 <= (((main_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((builder_locked7 | (main_sdram_interface_bank0_lock & (builder_roundrobin0_grant == 1'd0))) | (main_sdram_interface_bank1_lock & (builder_roundrobin1_grant == 1'd0))) | (main_sdram_interface_bank2_lock & (builder_roundrobin2_grant == 1'd0))) | (main_sdram_interface_bank3_lock & (builder_roundrobin3_grant == 1'd0))) | (main_sdram_interface_bank4_lock & (builder_roundrobin4_grant == 1'd0))) | (main_sdram_interface_bank5_lock & (builder_roundrobin5_grant == 1'd0))) | (main_sdram_interface_bank6_lock & (builder_roundrobin6_grant == 1'd0))))) & main_port_cmd_valid); + end + endcase +end +always @(*) begin + builder_rhs_array_muxed36 <= 30'd0; + case (builder_wb_sdram_con_grant) + default: begin + builder_rhs_array_muxed36 <= main_interface1_wb_sdram_adr; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed37 <= 32'd0; + case (builder_wb_sdram_con_grant) + default: begin + builder_rhs_array_muxed37 <= main_interface1_wb_sdram_dat_w; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed38 <= 4'd0; + case (builder_wb_sdram_con_grant) + default: begin + builder_rhs_array_muxed38 <= main_interface1_wb_sdram_sel; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed39 <= 1'd0; + case (builder_wb_sdram_con_grant) + default: begin + builder_rhs_array_muxed39 <= main_interface1_wb_sdram_cyc; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed40 <= 1'd0; + case (builder_wb_sdram_con_grant) + default: begin + builder_rhs_array_muxed40 <= main_interface1_wb_sdram_stb; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed41 <= 1'd0; + case (builder_wb_sdram_con_grant) + default: begin + builder_rhs_array_muxed41 <= main_interface1_wb_sdram_we; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed42 <= 3'd0; + case (builder_wb_sdram_con_grant) + default: begin + builder_rhs_array_muxed42 <= main_interface1_wb_sdram_cti; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed43 <= 2'd0; + case (builder_wb_sdram_con_grant) + default: begin + builder_rhs_array_muxed43 <= main_interface1_wb_sdram_bte; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed44 <= 30'd0; + case (builder_minsoc_grant) + 1'd0: begin + builder_rhs_array_muxed44 <= main_interface0_soc_bus_adr; + end + default: begin + builder_rhs_array_muxed44 <= main_interface1_soc_bus_adr; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed45 <= 32'd0; + case (builder_minsoc_grant) + 1'd0: begin + builder_rhs_array_muxed45 <= main_interface0_soc_bus_dat_w; + end + default: begin + builder_rhs_array_muxed45 <= main_interface1_soc_bus_dat_w; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed46 <= 4'd0; + case (builder_minsoc_grant) + 1'd0: begin + builder_rhs_array_muxed46 <= main_interface0_soc_bus_sel; + end + default: begin + builder_rhs_array_muxed46 <= main_interface1_soc_bus_sel; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed47 <= 1'd0; + case (builder_minsoc_grant) + 1'd0: begin + builder_rhs_array_muxed47 <= main_interface0_soc_bus_cyc; + end + default: begin + builder_rhs_array_muxed47 <= main_interface1_soc_bus_cyc; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed48 <= 1'd0; + case (builder_minsoc_grant) + 1'd0: begin + builder_rhs_array_muxed48 <= main_interface0_soc_bus_stb; + end + default: begin + builder_rhs_array_muxed48 <= main_interface1_soc_bus_stb; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed49 <= 1'd0; + case (builder_minsoc_grant) + 1'd0: begin + builder_rhs_array_muxed49 <= main_interface0_soc_bus_we; + end + default: begin + builder_rhs_array_muxed49 <= main_interface1_soc_bus_we; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed50 <= 3'd0; + case (builder_minsoc_grant) + 1'd0: begin + builder_rhs_array_muxed50 <= main_interface0_soc_bus_cti; + end + default: begin + builder_rhs_array_muxed50 <= main_interface1_soc_bus_cti; + end + endcase +end +always @(*) begin + builder_rhs_array_muxed51 <= 2'd0; + case (builder_minsoc_grant) + 1'd0: begin + builder_rhs_array_muxed51 <= main_interface0_soc_bus_bte; + end + default: begin + builder_rhs_array_muxed51 <= main_interface1_soc_bus_bte; + end + endcase +end +always @(*) begin + builder_array_muxed0 <= 3'd0; + case (main_sdram_steerer_sel0) + 1'd0: begin + builder_array_muxed0 <= main_sdram_nop_ba[2:0]; + end + 1'd1: begin + builder_array_muxed0 <= main_sdram_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + builder_array_muxed0 <= main_sdram_choose_req_cmd_payload_ba[2:0]; + end + default: begin + builder_array_muxed0 <= main_sdram_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + builder_array_muxed1 <= 14'd0; + case (main_sdram_steerer_sel0) + 1'd0: begin + builder_array_muxed1 <= main_sdram_nop_a; + end + 1'd1: begin + builder_array_muxed1 <= main_sdram_choose_cmd_cmd_payload_a; + end + 2'd2: begin + builder_array_muxed1 <= main_sdram_choose_req_cmd_payload_a; + end + default: begin + builder_array_muxed1 <= main_sdram_cmd_payload_a; + end + endcase +end +always @(*) begin + builder_array_muxed2 <= 1'd0; + case (main_sdram_steerer_sel0) + 1'd0: begin + builder_array_muxed2 <= 1'd0; + end + 1'd1: begin + builder_array_muxed2 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + builder_array_muxed2 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_cas); + end + default: begin + builder_array_muxed2 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_cas); + end + endcase +end +always @(*) begin + builder_array_muxed3 <= 1'd0; + case (main_sdram_steerer_sel0) + 1'd0: begin + builder_array_muxed3 <= 1'd0; + end + 1'd1: begin + builder_array_muxed3 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + builder_array_muxed3 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_ras); + end + default: begin + builder_array_muxed3 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_ras); + end + endcase +end +always @(*) begin + builder_array_muxed4 <= 1'd0; + case (main_sdram_steerer_sel0) + 1'd0: begin + builder_array_muxed4 <= 1'd0; + end + 1'd1: begin + builder_array_muxed4 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_we); + end + 2'd2: begin + builder_array_muxed4 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_we); + end + default: begin + builder_array_muxed4 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_we); + end + endcase +end +always @(*) begin + builder_array_muxed5 <= 1'd0; + case (main_sdram_steerer_sel0) + 1'd0: begin + builder_array_muxed5 <= 1'd0; + end + 1'd1: begin + builder_array_muxed5 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + builder_array_muxed5 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_read); + end + default: begin + builder_array_muxed5 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_is_read); + end + endcase +end +always @(*) begin + builder_array_muxed6 <= 1'd0; + case (main_sdram_steerer_sel0) + 1'd0: begin + builder_array_muxed6 <= 1'd0; + end + 1'd1: begin + builder_array_muxed6 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + builder_array_muxed6 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_write); + end + default: begin + builder_array_muxed6 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_is_write); + end + endcase +end +always @(*) begin + builder_array_muxed7 <= 3'd0; + case (main_sdram_steerer_sel1) + 1'd0: begin + builder_array_muxed7 <= main_sdram_nop_ba[2:0]; + end + 1'd1: begin + builder_array_muxed7 <= main_sdram_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + builder_array_muxed7 <= main_sdram_choose_req_cmd_payload_ba[2:0]; + end + default: begin + builder_array_muxed7 <= main_sdram_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + builder_array_muxed8 <= 14'd0; + case (main_sdram_steerer_sel1) + 1'd0: begin + builder_array_muxed8 <= main_sdram_nop_a; + end + 1'd1: begin + builder_array_muxed8 <= main_sdram_choose_cmd_cmd_payload_a; + end + 2'd2: begin + builder_array_muxed8 <= main_sdram_choose_req_cmd_payload_a; + end + default: begin + builder_array_muxed8 <= main_sdram_cmd_payload_a; + end + endcase +end +always @(*) begin + builder_array_muxed9 <= 1'd0; + case (main_sdram_steerer_sel1) + 1'd0: begin + builder_array_muxed9 <= 1'd0; + end + 1'd1: begin + builder_array_muxed9 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + builder_array_muxed9 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_cas); + end + default: begin + builder_array_muxed9 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_cas); + end + endcase +end +always @(*) begin + builder_array_muxed10 <= 1'd0; + case (main_sdram_steerer_sel1) + 1'd0: begin + builder_array_muxed10 <= 1'd0; + end + 1'd1: begin + builder_array_muxed10 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + builder_array_muxed10 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_ras); + end + default: begin + builder_array_muxed10 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_ras); + end + endcase +end +always @(*) begin + builder_array_muxed11 <= 1'd0; + case (main_sdram_steerer_sel1) + 1'd0: begin + builder_array_muxed11 <= 1'd0; + end + 1'd1: begin + builder_array_muxed11 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_we); + end + 2'd2: begin + builder_array_muxed11 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_we); + end + default: begin + builder_array_muxed11 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_we); + end + endcase +end +always @(*) begin + builder_array_muxed12 <= 1'd0; + case (main_sdram_steerer_sel1) + 1'd0: begin + builder_array_muxed12 <= 1'd0; + end + 1'd1: begin + builder_array_muxed12 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + builder_array_muxed12 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_read); + end + default: begin + builder_array_muxed12 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_is_read); + end + endcase +end +always @(*) begin + builder_array_muxed13 <= 1'd0; + case (main_sdram_steerer_sel1) + 1'd0: begin + builder_array_muxed13 <= 1'd0; + end + 1'd1: begin + builder_array_muxed13 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + builder_array_muxed13 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_write); + end + default: begin + builder_array_muxed13 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_is_write); + end + endcase +end +always @(*) begin + builder_array_muxed14 <= 3'd0; + case (main_sdram_steerer_sel2) + 1'd0: begin + builder_array_muxed14 <= main_sdram_nop_ba[2:0]; + end + 1'd1: begin + builder_array_muxed14 <= main_sdram_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + builder_array_muxed14 <= main_sdram_choose_req_cmd_payload_ba[2:0]; + end + default: begin + builder_array_muxed14 <= main_sdram_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + builder_array_muxed15 <= 14'd0; + case (main_sdram_steerer_sel2) + 1'd0: begin + builder_array_muxed15 <= main_sdram_nop_a; + end + 1'd1: begin + builder_array_muxed15 <= main_sdram_choose_cmd_cmd_payload_a; + end + 2'd2: begin + builder_array_muxed15 <= main_sdram_choose_req_cmd_payload_a; + end + default: begin + builder_array_muxed15 <= main_sdram_cmd_payload_a; + end + endcase +end +always @(*) begin + builder_array_muxed16 <= 1'd0; + case (main_sdram_steerer_sel2) + 1'd0: begin + builder_array_muxed16 <= 1'd0; + end + 1'd1: begin + builder_array_muxed16 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + builder_array_muxed16 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_cas); + end + default: begin + builder_array_muxed16 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_cas); + end + endcase +end +always @(*) begin + builder_array_muxed17 <= 1'd0; + case (main_sdram_steerer_sel2) + 1'd0: begin + builder_array_muxed17 <= 1'd0; + end + 1'd1: begin + builder_array_muxed17 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + builder_array_muxed17 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_ras); + end + default: begin + builder_array_muxed17 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_ras); + end + endcase +end +always @(*) begin + builder_array_muxed18 <= 1'd0; + case (main_sdram_steerer_sel2) + 1'd0: begin + builder_array_muxed18 <= 1'd0; + end + 1'd1: begin + builder_array_muxed18 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_we); + end + 2'd2: begin + builder_array_muxed18 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_we); + end + default: begin + builder_array_muxed18 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_we); + end + endcase +end +always @(*) begin + builder_array_muxed19 <= 1'd0; + case (main_sdram_steerer_sel2) + 1'd0: begin + builder_array_muxed19 <= 1'd0; + end + 1'd1: begin + builder_array_muxed19 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + builder_array_muxed19 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_read); + end + default: begin + builder_array_muxed19 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_is_read); + end + endcase +end +always @(*) begin + builder_array_muxed20 <= 1'd0; + case (main_sdram_steerer_sel2) + 1'd0: begin + builder_array_muxed20 <= 1'd0; + end + 1'd1: begin + builder_array_muxed20 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + builder_array_muxed20 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_write); + end + default: begin + builder_array_muxed20 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_is_write); + end + endcase +end +always @(*) begin + builder_array_muxed21 <= 3'd0; + case (main_sdram_steerer_sel3) + 1'd0: begin + builder_array_muxed21 <= main_sdram_nop_ba[2:0]; + end + 1'd1: begin + builder_array_muxed21 <= main_sdram_choose_cmd_cmd_payload_ba[2:0]; + end + 2'd2: begin + builder_array_muxed21 <= main_sdram_choose_req_cmd_payload_ba[2:0]; + end + default: begin + builder_array_muxed21 <= main_sdram_cmd_payload_ba[2:0]; + end + endcase +end +always @(*) begin + builder_array_muxed22 <= 14'd0; + case (main_sdram_steerer_sel3) + 1'd0: begin + builder_array_muxed22 <= main_sdram_nop_a; + end + 1'd1: begin + builder_array_muxed22 <= main_sdram_choose_cmd_cmd_payload_a; + end + 2'd2: begin + builder_array_muxed22 <= main_sdram_choose_req_cmd_payload_a; + end + default: begin + builder_array_muxed22 <= main_sdram_cmd_payload_a; + end + endcase +end +always @(*) begin + builder_array_muxed23 <= 1'd0; + case (main_sdram_steerer_sel3) + 1'd0: begin + builder_array_muxed23 <= 1'd0; + end + 1'd1: begin + builder_array_muxed23 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_cas); + end + 2'd2: begin + builder_array_muxed23 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_cas); + end + default: begin + builder_array_muxed23 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_cas); + end + endcase +end +always @(*) begin + builder_array_muxed24 <= 1'd0; + case (main_sdram_steerer_sel3) + 1'd0: begin + builder_array_muxed24 <= 1'd0; + end + 1'd1: begin + builder_array_muxed24 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_ras); + end + 2'd2: begin + builder_array_muxed24 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_ras); + end + default: begin + builder_array_muxed24 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_ras); + end + endcase +end +always @(*) begin + builder_array_muxed25 <= 1'd0; + case (main_sdram_steerer_sel3) + 1'd0: begin + builder_array_muxed25 <= 1'd0; + end + 1'd1: begin + builder_array_muxed25 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_we); + end + 2'd2: begin + builder_array_muxed25 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_we); + end + default: begin + builder_array_muxed25 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_we); + end + endcase +end +always @(*) begin + builder_array_muxed26 <= 1'd0; + case (main_sdram_steerer_sel3) + 1'd0: begin + builder_array_muxed26 <= 1'd0; + end + 1'd1: begin + builder_array_muxed26 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_is_read); + end + 2'd2: begin + builder_array_muxed26 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_read); + end + default: begin + builder_array_muxed26 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_is_read); + end + endcase +end +always @(*) begin + builder_array_muxed27 <= 1'd0; + case (main_sdram_steerer_sel3) + 1'd0: begin + builder_array_muxed27 <= 1'd0; + end + 1'd1: begin + builder_array_muxed27 <= ((main_sdram_choose_cmd_cmd_valid & main_sdram_choose_cmd_cmd_ready) & main_sdram_choose_cmd_cmd_payload_is_write); + end + 2'd2: begin + builder_array_muxed27 <= ((main_sdram_choose_req_cmd_valid & main_sdram_choose_req_cmd_ready) & main_sdram_choose_req_cmd_payload_is_write); + end + default: begin + builder_array_muxed27 <= ((main_sdram_cmd_valid & main_sdram_cmd_ready) & main_sdram_cmd_payload_is_write); + end + endcase +end +assign main_uart_phy_rx = builder_regs1; +assign builder_xilinxasyncresetsynchronizerimpl0 = ((~main_locked) | main_reset); +assign builder_xilinxasyncresetsynchronizerimpl1 = ((~main_locked) | main_reset); +assign builder_xilinxasyncresetsynchronizerimpl2 = ((~main_locked) | main_reset); +assign builder_xilinxasyncresetsynchronizerimpl3 = ((~main_locked) | main_reset); + +always @(posedge clk200_clk) begin + if ((main_reset_counter != 1'd0)) begin + main_reset_counter <= (main_reset_counter - 1'd1); + end else begin + main_ic_reset <= 1'd0; + end + if (clk200_rst) begin + main_reset_counter <= 4'd15; + main_ic_reset <= 1'd1; + end +end + +always @(posedge sys_clk) begin + if ((main_ctrl_bus_errors != 32'd4294967295)) begin + if (main_ctrl_bus_error) begin + main_ctrl_bus_errors <= (main_ctrl_bus_errors + 1'd1); + end + end + main_rom_bus_ack <= 1'd0; + if (((main_rom_bus_cyc & main_rom_bus_stb) & (~main_rom_bus_ack))) begin + main_rom_bus_ack <= 1'd1; + end + main_sram_bus_ack <= 1'd0; + if (((main_sram_bus_cyc & main_sram_bus_stb) & (~main_sram_bus_ack))) begin + main_sram_bus_ack <= 1'd1; + end + main_uart_phy_sink_ready <= 1'd0; + if (((main_uart_phy_sink_valid & (~main_uart_phy_tx_busy)) & (~main_uart_phy_sink_ready))) begin + main_uart_phy_tx_reg <= main_uart_phy_sink_payload_data; + main_uart_phy_tx_bitcount <= 1'd0; + main_uart_phy_tx_busy <= 1'd1; + serial_tx <= 1'd0; + end else begin + if ((main_uart_phy_uart_clk_txen & main_uart_phy_tx_busy)) begin + main_uart_phy_tx_bitcount <= (main_uart_phy_tx_bitcount + 1'd1); + if ((main_uart_phy_tx_bitcount == 4'd8)) begin + serial_tx <= 1'd1; + end else begin + if ((main_uart_phy_tx_bitcount == 4'd9)) begin + serial_tx <= 1'd1; + main_uart_phy_tx_busy <= 1'd0; + main_uart_phy_sink_ready <= 1'd1; + end else begin + serial_tx <= main_uart_phy_tx_reg[0]; + main_uart_phy_tx_reg <= {1'd0, main_uart_phy_tx_reg[7:1]}; + end + end + end + end + if (main_uart_phy_tx_busy) begin + {main_uart_phy_uart_clk_txen, main_uart_phy_phase_accumulator_tx} <= (main_uart_phy_phase_accumulator_tx + main_uart_phy_storage); + end else begin + {main_uart_phy_uart_clk_txen, main_uart_phy_phase_accumulator_tx} <= 1'd0; + end + main_uart_phy_source_valid <= 1'd0; + main_uart_phy_rx_r <= main_uart_phy_rx; + if ((~main_uart_phy_rx_busy)) begin + if (((~main_uart_phy_rx) & main_uart_phy_rx_r)) begin + main_uart_phy_rx_busy <= 1'd1; + main_uart_phy_rx_bitcount <= 1'd0; + end + end else begin + if (main_uart_phy_uart_clk_rxen) begin + main_uart_phy_rx_bitcount <= (main_uart_phy_rx_bitcount + 1'd1); + if ((main_uart_phy_rx_bitcount == 1'd0)) begin + if (main_uart_phy_rx) begin + main_uart_phy_rx_busy <= 1'd0; + end + end else begin + if ((main_uart_phy_rx_bitcount == 4'd9)) begin + main_uart_phy_rx_busy <= 1'd0; + if (main_uart_phy_rx) begin + main_uart_phy_source_payload_data <= main_uart_phy_rx_reg; + main_uart_phy_source_valid <= 1'd1; + end + end else begin + main_uart_phy_rx_reg <= {main_uart_phy_rx, main_uart_phy_rx_reg[7:1]}; + end + end + end + end + if (main_uart_phy_rx_busy) begin + {main_uart_phy_uart_clk_rxen, main_uart_phy_phase_accumulator_rx} <= (main_uart_phy_phase_accumulator_rx + main_uart_phy_storage); + end else begin + {main_uart_phy_uart_clk_rxen, main_uart_phy_phase_accumulator_rx} <= 32'd2147483648; + end + if (main_uart_tx_clear) begin + main_uart_tx_pending <= 1'd0; + end + main_uart_tx_old_trigger <= main_uart_tx_trigger; + if (((~main_uart_tx_trigger) & main_uart_tx_old_trigger)) begin + main_uart_tx_pending <= 1'd1; + end + if (main_uart_rx_clear) begin + main_uart_rx_pending <= 1'd0; + end + main_uart_rx_old_trigger <= main_uart_rx_trigger; + if (((~main_uart_rx_trigger) & main_uart_rx_old_trigger)) begin + main_uart_rx_pending <= 1'd1; + end + if (main_uart_tx_fifo_syncfifo_re) begin + main_uart_tx_fifo_readable <= 1'd1; + end else begin + if (main_uart_tx_fifo_re) begin + main_uart_tx_fifo_readable <= 1'd0; + end + end + if (((main_uart_tx_fifo_syncfifo_we & main_uart_tx_fifo_syncfifo_writable) & (~main_uart_tx_fifo_replace))) begin + main_uart_tx_fifo_produce <= (main_uart_tx_fifo_produce + 1'd1); + end + if (main_uart_tx_fifo_do_read) begin + main_uart_tx_fifo_consume <= (main_uart_tx_fifo_consume + 1'd1); + end + if (((main_uart_tx_fifo_syncfifo_we & main_uart_tx_fifo_syncfifo_writable) & (~main_uart_tx_fifo_replace))) begin + if ((~main_uart_tx_fifo_do_read)) begin + main_uart_tx_fifo_level0 <= (main_uart_tx_fifo_level0 + 1'd1); + end + end else begin + if (main_uart_tx_fifo_do_read) begin + main_uart_tx_fifo_level0 <= (main_uart_tx_fifo_level0 - 1'd1); + end + end + if (main_uart_rx_fifo_syncfifo_re) begin + main_uart_rx_fifo_readable <= 1'd1; + end else begin + if (main_uart_rx_fifo_re) begin + main_uart_rx_fifo_readable <= 1'd0; + end + end + if (((main_uart_rx_fifo_syncfifo_we & main_uart_rx_fifo_syncfifo_writable) & (~main_uart_rx_fifo_replace))) begin + main_uart_rx_fifo_produce <= (main_uart_rx_fifo_produce + 1'd1); + end + if (main_uart_rx_fifo_do_read) begin + main_uart_rx_fifo_consume <= (main_uart_rx_fifo_consume + 1'd1); + end + if (((main_uart_rx_fifo_syncfifo_we & main_uart_rx_fifo_syncfifo_writable) & (~main_uart_rx_fifo_replace))) begin + if ((~main_uart_rx_fifo_do_read)) begin + main_uart_rx_fifo_level0 <= (main_uart_rx_fifo_level0 + 1'd1); + end + end else begin + if (main_uart_rx_fifo_do_read) begin + main_uart_rx_fifo_level0 <= (main_uart_rx_fifo_level0 - 1'd1); + end + end + if (main_uart_reset) begin + main_uart_tx_pending <= 1'd0; + main_uart_tx_old_trigger <= 1'd0; + main_uart_rx_pending <= 1'd0; + main_uart_rx_old_trigger <= 1'd0; + main_uart_tx_fifo_readable <= 1'd0; + main_uart_tx_fifo_level0 <= 5'd0; + main_uart_tx_fifo_produce <= 4'd0; + main_uart_tx_fifo_consume <= 4'd0; + main_uart_rx_fifo_readable <= 1'd0; + main_uart_rx_fifo_level0 <= 5'd0; + main_uart_rx_fifo_produce <= 4'd0; + main_uart_rx_fifo_consume <= 4'd0; + end + if (main_timer0_en_storage) begin + if ((main_timer0_value == 1'd0)) begin + main_timer0_value <= main_timer0_reload_storage; + end else begin + main_timer0_value <= (main_timer0_value - 1'd1); + end + end else begin + main_timer0_value <= main_timer0_load_storage; + end + if (main_timer0_update_value_re) begin + main_timer0_value_status <= main_timer0_value; + end + if (main_timer0_zero_clear) begin + main_timer0_zero_pending <= 1'd0; + end + main_timer0_zero_old_trigger <= main_timer0_zero_trigger; + if (((~main_timer0_zero_trigger) & main_timer0_zero_old_trigger)) begin + main_timer0_zero_pending <= 1'd1; + end + builder_wb2csr_state <= builder_wb2csr_next_state; + if (main_a7ddrphy_dly_sel_storage[0]) begin + if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin + main_a7ddrphy_bitslip0_value <= 1'd0; + end else begin + if (main_a7ddrphy_rdly_dq_bitslip_re) begin + main_a7ddrphy_bitslip0_value <= (main_a7ddrphy_bitslip0_value + 1'd1); + end + end + end + if (main_a7ddrphy_dly_sel_storage[0]) begin + if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin + main_a7ddrphy_bitslip1_value <= 1'd0; + end else begin + if (main_a7ddrphy_rdly_dq_bitslip_re) begin + main_a7ddrphy_bitslip1_value <= (main_a7ddrphy_bitslip1_value + 1'd1); + end + end + end + if (main_a7ddrphy_dly_sel_storage[0]) begin + if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin + main_a7ddrphy_bitslip2_value <= 1'd0; + end else begin + if (main_a7ddrphy_rdly_dq_bitslip_re) begin + main_a7ddrphy_bitslip2_value <= (main_a7ddrphy_bitslip2_value + 1'd1); + end + end + end + if (main_a7ddrphy_dly_sel_storage[0]) begin + if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin + main_a7ddrphy_bitslip3_value <= 1'd0; + end else begin + if (main_a7ddrphy_rdly_dq_bitslip_re) begin + main_a7ddrphy_bitslip3_value <= (main_a7ddrphy_bitslip3_value + 1'd1); + end + end + end + if (main_a7ddrphy_dly_sel_storage[0]) begin + if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin + main_a7ddrphy_bitslip4_value <= 1'd0; + end else begin + if (main_a7ddrphy_rdly_dq_bitslip_re) begin + main_a7ddrphy_bitslip4_value <= (main_a7ddrphy_bitslip4_value + 1'd1); + end + end + end + if (main_a7ddrphy_dly_sel_storage[0]) begin + if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin + main_a7ddrphy_bitslip5_value <= 1'd0; + end else begin + if (main_a7ddrphy_rdly_dq_bitslip_re) begin + main_a7ddrphy_bitslip5_value <= (main_a7ddrphy_bitslip5_value + 1'd1); + end + end + end + if (main_a7ddrphy_dly_sel_storage[0]) begin + if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin + main_a7ddrphy_bitslip6_value <= 1'd0; + end else begin + if (main_a7ddrphy_rdly_dq_bitslip_re) begin + main_a7ddrphy_bitslip6_value <= (main_a7ddrphy_bitslip6_value + 1'd1); + end + end + end + if (main_a7ddrphy_dly_sel_storage[0]) begin + if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin + main_a7ddrphy_bitslip7_value <= 1'd0; + end else begin + if (main_a7ddrphy_rdly_dq_bitslip_re) begin + main_a7ddrphy_bitslip7_value <= (main_a7ddrphy_bitslip7_value + 1'd1); + end + end + end + if (main_a7ddrphy_dly_sel_storage[1]) begin + if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin + main_a7ddrphy_bitslip8_value <= 1'd0; + end else begin + if (main_a7ddrphy_rdly_dq_bitslip_re) begin + main_a7ddrphy_bitslip8_value <= (main_a7ddrphy_bitslip8_value + 1'd1); + end + end + end + if (main_a7ddrphy_dly_sel_storage[1]) begin + if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin + main_a7ddrphy_bitslip9_value <= 1'd0; + end else begin + if (main_a7ddrphy_rdly_dq_bitslip_re) begin + main_a7ddrphy_bitslip9_value <= (main_a7ddrphy_bitslip9_value + 1'd1); + end + end + end + if (main_a7ddrphy_dly_sel_storage[1]) begin + if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin + main_a7ddrphy_bitslip10_value <= 1'd0; + end else begin + if (main_a7ddrphy_rdly_dq_bitslip_re) begin + main_a7ddrphy_bitslip10_value <= (main_a7ddrphy_bitslip10_value + 1'd1); + end + end + end + if (main_a7ddrphy_dly_sel_storage[1]) begin + if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin + main_a7ddrphy_bitslip11_value <= 1'd0; + end else begin + if (main_a7ddrphy_rdly_dq_bitslip_re) begin + main_a7ddrphy_bitslip11_value <= (main_a7ddrphy_bitslip11_value + 1'd1); + end + end + end + if (main_a7ddrphy_dly_sel_storage[1]) begin + if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin + main_a7ddrphy_bitslip12_value <= 1'd0; + end else begin + if (main_a7ddrphy_rdly_dq_bitslip_re) begin + main_a7ddrphy_bitslip12_value <= (main_a7ddrphy_bitslip12_value + 1'd1); + end + end + end + if (main_a7ddrphy_dly_sel_storage[1]) begin + if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin + main_a7ddrphy_bitslip13_value <= 1'd0; + end else begin + if (main_a7ddrphy_rdly_dq_bitslip_re) begin + main_a7ddrphy_bitslip13_value <= (main_a7ddrphy_bitslip13_value + 1'd1); + end + end + end + if (main_a7ddrphy_dly_sel_storage[1]) begin + if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin + main_a7ddrphy_bitslip14_value <= 1'd0; + end else begin + if (main_a7ddrphy_rdly_dq_bitslip_re) begin + main_a7ddrphy_bitslip14_value <= (main_a7ddrphy_bitslip14_value + 1'd1); + end + end + end + if (main_a7ddrphy_dly_sel_storage[1]) begin + if (main_a7ddrphy_rdly_dq_bitslip_rst_re) begin + main_a7ddrphy_bitslip15_value <= 1'd0; + end else begin + if (main_a7ddrphy_rdly_dq_bitslip_re) begin + main_a7ddrphy_bitslip15_value <= (main_a7ddrphy_bitslip15_value + 1'd1); + end + end + end + main_a7ddrphy_n_rddata_en0 <= main_a7ddrphy_dfi_p2_rddata_en; + main_a7ddrphy_n_rddata_en1 <= main_a7ddrphy_n_rddata_en0; + main_a7ddrphy_n_rddata_en2 <= main_a7ddrphy_n_rddata_en1; + main_a7ddrphy_n_rddata_en3 <= main_a7ddrphy_n_rddata_en2; + main_a7ddrphy_n_rddata_en4 <= main_a7ddrphy_n_rddata_en3; + main_a7ddrphy_n_rddata_en5 <= main_a7ddrphy_n_rddata_en4; + main_a7ddrphy_n_rddata_en6 <= main_a7ddrphy_n_rddata_en5; + main_a7ddrphy_n_rddata_en7 <= main_a7ddrphy_n_rddata_en6; + main_a7ddrphy_dfi_p0_rddata_valid <= main_a7ddrphy_n_rddata_en7; + main_a7ddrphy_dfi_p1_rddata_valid <= main_a7ddrphy_n_rddata_en7; + main_a7ddrphy_dfi_p2_rddata_valid <= main_a7ddrphy_n_rddata_en7; + main_a7ddrphy_dfi_p3_rddata_valid <= main_a7ddrphy_n_rddata_en7; + main_a7ddrphy_last_wrdata_en <= {main_a7ddrphy_last_wrdata_en[2:0], main_a7ddrphy_dfi_p3_wrdata_en}; + main_a7ddrphy_oe_dqs <= main_a7ddrphy_oe; + main_a7ddrphy_oe_dq <= main_a7ddrphy_oe; + main_a7ddrphy_bitslip0_r <= {main_a7ddrphy_bitslip0_i, main_a7ddrphy_bitslip0_r[15:8]}; + case (main_a7ddrphy_bitslip0_value) + 1'd0: begin + main_a7ddrphy_bitslip0_o <= main_a7ddrphy_bitslip0_r[7:0]; + end + 1'd1: begin + main_a7ddrphy_bitslip0_o <= main_a7ddrphy_bitslip0_r[8:1]; + end + 2'd2: begin + main_a7ddrphy_bitslip0_o <= main_a7ddrphy_bitslip0_r[9:2]; + end + 2'd3: begin + main_a7ddrphy_bitslip0_o <= main_a7ddrphy_bitslip0_r[10:3]; + end + 3'd4: begin + main_a7ddrphy_bitslip0_o <= main_a7ddrphy_bitslip0_r[11:4]; + end + 3'd5: begin + main_a7ddrphy_bitslip0_o <= main_a7ddrphy_bitslip0_r[12:5]; + end + 3'd6: begin + main_a7ddrphy_bitslip0_o <= main_a7ddrphy_bitslip0_r[13:6]; + end + 3'd7: begin + main_a7ddrphy_bitslip0_o <= main_a7ddrphy_bitslip0_r[14:7]; + end + endcase + main_a7ddrphy_bitslip1_r <= {main_a7ddrphy_bitslip1_i, main_a7ddrphy_bitslip1_r[15:8]}; + case (main_a7ddrphy_bitslip1_value) + 1'd0: begin + main_a7ddrphy_bitslip1_o <= main_a7ddrphy_bitslip1_r[7:0]; + end + 1'd1: begin + main_a7ddrphy_bitslip1_o <= main_a7ddrphy_bitslip1_r[8:1]; + end + 2'd2: begin + main_a7ddrphy_bitslip1_o <= main_a7ddrphy_bitslip1_r[9:2]; + end + 2'd3: begin + main_a7ddrphy_bitslip1_o <= main_a7ddrphy_bitslip1_r[10:3]; + end + 3'd4: begin + main_a7ddrphy_bitslip1_o <= main_a7ddrphy_bitslip1_r[11:4]; + end + 3'd5: begin + main_a7ddrphy_bitslip1_o <= main_a7ddrphy_bitslip1_r[12:5]; + end + 3'd6: begin + main_a7ddrphy_bitslip1_o <= main_a7ddrphy_bitslip1_r[13:6]; + end + 3'd7: begin + main_a7ddrphy_bitslip1_o <= main_a7ddrphy_bitslip1_r[14:7]; + end + endcase + main_a7ddrphy_bitslip2_r <= {main_a7ddrphy_bitslip2_i, main_a7ddrphy_bitslip2_r[15:8]}; + case (main_a7ddrphy_bitslip2_value) + 1'd0: begin + main_a7ddrphy_bitslip2_o <= main_a7ddrphy_bitslip2_r[7:0]; + end + 1'd1: begin + main_a7ddrphy_bitslip2_o <= main_a7ddrphy_bitslip2_r[8:1]; + end + 2'd2: begin + main_a7ddrphy_bitslip2_o <= main_a7ddrphy_bitslip2_r[9:2]; + end + 2'd3: begin + main_a7ddrphy_bitslip2_o <= main_a7ddrphy_bitslip2_r[10:3]; + end + 3'd4: begin + main_a7ddrphy_bitslip2_o <= main_a7ddrphy_bitslip2_r[11:4]; + end + 3'd5: begin + main_a7ddrphy_bitslip2_o <= main_a7ddrphy_bitslip2_r[12:5]; + end + 3'd6: begin + main_a7ddrphy_bitslip2_o <= main_a7ddrphy_bitslip2_r[13:6]; + end + 3'd7: begin + main_a7ddrphy_bitslip2_o <= main_a7ddrphy_bitslip2_r[14:7]; + end + endcase + main_a7ddrphy_bitslip3_r <= {main_a7ddrphy_bitslip3_i, main_a7ddrphy_bitslip3_r[15:8]}; + case (main_a7ddrphy_bitslip3_value) + 1'd0: begin + main_a7ddrphy_bitslip3_o <= main_a7ddrphy_bitslip3_r[7:0]; + end + 1'd1: begin + main_a7ddrphy_bitslip3_o <= main_a7ddrphy_bitslip3_r[8:1]; + end + 2'd2: begin + main_a7ddrphy_bitslip3_o <= main_a7ddrphy_bitslip3_r[9:2]; + end + 2'd3: begin + main_a7ddrphy_bitslip3_o <= main_a7ddrphy_bitslip3_r[10:3]; + end + 3'd4: begin + main_a7ddrphy_bitslip3_o <= main_a7ddrphy_bitslip3_r[11:4]; + end + 3'd5: begin + main_a7ddrphy_bitslip3_o <= main_a7ddrphy_bitslip3_r[12:5]; + end + 3'd6: begin + main_a7ddrphy_bitslip3_o <= main_a7ddrphy_bitslip3_r[13:6]; + end + 3'd7: begin + main_a7ddrphy_bitslip3_o <= main_a7ddrphy_bitslip3_r[14:7]; + end + endcase + main_a7ddrphy_bitslip4_r <= {main_a7ddrphy_bitslip4_i, main_a7ddrphy_bitslip4_r[15:8]}; + case (main_a7ddrphy_bitslip4_value) + 1'd0: begin + main_a7ddrphy_bitslip4_o <= main_a7ddrphy_bitslip4_r[7:0]; + end + 1'd1: begin + main_a7ddrphy_bitslip4_o <= main_a7ddrphy_bitslip4_r[8:1]; + end + 2'd2: begin + main_a7ddrphy_bitslip4_o <= main_a7ddrphy_bitslip4_r[9:2]; + end + 2'd3: begin + main_a7ddrphy_bitslip4_o <= main_a7ddrphy_bitslip4_r[10:3]; + end + 3'd4: begin + main_a7ddrphy_bitslip4_o <= main_a7ddrphy_bitslip4_r[11:4]; + end + 3'd5: begin + main_a7ddrphy_bitslip4_o <= main_a7ddrphy_bitslip4_r[12:5]; + end + 3'd6: begin + main_a7ddrphy_bitslip4_o <= main_a7ddrphy_bitslip4_r[13:6]; + end + 3'd7: begin + main_a7ddrphy_bitslip4_o <= main_a7ddrphy_bitslip4_r[14:7]; + end + endcase + main_a7ddrphy_bitslip5_r <= {main_a7ddrphy_bitslip5_i, main_a7ddrphy_bitslip5_r[15:8]}; + case (main_a7ddrphy_bitslip5_value) + 1'd0: begin + main_a7ddrphy_bitslip5_o <= main_a7ddrphy_bitslip5_r[7:0]; + end + 1'd1: begin + main_a7ddrphy_bitslip5_o <= main_a7ddrphy_bitslip5_r[8:1]; + end + 2'd2: begin + main_a7ddrphy_bitslip5_o <= main_a7ddrphy_bitslip5_r[9:2]; + end + 2'd3: begin + main_a7ddrphy_bitslip5_o <= main_a7ddrphy_bitslip5_r[10:3]; + end + 3'd4: begin + main_a7ddrphy_bitslip5_o <= main_a7ddrphy_bitslip5_r[11:4]; + end + 3'd5: begin + main_a7ddrphy_bitslip5_o <= main_a7ddrphy_bitslip5_r[12:5]; + end + 3'd6: begin + main_a7ddrphy_bitslip5_o <= main_a7ddrphy_bitslip5_r[13:6]; + end + 3'd7: begin + main_a7ddrphy_bitslip5_o <= main_a7ddrphy_bitslip5_r[14:7]; + end + endcase + main_a7ddrphy_bitslip6_r <= {main_a7ddrphy_bitslip6_i, main_a7ddrphy_bitslip6_r[15:8]}; + case (main_a7ddrphy_bitslip6_value) + 1'd0: begin + main_a7ddrphy_bitslip6_o <= main_a7ddrphy_bitslip6_r[7:0]; + end + 1'd1: begin + main_a7ddrphy_bitslip6_o <= main_a7ddrphy_bitslip6_r[8:1]; + end + 2'd2: begin + main_a7ddrphy_bitslip6_o <= main_a7ddrphy_bitslip6_r[9:2]; + end + 2'd3: begin + main_a7ddrphy_bitslip6_o <= main_a7ddrphy_bitslip6_r[10:3]; + end + 3'd4: begin + main_a7ddrphy_bitslip6_o <= main_a7ddrphy_bitslip6_r[11:4]; + end + 3'd5: begin + main_a7ddrphy_bitslip6_o <= main_a7ddrphy_bitslip6_r[12:5]; + end + 3'd6: begin + main_a7ddrphy_bitslip6_o <= main_a7ddrphy_bitslip6_r[13:6]; + end + 3'd7: begin + main_a7ddrphy_bitslip6_o <= main_a7ddrphy_bitslip6_r[14:7]; + end + endcase + main_a7ddrphy_bitslip7_r <= {main_a7ddrphy_bitslip7_i, main_a7ddrphy_bitslip7_r[15:8]}; + case (main_a7ddrphy_bitslip7_value) + 1'd0: begin + main_a7ddrphy_bitslip7_o <= main_a7ddrphy_bitslip7_r[7:0]; + end + 1'd1: begin + main_a7ddrphy_bitslip7_o <= main_a7ddrphy_bitslip7_r[8:1]; + end + 2'd2: begin + main_a7ddrphy_bitslip7_o <= main_a7ddrphy_bitslip7_r[9:2]; + end + 2'd3: begin + main_a7ddrphy_bitslip7_o <= main_a7ddrphy_bitslip7_r[10:3]; + end + 3'd4: begin + main_a7ddrphy_bitslip7_o <= main_a7ddrphy_bitslip7_r[11:4]; + end + 3'd5: begin + main_a7ddrphy_bitslip7_o <= main_a7ddrphy_bitslip7_r[12:5]; + end + 3'd6: begin + main_a7ddrphy_bitslip7_o <= main_a7ddrphy_bitslip7_r[13:6]; + end + 3'd7: begin + main_a7ddrphy_bitslip7_o <= main_a7ddrphy_bitslip7_r[14:7]; + end + endcase + main_a7ddrphy_bitslip8_r <= {main_a7ddrphy_bitslip8_i, main_a7ddrphy_bitslip8_r[15:8]}; + case (main_a7ddrphy_bitslip8_value) + 1'd0: begin + main_a7ddrphy_bitslip8_o <= main_a7ddrphy_bitslip8_r[7:0]; + end + 1'd1: begin + main_a7ddrphy_bitslip8_o <= main_a7ddrphy_bitslip8_r[8:1]; + end + 2'd2: begin + main_a7ddrphy_bitslip8_o <= main_a7ddrphy_bitslip8_r[9:2]; + end + 2'd3: begin + main_a7ddrphy_bitslip8_o <= main_a7ddrphy_bitslip8_r[10:3]; + end + 3'd4: begin + main_a7ddrphy_bitslip8_o <= main_a7ddrphy_bitslip8_r[11:4]; + end + 3'd5: begin + main_a7ddrphy_bitslip8_o <= main_a7ddrphy_bitslip8_r[12:5]; + end + 3'd6: begin + main_a7ddrphy_bitslip8_o <= main_a7ddrphy_bitslip8_r[13:6]; + end + 3'd7: begin + main_a7ddrphy_bitslip8_o <= main_a7ddrphy_bitslip8_r[14:7]; + end + endcase + main_a7ddrphy_bitslip9_r <= {main_a7ddrphy_bitslip9_i, main_a7ddrphy_bitslip9_r[15:8]}; + case (main_a7ddrphy_bitslip9_value) + 1'd0: begin + main_a7ddrphy_bitslip9_o <= main_a7ddrphy_bitslip9_r[7:0]; + end + 1'd1: begin + main_a7ddrphy_bitslip9_o <= main_a7ddrphy_bitslip9_r[8:1]; + end + 2'd2: begin + main_a7ddrphy_bitslip9_o <= main_a7ddrphy_bitslip9_r[9:2]; + end + 2'd3: begin + main_a7ddrphy_bitslip9_o <= main_a7ddrphy_bitslip9_r[10:3]; + end + 3'd4: begin + main_a7ddrphy_bitslip9_o <= main_a7ddrphy_bitslip9_r[11:4]; + end + 3'd5: begin + main_a7ddrphy_bitslip9_o <= main_a7ddrphy_bitslip9_r[12:5]; + end + 3'd6: begin + main_a7ddrphy_bitslip9_o <= main_a7ddrphy_bitslip9_r[13:6]; + end + 3'd7: begin + main_a7ddrphy_bitslip9_o <= main_a7ddrphy_bitslip9_r[14:7]; + end + endcase + main_a7ddrphy_bitslip10_r <= {main_a7ddrphy_bitslip10_i, main_a7ddrphy_bitslip10_r[15:8]}; + case (main_a7ddrphy_bitslip10_value) + 1'd0: begin + main_a7ddrphy_bitslip10_o <= main_a7ddrphy_bitslip10_r[7:0]; + end + 1'd1: begin + main_a7ddrphy_bitslip10_o <= main_a7ddrphy_bitslip10_r[8:1]; + end + 2'd2: begin + main_a7ddrphy_bitslip10_o <= main_a7ddrphy_bitslip10_r[9:2]; + end + 2'd3: begin + main_a7ddrphy_bitslip10_o <= main_a7ddrphy_bitslip10_r[10:3]; + end + 3'd4: begin + main_a7ddrphy_bitslip10_o <= main_a7ddrphy_bitslip10_r[11:4]; + end + 3'd5: begin + main_a7ddrphy_bitslip10_o <= main_a7ddrphy_bitslip10_r[12:5]; + end + 3'd6: begin + main_a7ddrphy_bitslip10_o <= main_a7ddrphy_bitslip10_r[13:6]; + end + 3'd7: begin + main_a7ddrphy_bitslip10_o <= main_a7ddrphy_bitslip10_r[14:7]; + end + endcase + main_a7ddrphy_bitslip11_r <= {main_a7ddrphy_bitslip11_i, main_a7ddrphy_bitslip11_r[15:8]}; + case (main_a7ddrphy_bitslip11_value) + 1'd0: begin + main_a7ddrphy_bitslip11_o <= main_a7ddrphy_bitslip11_r[7:0]; + end + 1'd1: begin + main_a7ddrphy_bitslip11_o <= main_a7ddrphy_bitslip11_r[8:1]; + end + 2'd2: begin + main_a7ddrphy_bitslip11_o <= main_a7ddrphy_bitslip11_r[9:2]; + end + 2'd3: begin + main_a7ddrphy_bitslip11_o <= main_a7ddrphy_bitslip11_r[10:3]; + end + 3'd4: begin + main_a7ddrphy_bitslip11_o <= main_a7ddrphy_bitslip11_r[11:4]; + end + 3'd5: begin + main_a7ddrphy_bitslip11_o <= main_a7ddrphy_bitslip11_r[12:5]; + end + 3'd6: begin + main_a7ddrphy_bitslip11_o <= main_a7ddrphy_bitslip11_r[13:6]; + end + 3'd7: begin + main_a7ddrphy_bitslip11_o <= main_a7ddrphy_bitslip11_r[14:7]; + end + endcase + main_a7ddrphy_bitslip12_r <= {main_a7ddrphy_bitslip12_i, main_a7ddrphy_bitslip12_r[15:8]}; + case (main_a7ddrphy_bitslip12_value) + 1'd0: begin + main_a7ddrphy_bitslip12_o <= main_a7ddrphy_bitslip12_r[7:0]; + end + 1'd1: begin + main_a7ddrphy_bitslip12_o <= main_a7ddrphy_bitslip12_r[8:1]; + end + 2'd2: begin + main_a7ddrphy_bitslip12_o <= main_a7ddrphy_bitslip12_r[9:2]; + end + 2'd3: begin + main_a7ddrphy_bitslip12_o <= main_a7ddrphy_bitslip12_r[10:3]; + end + 3'd4: begin + main_a7ddrphy_bitslip12_o <= main_a7ddrphy_bitslip12_r[11:4]; + end + 3'd5: begin + main_a7ddrphy_bitslip12_o <= main_a7ddrphy_bitslip12_r[12:5]; + end + 3'd6: begin + main_a7ddrphy_bitslip12_o <= main_a7ddrphy_bitslip12_r[13:6]; + end + 3'd7: begin + main_a7ddrphy_bitslip12_o <= main_a7ddrphy_bitslip12_r[14:7]; + end + endcase + main_a7ddrphy_bitslip13_r <= {main_a7ddrphy_bitslip13_i, main_a7ddrphy_bitslip13_r[15:8]}; + case (main_a7ddrphy_bitslip13_value) + 1'd0: begin + main_a7ddrphy_bitslip13_o <= main_a7ddrphy_bitslip13_r[7:0]; + end + 1'd1: begin + main_a7ddrphy_bitslip13_o <= main_a7ddrphy_bitslip13_r[8:1]; + end + 2'd2: begin + main_a7ddrphy_bitslip13_o <= main_a7ddrphy_bitslip13_r[9:2]; + end + 2'd3: begin + main_a7ddrphy_bitslip13_o <= main_a7ddrphy_bitslip13_r[10:3]; + end + 3'd4: begin + main_a7ddrphy_bitslip13_o <= main_a7ddrphy_bitslip13_r[11:4]; + end + 3'd5: begin + main_a7ddrphy_bitslip13_o <= main_a7ddrphy_bitslip13_r[12:5]; + end + 3'd6: begin + main_a7ddrphy_bitslip13_o <= main_a7ddrphy_bitslip13_r[13:6]; + end + 3'd7: begin + main_a7ddrphy_bitslip13_o <= main_a7ddrphy_bitslip13_r[14:7]; + end + endcase + main_a7ddrphy_bitslip14_r <= {main_a7ddrphy_bitslip14_i, main_a7ddrphy_bitslip14_r[15:8]}; + case (main_a7ddrphy_bitslip14_value) + 1'd0: begin + main_a7ddrphy_bitslip14_o <= main_a7ddrphy_bitslip14_r[7:0]; + end + 1'd1: begin + main_a7ddrphy_bitslip14_o <= main_a7ddrphy_bitslip14_r[8:1]; + end + 2'd2: begin + main_a7ddrphy_bitslip14_o <= main_a7ddrphy_bitslip14_r[9:2]; + end + 2'd3: begin + main_a7ddrphy_bitslip14_o <= main_a7ddrphy_bitslip14_r[10:3]; + end + 3'd4: begin + main_a7ddrphy_bitslip14_o <= main_a7ddrphy_bitslip14_r[11:4]; + end + 3'd5: begin + main_a7ddrphy_bitslip14_o <= main_a7ddrphy_bitslip14_r[12:5]; + end + 3'd6: begin + main_a7ddrphy_bitslip14_o <= main_a7ddrphy_bitslip14_r[13:6]; + end + 3'd7: begin + main_a7ddrphy_bitslip14_o <= main_a7ddrphy_bitslip14_r[14:7]; + end + endcase + main_a7ddrphy_bitslip15_r <= {main_a7ddrphy_bitslip15_i, main_a7ddrphy_bitslip15_r[15:8]}; + case (main_a7ddrphy_bitslip15_value) + 1'd0: begin + main_a7ddrphy_bitslip15_o <= main_a7ddrphy_bitslip15_r[7:0]; + end + 1'd1: begin + main_a7ddrphy_bitslip15_o <= main_a7ddrphy_bitslip15_r[8:1]; + end + 2'd2: begin + main_a7ddrphy_bitslip15_o <= main_a7ddrphy_bitslip15_r[9:2]; + end + 2'd3: begin + main_a7ddrphy_bitslip15_o <= main_a7ddrphy_bitslip15_r[10:3]; + end + 3'd4: begin + main_a7ddrphy_bitslip15_o <= main_a7ddrphy_bitslip15_r[11:4]; + end + 3'd5: begin + main_a7ddrphy_bitslip15_o <= main_a7ddrphy_bitslip15_r[12:5]; + end + 3'd6: begin + main_a7ddrphy_bitslip15_o <= main_a7ddrphy_bitslip15_r[13:6]; + end + 3'd7: begin + main_a7ddrphy_bitslip15_o <= main_a7ddrphy_bitslip15_r[14:7]; + end + endcase + if (main_sdram_inti_p0_rddata_valid) begin + main_sdram_phaseinjector0_status <= main_sdram_inti_p0_rddata; + end + if (main_sdram_inti_p1_rddata_valid) begin + main_sdram_phaseinjector1_status <= main_sdram_inti_p1_rddata; + end + if (main_sdram_inti_p2_rddata_valid) begin + main_sdram_phaseinjector2_status <= main_sdram_inti_p2_rddata; + end + if (main_sdram_inti_p3_rddata_valid) begin + main_sdram_phaseinjector3_status <= main_sdram_inti_p3_rddata; + end + if ((main_sdram_timer_wait & (~main_sdram_timer_done0))) begin + main_sdram_timer_count1 <= (main_sdram_timer_count1 - 1'd1); + end else begin + main_sdram_timer_count1 <= 9'd390; + end + main_sdram_postponer_req_o <= 1'd0; + if (main_sdram_postponer_req_i) begin + main_sdram_postponer_count <= (main_sdram_postponer_count - 1'd1); + if ((main_sdram_postponer_count == 1'd0)) begin + main_sdram_postponer_count <= 1'd0; + main_sdram_postponer_req_o <= 1'd1; + end + end + if (main_sdram_sequencer_start0) begin + main_sdram_sequencer_count <= 1'd0; + end else begin + if (main_sdram_sequencer_done1) begin + if ((main_sdram_sequencer_count != 1'd0)) begin + main_sdram_sequencer_count <= (main_sdram_sequencer_count - 1'd1); + end + end + end + main_sdram_cmd_payload_a <= 1'd0; + main_sdram_cmd_payload_ba <= 1'd0; + main_sdram_cmd_payload_cas <= 1'd0; + main_sdram_cmd_payload_ras <= 1'd0; + main_sdram_cmd_payload_we <= 1'd0; + main_sdram_sequencer_done1 <= 1'd0; + if ((main_sdram_sequencer_start1 & (main_sdram_sequencer_counter == 1'd0))) begin + main_sdram_cmd_payload_a <= 11'd1024; + main_sdram_cmd_payload_ba <= 1'd0; + main_sdram_cmd_payload_cas <= 1'd0; + main_sdram_cmd_payload_ras <= 1'd1; + main_sdram_cmd_payload_we <= 1'd1; + end + if ((main_sdram_sequencer_counter == 2'd2)) begin + main_sdram_cmd_payload_a <= 1'd0; + main_sdram_cmd_payload_ba <= 1'd0; + main_sdram_cmd_payload_cas <= 1'd1; + main_sdram_cmd_payload_ras <= 1'd1; + main_sdram_cmd_payload_we <= 1'd0; + end + if ((main_sdram_sequencer_counter == 6'd34)) begin + main_sdram_cmd_payload_a <= 1'd0; + main_sdram_cmd_payload_ba <= 1'd0; + main_sdram_cmd_payload_cas <= 1'd0; + main_sdram_cmd_payload_ras <= 1'd0; + main_sdram_cmd_payload_we <= 1'd0; + main_sdram_sequencer_done1 <= 1'd1; + end + if ((main_sdram_sequencer_counter == 6'd34)) begin + main_sdram_sequencer_counter <= 1'd0; + end else begin + if ((main_sdram_sequencer_counter != 1'd0)) begin + main_sdram_sequencer_counter <= (main_sdram_sequencer_counter + 1'd1); + end else begin + if (main_sdram_sequencer_start1) begin + main_sdram_sequencer_counter <= 1'd1; + end + end + end + if ((main_sdram_zqcs_timer_wait & (~main_sdram_zqcs_timer_done0))) begin + main_sdram_zqcs_timer_count1 <= (main_sdram_zqcs_timer_count1 - 1'd1); + end else begin + main_sdram_zqcs_timer_count1 <= 26'd49999999; + end + main_sdram_zqcs_executer_done <= 1'd0; + if ((main_sdram_zqcs_executer_start & (main_sdram_zqcs_executer_counter == 1'd0))) begin + main_sdram_cmd_payload_a <= 11'd1024; + main_sdram_cmd_payload_ba <= 1'd0; + main_sdram_cmd_payload_cas <= 1'd0; + main_sdram_cmd_payload_ras <= 1'd1; + main_sdram_cmd_payload_we <= 1'd1; + end + if ((main_sdram_zqcs_executer_counter == 2'd2)) begin + main_sdram_cmd_payload_a <= 1'd0; + main_sdram_cmd_payload_ba <= 1'd0; + main_sdram_cmd_payload_cas <= 1'd0; + main_sdram_cmd_payload_ras <= 1'd0; + main_sdram_cmd_payload_we <= 1'd1; + end + if ((main_sdram_zqcs_executer_counter == 5'd18)) begin + main_sdram_cmd_payload_a <= 1'd0; + main_sdram_cmd_payload_ba <= 1'd0; + main_sdram_cmd_payload_cas <= 1'd0; + main_sdram_cmd_payload_ras <= 1'd0; + main_sdram_cmd_payload_we <= 1'd0; + main_sdram_zqcs_executer_done <= 1'd1; + end + if ((main_sdram_zqcs_executer_counter == 5'd18)) begin + main_sdram_zqcs_executer_counter <= 1'd0; + end else begin + if ((main_sdram_zqcs_executer_counter != 1'd0)) begin + main_sdram_zqcs_executer_counter <= (main_sdram_zqcs_executer_counter + 1'd1); + end else begin + if (main_sdram_zqcs_executer_start) begin + main_sdram_zqcs_executer_counter <= 1'd1; + end + end + end + builder_refresher_state <= builder_refresher_next_state; + if (main_sdram_bankmachine0_row_close) begin + main_sdram_bankmachine0_row_opened <= 1'd0; + end else begin + if (main_sdram_bankmachine0_row_open) begin + main_sdram_bankmachine0_row_opened <= 1'd1; + main_sdram_bankmachine0_row <= main_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~main_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin + main_sdram_bankmachine0_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine0_cmd_buffer_lookahead_produce + 1'd1); + end + if (main_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin + main_sdram_bankmachine0_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine0_cmd_buffer_lookahead_consume + 1'd1); + end + if (((main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~main_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin + if ((~main_sdram_bankmachine0_cmd_buffer_lookahead_do_read)) begin + main_sdram_bankmachine0_cmd_buffer_lookahead_level <= (main_sdram_bankmachine0_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (main_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin + main_sdram_bankmachine0_cmd_buffer_lookahead_level <= (main_sdram_bankmachine0_cmd_buffer_lookahead_level - 1'd1); + end + end + if (main_sdram_bankmachine0_cmd_buffer_pipe_ce) begin + main_sdram_bankmachine0_cmd_buffer_valid_n <= main_sdram_bankmachine0_cmd_buffer_sink_valid; + end + if (main_sdram_bankmachine0_cmd_buffer_pipe_ce) begin + main_sdram_bankmachine0_cmd_buffer_first_n <= (main_sdram_bankmachine0_cmd_buffer_sink_valid & main_sdram_bankmachine0_cmd_buffer_sink_first); + main_sdram_bankmachine0_cmd_buffer_last_n <= (main_sdram_bankmachine0_cmd_buffer_sink_valid & main_sdram_bankmachine0_cmd_buffer_sink_last); + end + if (main_sdram_bankmachine0_cmd_buffer_pipe_ce) begin + main_sdram_bankmachine0_cmd_buffer_source_payload_we <= main_sdram_bankmachine0_cmd_buffer_sink_payload_we; + main_sdram_bankmachine0_cmd_buffer_source_payload_addr <= main_sdram_bankmachine0_cmd_buffer_sink_payload_addr; + end + if (main_sdram_bankmachine0_twtpcon_valid) begin + main_sdram_bankmachine0_twtpcon_count <= 3'd4; + if (1'd0) begin + main_sdram_bankmachine0_twtpcon_ready <= 1'd1; + end else begin + main_sdram_bankmachine0_twtpcon_ready <= 1'd0; + end + end else begin + if ((~main_sdram_bankmachine0_twtpcon_ready)) begin + main_sdram_bankmachine0_twtpcon_count <= (main_sdram_bankmachine0_twtpcon_count - 1'd1); + if ((main_sdram_bankmachine0_twtpcon_count == 1'd1)) begin + main_sdram_bankmachine0_twtpcon_ready <= 1'd1; + end + end + end + if (main_sdram_bankmachine0_trccon_valid) begin + main_sdram_bankmachine0_trccon_count <= 2'd3; + if (1'd0) begin + main_sdram_bankmachine0_trccon_ready <= 1'd1; + end else begin + main_sdram_bankmachine0_trccon_ready <= 1'd0; + end + end else begin + if ((~main_sdram_bankmachine0_trccon_ready)) begin + main_sdram_bankmachine0_trccon_count <= (main_sdram_bankmachine0_trccon_count - 1'd1); + if ((main_sdram_bankmachine0_trccon_count == 1'd1)) begin + main_sdram_bankmachine0_trccon_ready <= 1'd1; + end + end + end + if (main_sdram_bankmachine0_trascon_valid) begin + main_sdram_bankmachine0_trascon_count <= 2'd2; + if (1'd0) begin + main_sdram_bankmachine0_trascon_ready <= 1'd1; + end else begin + main_sdram_bankmachine0_trascon_ready <= 1'd0; + end + end else begin + if ((~main_sdram_bankmachine0_trascon_ready)) begin + main_sdram_bankmachine0_trascon_count <= (main_sdram_bankmachine0_trascon_count - 1'd1); + if ((main_sdram_bankmachine0_trascon_count == 1'd1)) begin + main_sdram_bankmachine0_trascon_ready <= 1'd1; + end + end + end + builder_bankmachine0_state <= builder_bankmachine0_next_state; + if (main_sdram_bankmachine1_row_close) begin + main_sdram_bankmachine1_row_opened <= 1'd0; + end else begin + if (main_sdram_bankmachine1_row_open) begin + main_sdram_bankmachine1_row_opened <= 1'd1; + main_sdram_bankmachine1_row <= main_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~main_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin + main_sdram_bankmachine1_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine1_cmd_buffer_lookahead_produce + 1'd1); + end + if (main_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin + main_sdram_bankmachine1_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine1_cmd_buffer_lookahead_consume + 1'd1); + end + if (((main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~main_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin + if ((~main_sdram_bankmachine1_cmd_buffer_lookahead_do_read)) begin + main_sdram_bankmachine1_cmd_buffer_lookahead_level <= (main_sdram_bankmachine1_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (main_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin + main_sdram_bankmachine1_cmd_buffer_lookahead_level <= (main_sdram_bankmachine1_cmd_buffer_lookahead_level - 1'd1); + end + end + if (main_sdram_bankmachine1_cmd_buffer_pipe_ce) begin + main_sdram_bankmachine1_cmd_buffer_valid_n <= main_sdram_bankmachine1_cmd_buffer_sink_valid; + end + if (main_sdram_bankmachine1_cmd_buffer_pipe_ce) begin + main_sdram_bankmachine1_cmd_buffer_first_n <= (main_sdram_bankmachine1_cmd_buffer_sink_valid & main_sdram_bankmachine1_cmd_buffer_sink_first); + main_sdram_bankmachine1_cmd_buffer_last_n <= (main_sdram_bankmachine1_cmd_buffer_sink_valid & main_sdram_bankmachine1_cmd_buffer_sink_last); + end + if (main_sdram_bankmachine1_cmd_buffer_pipe_ce) begin + main_sdram_bankmachine1_cmd_buffer_source_payload_we <= main_sdram_bankmachine1_cmd_buffer_sink_payload_we; + main_sdram_bankmachine1_cmd_buffer_source_payload_addr <= main_sdram_bankmachine1_cmd_buffer_sink_payload_addr; + end + if (main_sdram_bankmachine1_twtpcon_valid) begin + main_sdram_bankmachine1_twtpcon_count <= 3'd4; + if (1'd0) begin + main_sdram_bankmachine1_twtpcon_ready <= 1'd1; + end else begin + main_sdram_bankmachine1_twtpcon_ready <= 1'd0; + end + end else begin + if ((~main_sdram_bankmachine1_twtpcon_ready)) begin + main_sdram_bankmachine1_twtpcon_count <= (main_sdram_bankmachine1_twtpcon_count - 1'd1); + if ((main_sdram_bankmachine1_twtpcon_count == 1'd1)) begin + main_sdram_bankmachine1_twtpcon_ready <= 1'd1; + end + end + end + if (main_sdram_bankmachine1_trccon_valid) begin + main_sdram_bankmachine1_trccon_count <= 2'd3; + if (1'd0) begin + main_sdram_bankmachine1_trccon_ready <= 1'd1; + end else begin + main_sdram_bankmachine1_trccon_ready <= 1'd0; + end + end else begin + if ((~main_sdram_bankmachine1_trccon_ready)) begin + main_sdram_bankmachine1_trccon_count <= (main_sdram_bankmachine1_trccon_count - 1'd1); + if ((main_sdram_bankmachine1_trccon_count == 1'd1)) begin + main_sdram_bankmachine1_trccon_ready <= 1'd1; + end + end + end + if (main_sdram_bankmachine1_trascon_valid) begin + main_sdram_bankmachine1_trascon_count <= 2'd2; + if (1'd0) begin + main_sdram_bankmachine1_trascon_ready <= 1'd1; + end else begin + main_sdram_bankmachine1_trascon_ready <= 1'd0; + end + end else begin + if ((~main_sdram_bankmachine1_trascon_ready)) begin + main_sdram_bankmachine1_trascon_count <= (main_sdram_bankmachine1_trascon_count - 1'd1); + if ((main_sdram_bankmachine1_trascon_count == 1'd1)) begin + main_sdram_bankmachine1_trascon_ready <= 1'd1; + end + end + end + builder_bankmachine1_state <= builder_bankmachine1_next_state; + if (main_sdram_bankmachine2_row_close) begin + main_sdram_bankmachine2_row_opened <= 1'd0; + end else begin + if (main_sdram_bankmachine2_row_open) begin + main_sdram_bankmachine2_row_opened <= 1'd1; + main_sdram_bankmachine2_row <= main_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~main_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin + main_sdram_bankmachine2_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine2_cmd_buffer_lookahead_produce + 1'd1); + end + if (main_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin + main_sdram_bankmachine2_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine2_cmd_buffer_lookahead_consume + 1'd1); + end + if (((main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~main_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin + if ((~main_sdram_bankmachine2_cmd_buffer_lookahead_do_read)) begin + main_sdram_bankmachine2_cmd_buffer_lookahead_level <= (main_sdram_bankmachine2_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (main_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin + main_sdram_bankmachine2_cmd_buffer_lookahead_level <= (main_sdram_bankmachine2_cmd_buffer_lookahead_level - 1'd1); + end + end + if (main_sdram_bankmachine2_cmd_buffer_pipe_ce) begin + main_sdram_bankmachine2_cmd_buffer_valid_n <= main_sdram_bankmachine2_cmd_buffer_sink_valid; + end + if (main_sdram_bankmachine2_cmd_buffer_pipe_ce) begin + main_sdram_bankmachine2_cmd_buffer_first_n <= (main_sdram_bankmachine2_cmd_buffer_sink_valid & main_sdram_bankmachine2_cmd_buffer_sink_first); + main_sdram_bankmachine2_cmd_buffer_last_n <= (main_sdram_bankmachine2_cmd_buffer_sink_valid & main_sdram_bankmachine2_cmd_buffer_sink_last); + end + if (main_sdram_bankmachine2_cmd_buffer_pipe_ce) begin + main_sdram_bankmachine2_cmd_buffer_source_payload_we <= main_sdram_bankmachine2_cmd_buffer_sink_payload_we; + main_sdram_bankmachine2_cmd_buffer_source_payload_addr <= main_sdram_bankmachine2_cmd_buffer_sink_payload_addr; + end + if (main_sdram_bankmachine2_twtpcon_valid) begin + main_sdram_bankmachine2_twtpcon_count <= 3'd4; + if (1'd0) begin + main_sdram_bankmachine2_twtpcon_ready <= 1'd1; + end else begin + main_sdram_bankmachine2_twtpcon_ready <= 1'd0; + end + end else begin + if ((~main_sdram_bankmachine2_twtpcon_ready)) begin + main_sdram_bankmachine2_twtpcon_count <= (main_sdram_bankmachine2_twtpcon_count - 1'd1); + if ((main_sdram_bankmachine2_twtpcon_count == 1'd1)) begin + main_sdram_bankmachine2_twtpcon_ready <= 1'd1; + end + end + end + if (main_sdram_bankmachine2_trccon_valid) begin + main_sdram_bankmachine2_trccon_count <= 2'd3; + if (1'd0) begin + main_sdram_bankmachine2_trccon_ready <= 1'd1; + end else begin + main_sdram_bankmachine2_trccon_ready <= 1'd0; + end + end else begin + if ((~main_sdram_bankmachine2_trccon_ready)) begin + main_sdram_bankmachine2_trccon_count <= (main_sdram_bankmachine2_trccon_count - 1'd1); + if ((main_sdram_bankmachine2_trccon_count == 1'd1)) begin + main_sdram_bankmachine2_trccon_ready <= 1'd1; + end + end + end + if (main_sdram_bankmachine2_trascon_valid) begin + main_sdram_bankmachine2_trascon_count <= 2'd2; + if (1'd0) begin + main_sdram_bankmachine2_trascon_ready <= 1'd1; + end else begin + main_sdram_bankmachine2_trascon_ready <= 1'd0; + end + end else begin + if ((~main_sdram_bankmachine2_trascon_ready)) begin + main_sdram_bankmachine2_trascon_count <= (main_sdram_bankmachine2_trascon_count - 1'd1); + if ((main_sdram_bankmachine2_trascon_count == 1'd1)) begin + main_sdram_bankmachine2_trascon_ready <= 1'd1; + end + end + end + builder_bankmachine2_state <= builder_bankmachine2_next_state; + if (main_sdram_bankmachine3_row_close) begin + main_sdram_bankmachine3_row_opened <= 1'd0; + end else begin + if (main_sdram_bankmachine3_row_open) begin + main_sdram_bankmachine3_row_opened <= 1'd1; + main_sdram_bankmachine3_row <= main_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~main_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin + main_sdram_bankmachine3_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine3_cmd_buffer_lookahead_produce + 1'd1); + end + if (main_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin + main_sdram_bankmachine3_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine3_cmd_buffer_lookahead_consume + 1'd1); + end + if (((main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~main_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin + if ((~main_sdram_bankmachine3_cmd_buffer_lookahead_do_read)) begin + main_sdram_bankmachine3_cmd_buffer_lookahead_level <= (main_sdram_bankmachine3_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (main_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin + main_sdram_bankmachine3_cmd_buffer_lookahead_level <= (main_sdram_bankmachine3_cmd_buffer_lookahead_level - 1'd1); + end + end + if (main_sdram_bankmachine3_cmd_buffer_pipe_ce) begin + main_sdram_bankmachine3_cmd_buffer_valid_n <= main_sdram_bankmachine3_cmd_buffer_sink_valid; + end + if (main_sdram_bankmachine3_cmd_buffer_pipe_ce) begin + main_sdram_bankmachine3_cmd_buffer_first_n <= (main_sdram_bankmachine3_cmd_buffer_sink_valid & main_sdram_bankmachine3_cmd_buffer_sink_first); + main_sdram_bankmachine3_cmd_buffer_last_n <= (main_sdram_bankmachine3_cmd_buffer_sink_valid & main_sdram_bankmachine3_cmd_buffer_sink_last); + end + if (main_sdram_bankmachine3_cmd_buffer_pipe_ce) begin + main_sdram_bankmachine3_cmd_buffer_source_payload_we <= main_sdram_bankmachine3_cmd_buffer_sink_payload_we; + main_sdram_bankmachine3_cmd_buffer_source_payload_addr <= main_sdram_bankmachine3_cmd_buffer_sink_payload_addr; + end + if (main_sdram_bankmachine3_twtpcon_valid) begin + main_sdram_bankmachine3_twtpcon_count <= 3'd4; + if (1'd0) begin + main_sdram_bankmachine3_twtpcon_ready <= 1'd1; + end else begin + main_sdram_bankmachine3_twtpcon_ready <= 1'd0; + end + end else begin + if ((~main_sdram_bankmachine3_twtpcon_ready)) begin + main_sdram_bankmachine3_twtpcon_count <= (main_sdram_bankmachine3_twtpcon_count - 1'd1); + if ((main_sdram_bankmachine3_twtpcon_count == 1'd1)) begin + main_sdram_bankmachine3_twtpcon_ready <= 1'd1; + end + end + end + if (main_sdram_bankmachine3_trccon_valid) begin + main_sdram_bankmachine3_trccon_count <= 2'd3; + if (1'd0) begin + main_sdram_bankmachine3_trccon_ready <= 1'd1; + end else begin + main_sdram_bankmachine3_trccon_ready <= 1'd0; + end + end else begin + if ((~main_sdram_bankmachine3_trccon_ready)) begin + main_sdram_bankmachine3_trccon_count <= (main_sdram_bankmachine3_trccon_count - 1'd1); + if ((main_sdram_bankmachine3_trccon_count == 1'd1)) begin + main_sdram_bankmachine3_trccon_ready <= 1'd1; + end + end + end + if (main_sdram_bankmachine3_trascon_valid) begin + main_sdram_bankmachine3_trascon_count <= 2'd2; + if (1'd0) begin + main_sdram_bankmachine3_trascon_ready <= 1'd1; + end else begin + main_sdram_bankmachine3_trascon_ready <= 1'd0; + end + end else begin + if ((~main_sdram_bankmachine3_trascon_ready)) begin + main_sdram_bankmachine3_trascon_count <= (main_sdram_bankmachine3_trascon_count - 1'd1); + if ((main_sdram_bankmachine3_trascon_count == 1'd1)) begin + main_sdram_bankmachine3_trascon_ready <= 1'd1; + end + end + end + builder_bankmachine3_state <= builder_bankmachine3_next_state; + if (main_sdram_bankmachine4_row_close) begin + main_sdram_bankmachine4_row_opened <= 1'd0; + end else begin + if (main_sdram_bankmachine4_row_open) begin + main_sdram_bankmachine4_row_opened <= 1'd1; + main_sdram_bankmachine4_row <= main_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~main_sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin + main_sdram_bankmachine4_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine4_cmd_buffer_lookahead_produce + 1'd1); + end + if (main_sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin + main_sdram_bankmachine4_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine4_cmd_buffer_lookahead_consume + 1'd1); + end + if (((main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & main_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~main_sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin + if ((~main_sdram_bankmachine4_cmd_buffer_lookahead_do_read)) begin + main_sdram_bankmachine4_cmd_buffer_lookahead_level <= (main_sdram_bankmachine4_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (main_sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin + main_sdram_bankmachine4_cmd_buffer_lookahead_level <= (main_sdram_bankmachine4_cmd_buffer_lookahead_level - 1'd1); + end + end + if (main_sdram_bankmachine4_cmd_buffer_pipe_ce) begin + main_sdram_bankmachine4_cmd_buffer_valid_n <= main_sdram_bankmachine4_cmd_buffer_sink_valid; + end + if (main_sdram_bankmachine4_cmd_buffer_pipe_ce) begin + main_sdram_bankmachine4_cmd_buffer_first_n <= (main_sdram_bankmachine4_cmd_buffer_sink_valid & main_sdram_bankmachine4_cmd_buffer_sink_first); + main_sdram_bankmachine4_cmd_buffer_last_n <= (main_sdram_bankmachine4_cmd_buffer_sink_valid & main_sdram_bankmachine4_cmd_buffer_sink_last); + end + if (main_sdram_bankmachine4_cmd_buffer_pipe_ce) begin + main_sdram_bankmachine4_cmd_buffer_source_payload_we <= main_sdram_bankmachine4_cmd_buffer_sink_payload_we; + main_sdram_bankmachine4_cmd_buffer_source_payload_addr <= main_sdram_bankmachine4_cmd_buffer_sink_payload_addr; + end + if (main_sdram_bankmachine4_twtpcon_valid) begin + main_sdram_bankmachine4_twtpcon_count <= 3'd4; + if (1'd0) begin + main_sdram_bankmachine4_twtpcon_ready <= 1'd1; + end else begin + main_sdram_bankmachine4_twtpcon_ready <= 1'd0; + end + end else begin + if ((~main_sdram_bankmachine4_twtpcon_ready)) begin + main_sdram_bankmachine4_twtpcon_count <= (main_sdram_bankmachine4_twtpcon_count - 1'd1); + if ((main_sdram_bankmachine4_twtpcon_count == 1'd1)) begin + main_sdram_bankmachine4_twtpcon_ready <= 1'd1; + end + end + end + if (main_sdram_bankmachine4_trccon_valid) begin + main_sdram_bankmachine4_trccon_count <= 2'd3; + if (1'd0) begin + main_sdram_bankmachine4_trccon_ready <= 1'd1; + end else begin + main_sdram_bankmachine4_trccon_ready <= 1'd0; + end + end else begin + if ((~main_sdram_bankmachine4_trccon_ready)) begin + main_sdram_bankmachine4_trccon_count <= (main_sdram_bankmachine4_trccon_count - 1'd1); + if ((main_sdram_bankmachine4_trccon_count == 1'd1)) begin + main_sdram_bankmachine4_trccon_ready <= 1'd1; + end + end + end + if (main_sdram_bankmachine4_trascon_valid) begin + main_sdram_bankmachine4_trascon_count <= 2'd2; + if (1'd0) begin + main_sdram_bankmachine4_trascon_ready <= 1'd1; + end else begin + main_sdram_bankmachine4_trascon_ready <= 1'd0; + end + end else begin + if ((~main_sdram_bankmachine4_trascon_ready)) begin + main_sdram_bankmachine4_trascon_count <= (main_sdram_bankmachine4_trascon_count - 1'd1); + if ((main_sdram_bankmachine4_trascon_count == 1'd1)) begin + main_sdram_bankmachine4_trascon_ready <= 1'd1; + end + end + end + builder_bankmachine4_state <= builder_bankmachine4_next_state; + if (main_sdram_bankmachine5_row_close) begin + main_sdram_bankmachine5_row_opened <= 1'd0; + end else begin + if (main_sdram_bankmachine5_row_open) begin + main_sdram_bankmachine5_row_opened <= 1'd1; + main_sdram_bankmachine5_row <= main_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~main_sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin + main_sdram_bankmachine5_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine5_cmd_buffer_lookahead_produce + 1'd1); + end + if (main_sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin + main_sdram_bankmachine5_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine5_cmd_buffer_lookahead_consume + 1'd1); + end + if (((main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & main_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~main_sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin + if ((~main_sdram_bankmachine5_cmd_buffer_lookahead_do_read)) begin + main_sdram_bankmachine5_cmd_buffer_lookahead_level <= (main_sdram_bankmachine5_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (main_sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin + main_sdram_bankmachine5_cmd_buffer_lookahead_level <= (main_sdram_bankmachine5_cmd_buffer_lookahead_level - 1'd1); + end + end + if (main_sdram_bankmachine5_cmd_buffer_pipe_ce) begin + main_sdram_bankmachine5_cmd_buffer_valid_n <= main_sdram_bankmachine5_cmd_buffer_sink_valid; + end + if (main_sdram_bankmachine5_cmd_buffer_pipe_ce) begin + main_sdram_bankmachine5_cmd_buffer_first_n <= (main_sdram_bankmachine5_cmd_buffer_sink_valid & main_sdram_bankmachine5_cmd_buffer_sink_first); + main_sdram_bankmachine5_cmd_buffer_last_n <= (main_sdram_bankmachine5_cmd_buffer_sink_valid & main_sdram_bankmachine5_cmd_buffer_sink_last); + end + if (main_sdram_bankmachine5_cmd_buffer_pipe_ce) begin + main_sdram_bankmachine5_cmd_buffer_source_payload_we <= main_sdram_bankmachine5_cmd_buffer_sink_payload_we; + main_sdram_bankmachine5_cmd_buffer_source_payload_addr <= main_sdram_bankmachine5_cmd_buffer_sink_payload_addr; + end + if (main_sdram_bankmachine5_twtpcon_valid) begin + main_sdram_bankmachine5_twtpcon_count <= 3'd4; + if (1'd0) begin + main_sdram_bankmachine5_twtpcon_ready <= 1'd1; + end else begin + main_sdram_bankmachine5_twtpcon_ready <= 1'd0; + end + end else begin + if ((~main_sdram_bankmachine5_twtpcon_ready)) begin + main_sdram_bankmachine5_twtpcon_count <= (main_sdram_bankmachine5_twtpcon_count - 1'd1); + if ((main_sdram_bankmachine5_twtpcon_count == 1'd1)) begin + main_sdram_bankmachine5_twtpcon_ready <= 1'd1; + end + end + end + if (main_sdram_bankmachine5_trccon_valid) begin + main_sdram_bankmachine5_trccon_count <= 2'd3; + if (1'd0) begin + main_sdram_bankmachine5_trccon_ready <= 1'd1; + end else begin + main_sdram_bankmachine5_trccon_ready <= 1'd0; + end + end else begin + if ((~main_sdram_bankmachine5_trccon_ready)) begin + main_sdram_bankmachine5_trccon_count <= (main_sdram_bankmachine5_trccon_count - 1'd1); + if ((main_sdram_bankmachine5_trccon_count == 1'd1)) begin + main_sdram_bankmachine5_trccon_ready <= 1'd1; + end + end + end + if (main_sdram_bankmachine5_trascon_valid) begin + main_sdram_bankmachine5_trascon_count <= 2'd2; + if (1'd0) begin + main_sdram_bankmachine5_trascon_ready <= 1'd1; + end else begin + main_sdram_bankmachine5_trascon_ready <= 1'd0; + end + end else begin + if ((~main_sdram_bankmachine5_trascon_ready)) begin + main_sdram_bankmachine5_trascon_count <= (main_sdram_bankmachine5_trascon_count - 1'd1); + if ((main_sdram_bankmachine5_trascon_count == 1'd1)) begin + main_sdram_bankmachine5_trascon_ready <= 1'd1; + end + end + end + builder_bankmachine5_state <= builder_bankmachine5_next_state; + if (main_sdram_bankmachine6_row_close) begin + main_sdram_bankmachine6_row_opened <= 1'd0; + end else begin + if (main_sdram_bankmachine6_row_open) begin + main_sdram_bankmachine6_row_opened <= 1'd1; + main_sdram_bankmachine6_row <= main_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~main_sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin + main_sdram_bankmachine6_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine6_cmd_buffer_lookahead_produce + 1'd1); + end + if (main_sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin + main_sdram_bankmachine6_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine6_cmd_buffer_lookahead_consume + 1'd1); + end + if (((main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & main_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~main_sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin + if ((~main_sdram_bankmachine6_cmd_buffer_lookahead_do_read)) begin + main_sdram_bankmachine6_cmd_buffer_lookahead_level <= (main_sdram_bankmachine6_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (main_sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin + main_sdram_bankmachine6_cmd_buffer_lookahead_level <= (main_sdram_bankmachine6_cmd_buffer_lookahead_level - 1'd1); + end + end + if (main_sdram_bankmachine6_cmd_buffer_pipe_ce) begin + main_sdram_bankmachine6_cmd_buffer_valid_n <= main_sdram_bankmachine6_cmd_buffer_sink_valid; + end + if (main_sdram_bankmachine6_cmd_buffer_pipe_ce) begin + main_sdram_bankmachine6_cmd_buffer_first_n <= (main_sdram_bankmachine6_cmd_buffer_sink_valid & main_sdram_bankmachine6_cmd_buffer_sink_first); + main_sdram_bankmachine6_cmd_buffer_last_n <= (main_sdram_bankmachine6_cmd_buffer_sink_valid & main_sdram_bankmachine6_cmd_buffer_sink_last); + end + if (main_sdram_bankmachine6_cmd_buffer_pipe_ce) begin + main_sdram_bankmachine6_cmd_buffer_source_payload_we <= main_sdram_bankmachine6_cmd_buffer_sink_payload_we; + main_sdram_bankmachine6_cmd_buffer_source_payload_addr <= main_sdram_bankmachine6_cmd_buffer_sink_payload_addr; + end + if (main_sdram_bankmachine6_twtpcon_valid) begin + main_sdram_bankmachine6_twtpcon_count <= 3'd4; + if (1'd0) begin + main_sdram_bankmachine6_twtpcon_ready <= 1'd1; + end else begin + main_sdram_bankmachine6_twtpcon_ready <= 1'd0; + end + end else begin + if ((~main_sdram_bankmachine6_twtpcon_ready)) begin + main_sdram_bankmachine6_twtpcon_count <= (main_sdram_bankmachine6_twtpcon_count - 1'd1); + if ((main_sdram_bankmachine6_twtpcon_count == 1'd1)) begin + main_sdram_bankmachine6_twtpcon_ready <= 1'd1; + end + end + end + if (main_sdram_bankmachine6_trccon_valid) begin + main_sdram_bankmachine6_trccon_count <= 2'd3; + if (1'd0) begin + main_sdram_bankmachine6_trccon_ready <= 1'd1; + end else begin + main_sdram_bankmachine6_trccon_ready <= 1'd0; + end + end else begin + if ((~main_sdram_bankmachine6_trccon_ready)) begin + main_sdram_bankmachine6_trccon_count <= (main_sdram_bankmachine6_trccon_count - 1'd1); + if ((main_sdram_bankmachine6_trccon_count == 1'd1)) begin + main_sdram_bankmachine6_trccon_ready <= 1'd1; + end + end + end + if (main_sdram_bankmachine6_trascon_valid) begin + main_sdram_bankmachine6_trascon_count <= 2'd2; + if (1'd0) begin + main_sdram_bankmachine6_trascon_ready <= 1'd1; + end else begin + main_sdram_bankmachine6_trascon_ready <= 1'd0; + end + end else begin + if ((~main_sdram_bankmachine6_trascon_ready)) begin + main_sdram_bankmachine6_trascon_count <= (main_sdram_bankmachine6_trascon_count - 1'd1); + if ((main_sdram_bankmachine6_trascon_count == 1'd1)) begin + main_sdram_bankmachine6_trascon_ready <= 1'd1; + end + end + end + builder_bankmachine6_state <= builder_bankmachine6_next_state; + if (main_sdram_bankmachine7_row_close) begin + main_sdram_bankmachine7_row_opened <= 1'd0; + end else begin + if (main_sdram_bankmachine7_row_open) begin + main_sdram_bankmachine7_row_opened <= 1'd1; + main_sdram_bankmachine7_row <= main_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7]; + end + end + if (((main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~main_sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin + main_sdram_bankmachine7_cmd_buffer_lookahead_produce <= (main_sdram_bankmachine7_cmd_buffer_lookahead_produce + 1'd1); + end + if (main_sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin + main_sdram_bankmachine7_cmd_buffer_lookahead_consume <= (main_sdram_bankmachine7_cmd_buffer_lookahead_consume + 1'd1); + end + if (((main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & main_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~main_sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin + if ((~main_sdram_bankmachine7_cmd_buffer_lookahead_do_read)) begin + main_sdram_bankmachine7_cmd_buffer_lookahead_level <= (main_sdram_bankmachine7_cmd_buffer_lookahead_level + 1'd1); + end + end else begin + if (main_sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin + main_sdram_bankmachine7_cmd_buffer_lookahead_level <= (main_sdram_bankmachine7_cmd_buffer_lookahead_level - 1'd1); + end + end + if (main_sdram_bankmachine7_cmd_buffer_pipe_ce) begin + main_sdram_bankmachine7_cmd_buffer_valid_n <= main_sdram_bankmachine7_cmd_buffer_sink_valid; + end + if (main_sdram_bankmachine7_cmd_buffer_pipe_ce) begin + main_sdram_bankmachine7_cmd_buffer_first_n <= (main_sdram_bankmachine7_cmd_buffer_sink_valid & main_sdram_bankmachine7_cmd_buffer_sink_first); + main_sdram_bankmachine7_cmd_buffer_last_n <= (main_sdram_bankmachine7_cmd_buffer_sink_valid & main_sdram_bankmachine7_cmd_buffer_sink_last); + end + if (main_sdram_bankmachine7_cmd_buffer_pipe_ce) begin + main_sdram_bankmachine7_cmd_buffer_source_payload_we <= main_sdram_bankmachine7_cmd_buffer_sink_payload_we; + main_sdram_bankmachine7_cmd_buffer_source_payload_addr <= main_sdram_bankmachine7_cmd_buffer_sink_payload_addr; + end + if (main_sdram_bankmachine7_twtpcon_valid) begin + main_sdram_bankmachine7_twtpcon_count <= 3'd4; + if (1'd0) begin + main_sdram_bankmachine7_twtpcon_ready <= 1'd1; + end else begin + main_sdram_bankmachine7_twtpcon_ready <= 1'd0; + end + end else begin + if ((~main_sdram_bankmachine7_twtpcon_ready)) begin + main_sdram_bankmachine7_twtpcon_count <= (main_sdram_bankmachine7_twtpcon_count - 1'd1); + if ((main_sdram_bankmachine7_twtpcon_count == 1'd1)) begin + main_sdram_bankmachine7_twtpcon_ready <= 1'd1; + end + end + end + if (main_sdram_bankmachine7_trccon_valid) begin + main_sdram_bankmachine7_trccon_count <= 2'd3; + if (1'd0) begin + main_sdram_bankmachine7_trccon_ready <= 1'd1; + end else begin + main_sdram_bankmachine7_trccon_ready <= 1'd0; + end + end else begin + if ((~main_sdram_bankmachine7_trccon_ready)) begin + main_sdram_bankmachine7_trccon_count <= (main_sdram_bankmachine7_trccon_count - 1'd1); + if ((main_sdram_bankmachine7_trccon_count == 1'd1)) begin + main_sdram_bankmachine7_trccon_ready <= 1'd1; + end + end + end + if (main_sdram_bankmachine7_trascon_valid) begin + main_sdram_bankmachine7_trascon_count <= 2'd2; + if (1'd0) begin + main_sdram_bankmachine7_trascon_ready <= 1'd1; + end else begin + main_sdram_bankmachine7_trascon_ready <= 1'd0; + end + end else begin + if ((~main_sdram_bankmachine7_trascon_ready)) begin + main_sdram_bankmachine7_trascon_count <= (main_sdram_bankmachine7_trascon_count - 1'd1); + if ((main_sdram_bankmachine7_trascon_count == 1'd1)) begin + main_sdram_bankmachine7_trascon_ready <= 1'd1; + end + end + end + builder_bankmachine7_state <= builder_bankmachine7_next_state; + if ((~main_sdram_en0)) begin + main_sdram_time0 <= 5'd31; + end else begin + if ((~main_sdram_max_time0)) begin + main_sdram_time0 <= (main_sdram_time0 - 1'd1); + end + end + if ((~main_sdram_en1)) begin + main_sdram_time1 <= 4'd15; + end else begin + if ((~main_sdram_max_time1)) begin + main_sdram_time1 <= (main_sdram_time1 - 1'd1); + end + end + if (main_sdram_choose_cmd_ce) begin + case (main_sdram_choose_cmd_grant) + 1'd0: begin + if (main_sdram_choose_cmd_request[1]) begin + main_sdram_choose_cmd_grant <= 1'd1; + end else begin + if (main_sdram_choose_cmd_request[2]) begin + main_sdram_choose_cmd_grant <= 2'd2; + end else begin + if (main_sdram_choose_cmd_request[3]) begin + main_sdram_choose_cmd_grant <= 2'd3; + end else begin + if (main_sdram_choose_cmd_request[4]) begin + main_sdram_choose_cmd_grant <= 3'd4; + end else begin + if (main_sdram_choose_cmd_request[5]) begin + main_sdram_choose_cmd_grant <= 3'd5; + end else begin + if (main_sdram_choose_cmd_request[6]) begin + main_sdram_choose_cmd_grant <= 3'd6; + end else begin + if (main_sdram_choose_cmd_request[7]) begin + main_sdram_choose_cmd_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (main_sdram_choose_cmd_request[2]) begin + main_sdram_choose_cmd_grant <= 2'd2; + end else begin + if (main_sdram_choose_cmd_request[3]) begin + main_sdram_choose_cmd_grant <= 2'd3; + end else begin + if (main_sdram_choose_cmd_request[4]) begin + main_sdram_choose_cmd_grant <= 3'd4; + end else begin + if (main_sdram_choose_cmd_request[5]) begin + main_sdram_choose_cmd_grant <= 3'd5; + end else begin + if (main_sdram_choose_cmd_request[6]) begin + main_sdram_choose_cmd_grant <= 3'd6; + end else begin + if (main_sdram_choose_cmd_request[7]) begin + main_sdram_choose_cmd_grant <= 3'd7; + end else begin + if (main_sdram_choose_cmd_request[0]) begin + main_sdram_choose_cmd_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (main_sdram_choose_cmd_request[3]) begin + main_sdram_choose_cmd_grant <= 2'd3; + end else begin + if (main_sdram_choose_cmd_request[4]) begin + main_sdram_choose_cmd_grant <= 3'd4; + end else begin + if (main_sdram_choose_cmd_request[5]) begin + main_sdram_choose_cmd_grant <= 3'd5; + end else begin + if (main_sdram_choose_cmd_request[6]) begin + main_sdram_choose_cmd_grant <= 3'd6; + end else begin + if (main_sdram_choose_cmd_request[7]) begin + main_sdram_choose_cmd_grant <= 3'd7; + end else begin + if (main_sdram_choose_cmd_request[0]) begin + main_sdram_choose_cmd_grant <= 1'd0; + end else begin + if (main_sdram_choose_cmd_request[1]) begin + main_sdram_choose_cmd_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (main_sdram_choose_cmd_request[4]) begin + main_sdram_choose_cmd_grant <= 3'd4; + end else begin + if (main_sdram_choose_cmd_request[5]) begin + main_sdram_choose_cmd_grant <= 3'd5; + end else begin + if (main_sdram_choose_cmd_request[6]) begin + main_sdram_choose_cmd_grant <= 3'd6; + end else begin + if (main_sdram_choose_cmd_request[7]) begin + main_sdram_choose_cmd_grant <= 3'd7; + end else begin + if (main_sdram_choose_cmd_request[0]) begin + main_sdram_choose_cmd_grant <= 1'd0; + end else begin + if (main_sdram_choose_cmd_request[1]) begin + main_sdram_choose_cmd_grant <= 1'd1; + end else begin + if (main_sdram_choose_cmd_request[2]) begin + main_sdram_choose_cmd_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (main_sdram_choose_cmd_request[5]) begin + main_sdram_choose_cmd_grant <= 3'd5; + end else begin + if (main_sdram_choose_cmd_request[6]) begin + main_sdram_choose_cmd_grant <= 3'd6; + end else begin + if (main_sdram_choose_cmd_request[7]) begin + main_sdram_choose_cmd_grant <= 3'd7; + end else begin + if (main_sdram_choose_cmd_request[0]) begin + main_sdram_choose_cmd_grant <= 1'd0; + end else begin + if (main_sdram_choose_cmd_request[1]) begin + main_sdram_choose_cmd_grant <= 1'd1; + end else begin + if (main_sdram_choose_cmd_request[2]) begin + main_sdram_choose_cmd_grant <= 2'd2; + end else begin + if (main_sdram_choose_cmd_request[3]) begin + main_sdram_choose_cmd_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (main_sdram_choose_cmd_request[6]) begin + main_sdram_choose_cmd_grant <= 3'd6; + end else begin + if (main_sdram_choose_cmd_request[7]) begin + main_sdram_choose_cmd_grant <= 3'd7; + end else begin + if (main_sdram_choose_cmd_request[0]) begin + main_sdram_choose_cmd_grant <= 1'd0; + end else begin + if (main_sdram_choose_cmd_request[1]) begin + main_sdram_choose_cmd_grant <= 1'd1; + end else begin + if (main_sdram_choose_cmd_request[2]) begin + main_sdram_choose_cmd_grant <= 2'd2; + end else begin + if (main_sdram_choose_cmd_request[3]) begin + main_sdram_choose_cmd_grant <= 2'd3; + end else begin + if (main_sdram_choose_cmd_request[4]) begin + main_sdram_choose_cmd_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (main_sdram_choose_cmd_request[7]) begin + main_sdram_choose_cmd_grant <= 3'd7; + end else begin + if (main_sdram_choose_cmd_request[0]) begin + main_sdram_choose_cmd_grant <= 1'd0; + end else begin + if (main_sdram_choose_cmd_request[1]) begin + main_sdram_choose_cmd_grant <= 1'd1; + end else begin + if (main_sdram_choose_cmd_request[2]) begin + main_sdram_choose_cmd_grant <= 2'd2; + end else begin + if (main_sdram_choose_cmd_request[3]) begin + main_sdram_choose_cmd_grant <= 2'd3; + end else begin + if (main_sdram_choose_cmd_request[4]) begin + main_sdram_choose_cmd_grant <= 3'd4; + end else begin + if (main_sdram_choose_cmd_request[5]) begin + main_sdram_choose_cmd_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (main_sdram_choose_cmd_request[0]) begin + main_sdram_choose_cmd_grant <= 1'd0; + end else begin + if (main_sdram_choose_cmd_request[1]) begin + main_sdram_choose_cmd_grant <= 1'd1; + end else begin + if (main_sdram_choose_cmd_request[2]) begin + main_sdram_choose_cmd_grant <= 2'd2; + end else begin + if (main_sdram_choose_cmd_request[3]) begin + main_sdram_choose_cmd_grant <= 2'd3; + end else begin + if (main_sdram_choose_cmd_request[4]) begin + main_sdram_choose_cmd_grant <= 3'd4; + end else begin + if (main_sdram_choose_cmd_request[5]) begin + main_sdram_choose_cmd_grant <= 3'd5; + end else begin + if (main_sdram_choose_cmd_request[6]) begin + main_sdram_choose_cmd_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + if (main_sdram_choose_req_ce) begin + case (main_sdram_choose_req_grant) + 1'd0: begin + if (main_sdram_choose_req_request[1]) begin + main_sdram_choose_req_grant <= 1'd1; + end else begin + if (main_sdram_choose_req_request[2]) begin + main_sdram_choose_req_grant <= 2'd2; + end else begin + if (main_sdram_choose_req_request[3]) begin + main_sdram_choose_req_grant <= 2'd3; + end else begin + if (main_sdram_choose_req_request[4]) begin + main_sdram_choose_req_grant <= 3'd4; + end else begin + if (main_sdram_choose_req_request[5]) begin + main_sdram_choose_req_grant <= 3'd5; + end else begin + if (main_sdram_choose_req_request[6]) begin + main_sdram_choose_req_grant <= 3'd6; + end else begin + if (main_sdram_choose_req_request[7]) begin + main_sdram_choose_req_grant <= 3'd7; + end + end + end + end + end + end + end + end + 1'd1: begin + if (main_sdram_choose_req_request[2]) begin + main_sdram_choose_req_grant <= 2'd2; + end else begin + if (main_sdram_choose_req_request[3]) begin + main_sdram_choose_req_grant <= 2'd3; + end else begin + if (main_sdram_choose_req_request[4]) begin + main_sdram_choose_req_grant <= 3'd4; + end else begin + if (main_sdram_choose_req_request[5]) begin + main_sdram_choose_req_grant <= 3'd5; + end else begin + if (main_sdram_choose_req_request[6]) begin + main_sdram_choose_req_grant <= 3'd6; + end else begin + if (main_sdram_choose_req_request[7]) begin + main_sdram_choose_req_grant <= 3'd7; + end else begin + if (main_sdram_choose_req_request[0]) begin + main_sdram_choose_req_grant <= 1'd0; + end + end + end + end + end + end + end + end + 2'd2: begin + if (main_sdram_choose_req_request[3]) begin + main_sdram_choose_req_grant <= 2'd3; + end else begin + if (main_sdram_choose_req_request[4]) begin + main_sdram_choose_req_grant <= 3'd4; + end else begin + if (main_sdram_choose_req_request[5]) begin + main_sdram_choose_req_grant <= 3'd5; + end else begin + if (main_sdram_choose_req_request[6]) begin + main_sdram_choose_req_grant <= 3'd6; + end else begin + if (main_sdram_choose_req_request[7]) begin + main_sdram_choose_req_grant <= 3'd7; + end else begin + if (main_sdram_choose_req_request[0]) begin + main_sdram_choose_req_grant <= 1'd0; + end else begin + if (main_sdram_choose_req_request[1]) begin + main_sdram_choose_req_grant <= 1'd1; + end + end + end + end + end + end + end + end + 2'd3: begin + if (main_sdram_choose_req_request[4]) begin + main_sdram_choose_req_grant <= 3'd4; + end else begin + if (main_sdram_choose_req_request[5]) begin + main_sdram_choose_req_grant <= 3'd5; + end else begin + if (main_sdram_choose_req_request[6]) begin + main_sdram_choose_req_grant <= 3'd6; + end else begin + if (main_sdram_choose_req_request[7]) begin + main_sdram_choose_req_grant <= 3'd7; + end else begin + if (main_sdram_choose_req_request[0]) begin + main_sdram_choose_req_grant <= 1'd0; + end else begin + if (main_sdram_choose_req_request[1]) begin + main_sdram_choose_req_grant <= 1'd1; + end else begin + if (main_sdram_choose_req_request[2]) begin + main_sdram_choose_req_grant <= 2'd2; + end + end + end + end + end + end + end + end + 3'd4: begin + if (main_sdram_choose_req_request[5]) begin + main_sdram_choose_req_grant <= 3'd5; + end else begin + if (main_sdram_choose_req_request[6]) begin + main_sdram_choose_req_grant <= 3'd6; + end else begin + if (main_sdram_choose_req_request[7]) begin + main_sdram_choose_req_grant <= 3'd7; + end else begin + if (main_sdram_choose_req_request[0]) begin + main_sdram_choose_req_grant <= 1'd0; + end else begin + if (main_sdram_choose_req_request[1]) begin + main_sdram_choose_req_grant <= 1'd1; + end else begin + if (main_sdram_choose_req_request[2]) begin + main_sdram_choose_req_grant <= 2'd2; + end else begin + if (main_sdram_choose_req_request[3]) begin + main_sdram_choose_req_grant <= 2'd3; + end + end + end + end + end + end + end + end + 3'd5: begin + if (main_sdram_choose_req_request[6]) begin + main_sdram_choose_req_grant <= 3'd6; + end else begin + if (main_sdram_choose_req_request[7]) begin + main_sdram_choose_req_grant <= 3'd7; + end else begin + if (main_sdram_choose_req_request[0]) begin + main_sdram_choose_req_grant <= 1'd0; + end else begin + if (main_sdram_choose_req_request[1]) begin + main_sdram_choose_req_grant <= 1'd1; + end else begin + if (main_sdram_choose_req_request[2]) begin + main_sdram_choose_req_grant <= 2'd2; + end else begin + if (main_sdram_choose_req_request[3]) begin + main_sdram_choose_req_grant <= 2'd3; + end else begin + if (main_sdram_choose_req_request[4]) begin + main_sdram_choose_req_grant <= 3'd4; + end + end + end + end + end + end + end + end + 3'd6: begin + if (main_sdram_choose_req_request[7]) begin + main_sdram_choose_req_grant <= 3'd7; + end else begin + if (main_sdram_choose_req_request[0]) begin + main_sdram_choose_req_grant <= 1'd0; + end else begin + if (main_sdram_choose_req_request[1]) begin + main_sdram_choose_req_grant <= 1'd1; + end else begin + if (main_sdram_choose_req_request[2]) begin + main_sdram_choose_req_grant <= 2'd2; + end else begin + if (main_sdram_choose_req_request[3]) begin + main_sdram_choose_req_grant <= 2'd3; + end else begin + if (main_sdram_choose_req_request[4]) begin + main_sdram_choose_req_grant <= 3'd4; + end else begin + if (main_sdram_choose_req_request[5]) begin + main_sdram_choose_req_grant <= 3'd5; + end + end + end + end + end + end + end + end + 3'd7: begin + if (main_sdram_choose_req_request[0]) begin + main_sdram_choose_req_grant <= 1'd0; + end else begin + if (main_sdram_choose_req_request[1]) begin + main_sdram_choose_req_grant <= 1'd1; + end else begin + if (main_sdram_choose_req_request[2]) begin + main_sdram_choose_req_grant <= 2'd2; + end else begin + if (main_sdram_choose_req_request[3]) begin + main_sdram_choose_req_grant <= 2'd3; + end else begin + if (main_sdram_choose_req_request[4]) begin + main_sdram_choose_req_grant <= 3'd4; + end else begin + if (main_sdram_choose_req_request[5]) begin + main_sdram_choose_req_grant <= 3'd5; + end else begin + if (main_sdram_choose_req_request[6]) begin + main_sdram_choose_req_grant <= 3'd6; + end + end + end + end + end + end + end + end + endcase + end + main_sdram_dfi_p0_cs_n <= 1'd0; + main_sdram_dfi_p0_bank <= builder_array_muxed0; + main_sdram_dfi_p0_address <= builder_array_muxed1; + main_sdram_dfi_p0_cas_n <= (~builder_array_muxed2); + main_sdram_dfi_p0_ras_n <= (~builder_array_muxed3); + main_sdram_dfi_p0_we_n <= (~builder_array_muxed4); + main_sdram_dfi_p0_rddata_en <= builder_array_muxed5; + main_sdram_dfi_p0_wrdata_en <= builder_array_muxed6; + main_sdram_dfi_p1_cs_n <= 1'd0; + main_sdram_dfi_p1_bank <= builder_array_muxed7; + main_sdram_dfi_p1_address <= builder_array_muxed8; + main_sdram_dfi_p1_cas_n <= (~builder_array_muxed9); + main_sdram_dfi_p1_ras_n <= (~builder_array_muxed10); + main_sdram_dfi_p1_we_n <= (~builder_array_muxed11); + main_sdram_dfi_p1_rddata_en <= builder_array_muxed12; + main_sdram_dfi_p1_wrdata_en <= builder_array_muxed13; + main_sdram_dfi_p2_cs_n <= 1'd0; + main_sdram_dfi_p2_bank <= builder_array_muxed14; + main_sdram_dfi_p2_address <= builder_array_muxed15; + main_sdram_dfi_p2_cas_n <= (~builder_array_muxed16); + main_sdram_dfi_p2_ras_n <= (~builder_array_muxed17); + main_sdram_dfi_p2_we_n <= (~builder_array_muxed18); + main_sdram_dfi_p2_rddata_en <= builder_array_muxed19; + main_sdram_dfi_p2_wrdata_en <= builder_array_muxed20; + main_sdram_dfi_p3_cs_n <= 1'd0; + main_sdram_dfi_p3_bank <= builder_array_muxed21; + main_sdram_dfi_p3_address <= builder_array_muxed22; + main_sdram_dfi_p3_cas_n <= (~builder_array_muxed23); + main_sdram_dfi_p3_ras_n <= (~builder_array_muxed24); + main_sdram_dfi_p3_we_n <= (~builder_array_muxed25); + main_sdram_dfi_p3_rddata_en <= builder_array_muxed26; + main_sdram_dfi_p3_wrdata_en <= builder_array_muxed27; + if (main_sdram_trrdcon_valid) begin + main_sdram_trrdcon_count <= 1'd1; + if (1'd0) begin + main_sdram_trrdcon_ready <= 1'd1; + end else begin + main_sdram_trrdcon_ready <= 1'd0; + end + end else begin + if ((~main_sdram_trrdcon_ready)) begin + main_sdram_trrdcon_count <= (main_sdram_trrdcon_count - 1'd1); + if ((main_sdram_trrdcon_count == 1'd1)) begin + main_sdram_trrdcon_ready <= 1'd1; + end + end + end + main_sdram_tfawcon_window <= {main_sdram_tfawcon_window, main_sdram_tfawcon_valid}; + if ((main_sdram_tfawcon_count < 3'd4)) begin + if ((main_sdram_tfawcon_count == 2'd3)) begin + main_sdram_tfawcon_ready <= (~main_sdram_tfawcon_valid); + end else begin + main_sdram_tfawcon_ready <= 1'd1; + end + end + if (main_sdram_tccdcon_valid) begin + main_sdram_tccdcon_count <= 1'd0; + if (1'd1) begin + main_sdram_tccdcon_ready <= 1'd1; + end else begin + main_sdram_tccdcon_ready <= 1'd0; + end + end else begin + if ((~main_sdram_tccdcon_ready)) begin + main_sdram_tccdcon_count <= (main_sdram_tccdcon_count - 1'd1); + if ((main_sdram_tccdcon_count == 1'd1)) begin + main_sdram_tccdcon_ready <= 1'd1; + end + end + end + if (main_sdram_twtrcon_valid) begin + main_sdram_twtrcon_count <= 3'd4; + if (1'd0) begin + main_sdram_twtrcon_ready <= 1'd1; + end else begin + main_sdram_twtrcon_ready <= 1'd0; + end + end else begin + if ((~main_sdram_twtrcon_ready)) begin + main_sdram_twtrcon_count <= (main_sdram_twtrcon_count - 1'd1); + if ((main_sdram_twtrcon_count == 1'd1)) begin + main_sdram_twtrcon_ready <= 1'd1; + end + end + end + builder_multiplexer_state <= builder_multiplexer_next_state; + if (((builder_roundrobin0_grant == 1'd0) & main_sdram_interface_bank0_rdata_valid)) begin + builder_rbank <= 1'd0; + end + if (((builder_roundrobin0_grant == 1'd0) & main_sdram_interface_bank0_wdata_ready)) begin + builder_wbank <= 1'd0; + end + if (((builder_roundrobin1_grant == 1'd0) & main_sdram_interface_bank1_rdata_valid)) begin + builder_rbank <= 1'd1; + end + if (((builder_roundrobin1_grant == 1'd0) & main_sdram_interface_bank1_wdata_ready)) begin + builder_wbank <= 1'd1; + end + if (((builder_roundrobin2_grant == 1'd0) & main_sdram_interface_bank2_rdata_valid)) begin + builder_rbank <= 2'd2; + end + if (((builder_roundrobin2_grant == 1'd0) & main_sdram_interface_bank2_wdata_ready)) begin + builder_wbank <= 2'd2; + end + if (((builder_roundrobin3_grant == 1'd0) & main_sdram_interface_bank3_rdata_valid)) begin + builder_rbank <= 2'd3; + end + if (((builder_roundrobin3_grant == 1'd0) & main_sdram_interface_bank3_wdata_ready)) begin + builder_wbank <= 2'd3; + end + if (((builder_roundrobin4_grant == 1'd0) & main_sdram_interface_bank4_rdata_valid)) begin + builder_rbank <= 3'd4; + end + if (((builder_roundrobin4_grant == 1'd0) & main_sdram_interface_bank4_wdata_ready)) begin + builder_wbank <= 3'd4; + end + if (((builder_roundrobin5_grant == 1'd0) & main_sdram_interface_bank5_rdata_valid)) begin + builder_rbank <= 3'd5; + end + if (((builder_roundrobin5_grant == 1'd0) & main_sdram_interface_bank5_wdata_ready)) begin + builder_wbank <= 3'd5; + end + if (((builder_roundrobin6_grant == 1'd0) & main_sdram_interface_bank6_rdata_valid)) begin + builder_rbank <= 3'd6; + end + if (((builder_roundrobin6_grant == 1'd0) & main_sdram_interface_bank6_wdata_ready)) begin + builder_wbank <= 3'd6; + end + if (((builder_roundrobin7_grant == 1'd0) & main_sdram_interface_bank7_rdata_valid)) begin + builder_rbank <= 3'd7; + end + if (((builder_roundrobin7_grant == 1'd0) & main_sdram_interface_bank7_wdata_ready)) begin + builder_wbank <= 3'd7; + end + builder_new_master_wdata_ready0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_sdram_interface_bank0_wdata_ready)) | ((builder_roundrobin1_grant == 1'd0) & main_sdram_interface_bank1_wdata_ready)) | ((builder_roundrobin2_grant == 1'd0) & main_sdram_interface_bank2_wdata_ready)) | ((builder_roundrobin3_grant == 1'd0) & main_sdram_interface_bank3_wdata_ready)) | ((builder_roundrobin4_grant == 1'd0) & main_sdram_interface_bank4_wdata_ready)) | ((builder_roundrobin5_grant == 1'd0) & main_sdram_interface_bank5_wdata_ready)) | ((builder_roundrobin6_grant == 1'd0) & main_sdram_interface_bank6_wdata_ready)) | ((builder_roundrobin7_grant == 1'd0) & main_sdram_interface_bank7_wdata_ready)); + builder_new_master_wdata_ready1 <= builder_new_master_wdata_ready0; + builder_new_master_wdata_ready2 <= builder_new_master_wdata_ready1; + builder_new_master_rdata_valid0 <= ((((((((1'd0 | ((builder_roundrobin0_grant == 1'd0) & main_sdram_interface_bank0_rdata_valid)) | ((builder_roundrobin1_grant == 1'd0) & main_sdram_interface_bank1_rdata_valid)) | ((builder_roundrobin2_grant == 1'd0) & main_sdram_interface_bank2_rdata_valid)) | ((builder_roundrobin3_grant == 1'd0) & main_sdram_interface_bank3_rdata_valid)) | ((builder_roundrobin4_grant == 1'd0) & main_sdram_interface_bank4_rdata_valid)) | ((builder_roundrobin5_grant == 1'd0) & main_sdram_interface_bank5_rdata_valid)) | ((builder_roundrobin6_grant == 1'd0) & main_sdram_interface_bank6_rdata_valid)) | ((builder_roundrobin7_grant == 1'd0) & main_sdram_interface_bank7_rdata_valid)); + builder_new_master_rdata_valid1 <= builder_new_master_rdata_valid0; + builder_new_master_rdata_valid2 <= builder_new_master_rdata_valid1; + builder_new_master_rdata_valid3 <= builder_new_master_rdata_valid2; + builder_new_master_rdata_valid4 <= builder_new_master_rdata_valid3; + builder_new_master_rdata_valid5 <= builder_new_master_rdata_valid4; + builder_new_master_rdata_valid6 <= builder_new_master_rdata_valid5; + builder_new_master_rdata_valid7 <= builder_new_master_rdata_valid6; + builder_new_master_rdata_valid8 <= builder_new_master_rdata_valid7; + builder_new_master_rdata_valid9 <= builder_new_master_rdata_valid8; + main_adr_offset_r <= main_interface0_wb_sdram_adr[1:0]; + builder_fullmemorywe_state <= builder_fullmemorywe_next_state; + builder_litedramwishbone2native_state <= builder_litedramwishbone2native_next_state; + case (builder_minsoc_grant) + 1'd0: begin + if ((~builder_minsoc_request[0])) begin + if (builder_minsoc_request[1]) begin + builder_minsoc_grant <= 1'd1; + end + end + end + 1'd1: begin + if ((~builder_minsoc_request[1])) begin + if (builder_minsoc_request[0]) begin + builder_minsoc_grant <= 1'd0; + end + end + end + endcase + builder_minsoc_slave_sel_r <= builder_minsoc_slave_sel; + if (builder_minsoc_wait) begin + if ((~builder_minsoc_done)) begin + builder_minsoc_count <= (builder_minsoc_count - 1'd1); + end + end else begin + builder_minsoc_count <= 20'd1000000; + end + builder_minsoc_interface0_bank_bus_dat_r <= 1'd0; + if (builder_minsoc_csrbank0_sel) begin + case (builder_minsoc_interface0_bank_bus_adr[3:0]) + 1'd0: begin + builder_minsoc_interface0_bank_bus_dat_r <= main_ctrl_reset_reset_w; + end + 1'd1: begin + builder_minsoc_interface0_bank_bus_dat_r <= builder_minsoc_csrbank0_scratch3_w; + end + 2'd2: begin + builder_minsoc_interface0_bank_bus_dat_r <= builder_minsoc_csrbank0_scratch2_w; + end + 2'd3: begin + builder_minsoc_interface0_bank_bus_dat_r <= builder_minsoc_csrbank0_scratch1_w; + end + 3'd4: begin + builder_minsoc_interface0_bank_bus_dat_r <= builder_minsoc_csrbank0_scratch0_w; + end + 3'd5: begin + builder_minsoc_interface0_bank_bus_dat_r <= builder_minsoc_csrbank0_bus_errors3_w; + end + 3'd6: begin + builder_minsoc_interface0_bank_bus_dat_r <= builder_minsoc_csrbank0_bus_errors2_w; + end + 3'd7: begin + builder_minsoc_interface0_bank_bus_dat_r <= builder_minsoc_csrbank0_bus_errors1_w; + end + 4'd8: begin + builder_minsoc_interface0_bank_bus_dat_r <= builder_minsoc_csrbank0_bus_errors0_w; + end + endcase + end + if (builder_minsoc_csrbank0_scratch3_re) begin + main_ctrl_storage[31:24] <= builder_minsoc_csrbank0_scratch3_r; + end + if (builder_minsoc_csrbank0_scratch2_re) begin + main_ctrl_storage[23:16] <= builder_minsoc_csrbank0_scratch2_r; + end + if (builder_minsoc_csrbank0_scratch1_re) begin + main_ctrl_storage[15:8] <= builder_minsoc_csrbank0_scratch1_r; + end + if (builder_minsoc_csrbank0_scratch0_re) begin + main_ctrl_storage[7:0] <= builder_minsoc_csrbank0_scratch0_r; + end + main_ctrl_re <= builder_minsoc_csrbank0_scratch0_re; + builder_minsoc_interface1_bank_bus_dat_r <= 1'd0; + if (builder_minsoc_csrbank1_sel) begin + case (builder_minsoc_interface1_bank_bus_adr[2:0]) + 1'd0: begin + builder_minsoc_interface1_bank_bus_dat_r <= builder_minsoc_csrbank1_half_sys8x_taps0_w; + end + 1'd1: begin + builder_minsoc_interface1_bank_bus_dat_r <= main_a7ddrphy_cdly_rst_w; + end + 2'd2: begin + builder_minsoc_interface1_bank_bus_dat_r <= main_a7ddrphy_cdly_inc_w; + end + 2'd3: begin + builder_minsoc_interface1_bank_bus_dat_r <= builder_minsoc_csrbank1_dly_sel0_w; + end + 3'd4: begin + builder_minsoc_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_rst_w; + end + 3'd5: begin + builder_minsoc_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_inc_w; + end + 3'd6: begin + builder_minsoc_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_rst_w; + end + 3'd7: begin + builder_minsoc_interface1_bank_bus_dat_r <= main_a7ddrphy_rdly_dq_bitslip_w; + end + endcase + end + if (builder_minsoc_csrbank1_half_sys8x_taps0_re) begin + main_a7ddrphy_half_sys8x_taps_storage[4:0] <= builder_minsoc_csrbank1_half_sys8x_taps0_r; + end + main_a7ddrphy_half_sys8x_taps_re <= builder_minsoc_csrbank1_half_sys8x_taps0_re; + if (builder_minsoc_csrbank1_dly_sel0_re) begin + main_a7ddrphy_dly_sel_storage[1:0] <= builder_minsoc_csrbank1_dly_sel0_r; + end + main_a7ddrphy_dly_sel_re <= builder_minsoc_csrbank1_dly_sel0_re; + builder_minsoc_interface2_bank_bus_dat_r <= 1'd0; + if (builder_minsoc_csrbank2_sel) begin + case (builder_minsoc_interface2_bank_bus_adr[5:0]) + 1'd0: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_control0_w; + end + 1'd1: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_command0_w; + end + 2'd2: begin + builder_minsoc_interface2_bank_bus_dat_r <= main_sdram_phaseinjector0_command_issue_w; + end + 2'd3: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_address1_w; + end + 3'd4: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_address0_w; + end + 3'd5: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_baddress0_w; + end + 3'd6: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_wrdata3_w; + end + 3'd7: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_wrdata2_w; + end + 4'd8: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_wrdata1_w; + end + 4'd9: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_wrdata0_w; + end + 4'd10: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_rddata3_w; + end + 4'd11: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_rddata2_w; + end + 4'd12: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_rddata1_w; + end + 4'd13: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi0_rddata0_w; + end + 4'd14: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_command0_w; + end + 4'd15: begin + builder_minsoc_interface2_bank_bus_dat_r <= main_sdram_phaseinjector1_command_issue_w; + end + 5'd16: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_address1_w; + end + 5'd17: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_address0_w; + end + 5'd18: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_baddress0_w; + end + 5'd19: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_wrdata3_w; + end + 5'd20: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_wrdata2_w; + end + 5'd21: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_wrdata1_w; + end + 5'd22: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_wrdata0_w; + end + 5'd23: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_rddata3_w; + end + 5'd24: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_rddata2_w; + end + 5'd25: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_rddata1_w; + end + 5'd26: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi1_rddata0_w; + end + 5'd27: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_command0_w; + end + 5'd28: begin + builder_minsoc_interface2_bank_bus_dat_r <= main_sdram_phaseinjector2_command_issue_w; + end + 5'd29: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_address1_w; + end + 5'd30: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_address0_w; + end + 5'd31: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_baddress0_w; + end + 6'd32: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_wrdata3_w; + end + 6'd33: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_wrdata2_w; + end + 6'd34: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_wrdata1_w; + end + 6'd35: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_wrdata0_w; + end + 6'd36: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_rddata3_w; + end + 6'd37: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_rddata2_w; + end + 6'd38: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_rddata1_w; + end + 6'd39: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi2_rddata0_w; + end + 6'd40: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_command0_w; + end + 6'd41: begin + builder_minsoc_interface2_bank_bus_dat_r <= main_sdram_phaseinjector3_command_issue_w; + end + 6'd42: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_address1_w; + end + 6'd43: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_address0_w; + end + 6'd44: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_baddress0_w; + end + 6'd45: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_wrdata3_w; + end + 6'd46: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_wrdata2_w; + end + 6'd47: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_wrdata1_w; + end + 6'd48: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_wrdata0_w; + end + 6'd49: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_rddata3_w; + end + 6'd50: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_rddata2_w; + end + 6'd51: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_rddata1_w; + end + 6'd52: begin + builder_minsoc_interface2_bank_bus_dat_r <= builder_minsoc_csrbank2_dfii_pi3_rddata0_w; + end + endcase + end + if (builder_minsoc_csrbank2_dfii_control0_re) begin + main_sdram_storage[3:0] <= builder_minsoc_csrbank2_dfii_control0_r; + end + main_sdram_re <= builder_minsoc_csrbank2_dfii_control0_re; + if (builder_minsoc_csrbank2_dfii_pi0_command0_re) begin + main_sdram_phaseinjector0_command_storage[5:0] <= builder_minsoc_csrbank2_dfii_pi0_command0_r; + end + main_sdram_phaseinjector0_command_re <= builder_minsoc_csrbank2_dfii_pi0_command0_re; + if (builder_minsoc_csrbank2_dfii_pi0_address1_re) begin + main_sdram_phaseinjector0_address_storage[13:8] <= builder_minsoc_csrbank2_dfii_pi0_address1_r; + end + if (builder_minsoc_csrbank2_dfii_pi0_address0_re) begin + main_sdram_phaseinjector0_address_storage[7:0] <= builder_minsoc_csrbank2_dfii_pi0_address0_r; + end + main_sdram_phaseinjector0_address_re <= builder_minsoc_csrbank2_dfii_pi0_address0_re; + if (builder_minsoc_csrbank2_dfii_pi0_baddress0_re) begin + main_sdram_phaseinjector0_baddress_storage[2:0] <= builder_minsoc_csrbank2_dfii_pi0_baddress0_r; + end + main_sdram_phaseinjector0_baddress_re <= builder_minsoc_csrbank2_dfii_pi0_baddress0_re; + if (builder_minsoc_csrbank2_dfii_pi0_wrdata3_re) begin + main_sdram_phaseinjector0_wrdata_storage[31:24] <= builder_minsoc_csrbank2_dfii_pi0_wrdata3_r; + end + if (builder_minsoc_csrbank2_dfii_pi0_wrdata2_re) begin + main_sdram_phaseinjector0_wrdata_storage[23:16] <= builder_minsoc_csrbank2_dfii_pi0_wrdata2_r; + end + if (builder_minsoc_csrbank2_dfii_pi0_wrdata1_re) begin + main_sdram_phaseinjector0_wrdata_storage[15:8] <= builder_minsoc_csrbank2_dfii_pi0_wrdata1_r; + end + if (builder_minsoc_csrbank2_dfii_pi0_wrdata0_re) begin + main_sdram_phaseinjector0_wrdata_storage[7:0] <= builder_minsoc_csrbank2_dfii_pi0_wrdata0_r; + end + main_sdram_phaseinjector0_wrdata_re <= builder_minsoc_csrbank2_dfii_pi0_wrdata0_re; + if (builder_minsoc_csrbank2_dfii_pi1_command0_re) begin + main_sdram_phaseinjector1_command_storage[5:0] <= builder_minsoc_csrbank2_dfii_pi1_command0_r; + end + main_sdram_phaseinjector1_command_re <= builder_minsoc_csrbank2_dfii_pi1_command0_re; + if (builder_minsoc_csrbank2_dfii_pi1_address1_re) begin + main_sdram_phaseinjector1_address_storage[13:8] <= builder_minsoc_csrbank2_dfii_pi1_address1_r; + end + if (builder_minsoc_csrbank2_dfii_pi1_address0_re) begin + main_sdram_phaseinjector1_address_storage[7:0] <= builder_minsoc_csrbank2_dfii_pi1_address0_r; + end + main_sdram_phaseinjector1_address_re <= builder_minsoc_csrbank2_dfii_pi1_address0_re; + if (builder_minsoc_csrbank2_dfii_pi1_baddress0_re) begin + main_sdram_phaseinjector1_baddress_storage[2:0] <= builder_minsoc_csrbank2_dfii_pi1_baddress0_r; + end + main_sdram_phaseinjector1_baddress_re <= builder_minsoc_csrbank2_dfii_pi1_baddress0_re; + if (builder_minsoc_csrbank2_dfii_pi1_wrdata3_re) begin + main_sdram_phaseinjector1_wrdata_storage[31:24] <= builder_minsoc_csrbank2_dfii_pi1_wrdata3_r; + end + if (builder_minsoc_csrbank2_dfii_pi1_wrdata2_re) begin + main_sdram_phaseinjector1_wrdata_storage[23:16] <= builder_minsoc_csrbank2_dfii_pi1_wrdata2_r; + end + if (builder_minsoc_csrbank2_dfii_pi1_wrdata1_re) begin + main_sdram_phaseinjector1_wrdata_storage[15:8] <= builder_minsoc_csrbank2_dfii_pi1_wrdata1_r; + end + if (builder_minsoc_csrbank2_dfii_pi1_wrdata0_re) begin + main_sdram_phaseinjector1_wrdata_storage[7:0] <= builder_minsoc_csrbank2_dfii_pi1_wrdata0_r; + end + main_sdram_phaseinjector1_wrdata_re <= builder_minsoc_csrbank2_dfii_pi1_wrdata0_re; + if (builder_minsoc_csrbank2_dfii_pi2_command0_re) begin + main_sdram_phaseinjector2_command_storage[5:0] <= builder_minsoc_csrbank2_dfii_pi2_command0_r; + end + main_sdram_phaseinjector2_command_re <= builder_minsoc_csrbank2_dfii_pi2_command0_re; + if (builder_minsoc_csrbank2_dfii_pi2_address1_re) begin + main_sdram_phaseinjector2_address_storage[13:8] <= builder_minsoc_csrbank2_dfii_pi2_address1_r; + end + if (builder_minsoc_csrbank2_dfii_pi2_address0_re) begin + main_sdram_phaseinjector2_address_storage[7:0] <= builder_minsoc_csrbank2_dfii_pi2_address0_r; + end + main_sdram_phaseinjector2_address_re <= builder_minsoc_csrbank2_dfii_pi2_address0_re; + if (builder_minsoc_csrbank2_dfii_pi2_baddress0_re) begin + main_sdram_phaseinjector2_baddress_storage[2:0] <= builder_minsoc_csrbank2_dfii_pi2_baddress0_r; + end + main_sdram_phaseinjector2_baddress_re <= builder_minsoc_csrbank2_dfii_pi2_baddress0_re; + if (builder_minsoc_csrbank2_dfii_pi2_wrdata3_re) begin + main_sdram_phaseinjector2_wrdata_storage[31:24] <= builder_minsoc_csrbank2_dfii_pi2_wrdata3_r; + end + if (builder_minsoc_csrbank2_dfii_pi2_wrdata2_re) begin + main_sdram_phaseinjector2_wrdata_storage[23:16] <= builder_minsoc_csrbank2_dfii_pi2_wrdata2_r; + end + if (builder_minsoc_csrbank2_dfii_pi2_wrdata1_re) begin + main_sdram_phaseinjector2_wrdata_storage[15:8] <= builder_minsoc_csrbank2_dfii_pi2_wrdata1_r; + end + if (builder_minsoc_csrbank2_dfii_pi2_wrdata0_re) begin + main_sdram_phaseinjector2_wrdata_storage[7:0] <= builder_minsoc_csrbank2_dfii_pi2_wrdata0_r; + end + main_sdram_phaseinjector2_wrdata_re <= builder_minsoc_csrbank2_dfii_pi2_wrdata0_re; + if (builder_minsoc_csrbank2_dfii_pi3_command0_re) begin + main_sdram_phaseinjector3_command_storage[5:0] <= builder_minsoc_csrbank2_dfii_pi3_command0_r; + end + main_sdram_phaseinjector3_command_re <= builder_minsoc_csrbank2_dfii_pi3_command0_re; + if (builder_minsoc_csrbank2_dfii_pi3_address1_re) begin + main_sdram_phaseinjector3_address_storage[13:8] <= builder_minsoc_csrbank2_dfii_pi3_address1_r; + end + if (builder_minsoc_csrbank2_dfii_pi3_address0_re) begin + main_sdram_phaseinjector3_address_storage[7:0] <= builder_minsoc_csrbank2_dfii_pi3_address0_r; + end + main_sdram_phaseinjector3_address_re <= builder_minsoc_csrbank2_dfii_pi3_address0_re; + if (builder_minsoc_csrbank2_dfii_pi3_baddress0_re) begin + main_sdram_phaseinjector3_baddress_storage[2:0] <= builder_minsoc_csrbank2_dfii_pi3_baddress0_r; + end + main_sdram_phaseinjector3_baddress_re <= builder_minsoc_csrbank2_dfii_pi3_baddress0_re; + if (builder_minsoc_csrbank2_dfii_pi3_wrdata3_re) begin + main_sdram_phaseinjector3_wrdata_storage[31:24] <= builder_minsoc_csrbank2_dfii_pi3_wrdata3_r; + end + if (builder_minsoc_csrbank2_dfii_pi3_wrdata2_re) begin + main_sdram_phaseinjector3_wrdata_storage[23:16] <= builder_minsoc_csrbank2_dfii_pi3_wrdata2_r; + end + if (builder_minsoc_csrbank2_dfii_pi3_wrdata1_re) begin + main_sdram_phaseinjector3_wrdata_storage[15:8] <= builder_minsoc_csrbank2_dfii_pi3_wrdata1_r; + end + if (builder_minsoc_csrbank2_dfii_pi3_wrdata0_re) begin + main_sdram_phaseinjector3_wrdata_storage[7:0] <= builder_minsoc_csrbank2_dfii_pi3_wrdata0_r; + end + main_sdram_phaseinjector3_wrdata_re <= builder_minsoc_csrbank2_dfii_pi3_wrdata0_re; + builder_minsoc_interface3_bank_bus_dat_r <= 1'd0; + if (builder_minsoc_csrbank3_sel) begin + case (builder_minsoc_interface3_bank_bus_adr[4:0]) + 1'd0: begin + builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_load3_w; + end + 1'd1: begin + builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_load2_w; + end + 2'd2: begin + builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_load1_w; + end + 2'd3: begin + builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_load0_w; + end + 3'd4: begin + builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_reload3_w; + end + 3'd5: begin + builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_reload2_w; + end + 3'd6: begin + builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_reload1_w; + end + 3'd7: begin + builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_reload0_w; + end + 4'd8: begin + builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_en0_w; + end + 4'd9: begin + builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_update_value0_w; + end + 4'd10: begin + builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_value3_w; + end + 4'd11: begin + builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_value2_w; + end + 4'd12: begin + builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_value1_w; + end + 4'd13: begin + builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_value0_w; + end + 4'd14: begin + builder_minsoc_interface3_bank_bus_dat_r <= main_timer0_eventmanager_status_w; + end + 4'd15: begin + builder_minsoc_interface3_bank_bus_dat_r <= main_timer0_eventmanager_pending_w; + end + 5'd16: begin + builder_minsoc_interface3_bank_bus_dat_r <= builder_minsoc_csrbank3_ev_enable0_w; + end + endcase + end + if (builder_minsoc_csrbank3_load3_re) begin + main_timer0_load_storage[31:24] <= builder_minsoc_csrbank3_load3_r; + end + if (builder_minsoc_csrbank3_load2_re) begin + main_timer0_load_storage[23:16] <= builder_minsoc_csrbank3_load2_r; + end + if (builder_minsoc_csrbank3_load1_re) begin + main_timer0_load_storage[15:8] <= builder_minsoc_csrbank3_load1_r; + end + if (builder_minsoc_csrbank3_load0_re) begin + main_timer0_load_storage[7:0] <= builder_minsoc_csrbank3_load0_r; + end + main_timer0_load_re <= builder_minsoc_csrbank3_load0_re; + if (builder_minsoc_csrbank3_reload3_re) begin + main_timer0_reload_storage[31:24] <= builder_minsoc_csrbank3_reload3_r; + end + if (builder_minsoc_csrbank3_reload2_re) begin + main_timer0_reload_storage[23:16] <= builder_minsoc_csrbank3_reload2_r; + end + if (builder_minsoc_csrbank3_reload1_re) begin + main_timer0_reload_storage[15:8] <= builder_minsoc_csrbank3_reload1_r; + end + if (builder_minsoc_csrbank3_reload0_re) begin + main_timer0_reload_storage[7:0] <= builder_minsoc_csrbank3_reload0_r; + end + main_timer0_reload_re <= builder_minsoc_csrbank3_reload0_re; + if (builder_minsoc_csrbank3_en0_re) begin + main_timer0_en_storage <= builder_minsoc_csrbank3_en0_r; + end + main_timer0_en_re <= builder_minsoc_csrbank3_en0_re; + if (builder_minsoc_csrbank3_update_value0_re) begin + main_timer0_update_value_storage <= builder_minsoc_csrbank3_update_value0_r; + end + main_timer0_update_value_re <= builder_minsoc_csrbank3_update_value0_re; + if (builder_minsoc_csrbank3_ev_enable0_re) begin + main_timer0_eventmanager_storage <= builder_minsoc_csrbank3_ev_enable0_r; + end + main_timer0_eventmanager_re <= builder_minsoc_csrbank3_ev_enable0_re; + builder_minsoc_interface4_bank_bus_dat_r <= 1'd0; + if (builder_minsoc_csrbank4_sel) begin + case (builder_minsoc_interface4_bank_bus_adr[2:0]) + 1'd0: begin + builder_minsoc_interface4_bank_bus_dat_r <= main_uart_rxtx_w; + end + 1'd1: begin + builder_minsoc_interface4_bank_bus_dat_r <= builder_minsoc_csrbank4_txfull_w; + end + 2'd2: begin + builder_minsoc_interface4_bank_bus_dat_r <= builder_minsoc_csrbank4_rxempty_w; + end + 2'd3: begin + builder_minsoc_interface4_bank_bus_dat_r <= main_uart_eventmanager_status_w; + end + 3'd4: begin + builder_minsoc_interface4_bank_bus_dat_r <= main_uart_eventmanager_pending_w; + end + 3'd5: begin + builder_minsoc_interface4_bank_bus_dat_r <= builder_minsoc_csrbank4_ev_enable0_w; + end + endcase + end + if (builder_minsoc_csrbank4_ev_enable0_re) begin + main_uart_eventmanager_storage[1:0] <= builder_minsoc_csrbank4_ev_enable0_r; + end + main_uart_eventmanager_re <= builder_minsoc_csrbank4_ev_enable0_re; + builder_minsoc_interface5_bank_bus_dat_r <= 1'd0; + if (builder_minsoc_csrbank5_sel) begin + case (builder_minsoc_interface5_bank_bus_adr[1:0]) + 1'd0: begin + builder_minsoc_interface5_bank_bus_dat_r <= builder_minsoc_csrbank5_tuning_word3_w; + end + 1'd1: begin + builder_minsoc_interface5_bank_bus_dat_r <= builder_minsoc_csrbank5_tuning_word2_w; + end + 2'd2: begin + builder_minsoc_interface5_bank_bus_dat_r <= builder_minsoc_csrbank5_tuning_word1_w; + end + 2'd3: begin + builder_minsoc_interface5_bank_bus_dat_r <= builder_minsoc_csrbank5_tuning_word0_w; + end + endcase + end + if (builder_minsoc_csrbank5_tuning_word3_re) begin + main_uart_phy_storage[31:24] <= builder_minsoc_csrbank5_tuning_word3_r; + end + if (builder_minsoc_csrbank5_tuning_word2_re) begin + main_uart_phy_storage[23:16] <= builder_minsoc_csrbank5_tuning_word2_r; + end + if (builder_minsoc_csrbank5_tuning_word1_re) begin + main_uart_phy_storage[15:8] <= builder_minsoc_csrbank5_tuning_word1_r; + end + if (builder_minsoc_csrbank5_tuning_word0_re) begin + main_uart_phy_storage[7:0] <= builder_minsoc_csrbank5_tuning_word0_r; + end + main_uart_phy_re <= builder_minsoc_csrbank5_tuning_word0_re; + if (sys_rst) begin + main_ctrl_storage <= 32'd305419896; + main_ctrl_re <= 1'd0; + main_ctrl_bus_errors <= 32'd0; + main_rom_bus_ack <= 1'd0; + main_sram_bus_ack <= 1'd0; + serial_tx <= 1'd1; + main_uart_phy_storage <= 32'd9895604; + main_uart_phy_re <= 1'd0; + main_uart_phy_sink_ready <= 1'd0; + main_uart_phy_uart_clk_txen <= 1'd0; + main_uart_phy_phase_accumulator_tx <= 32'd0; + main_uart_phy_tx_reg <= 8'd0; + main_uart_phy_tx_bitcount <= 4'd0; + main_uart_phy_tx_busy <= 1'd0; + main_uart_phy_source_valid <= 1'd0; + main_uart_phy_source_payload_data <= 8'd0; + main_uart_phy_uart_clk_rxen <= 1'd0; + main_uart_phy_phase_accumulator_rx <= 32'd0; + main_uart_phy_rx_r <= 1'd0; + main_uart_phy_rx_reg <= 8'd0; + main_uart_phy_rx_bitcount <= 4'd0; + main_uart_phy_rx_busy <= 1'd0; + main_uart_tx_pending <= 1'd0; + main_uart_tx_old_trigger <= 1'd0; + main_uart_rx_pending <= 1'd0; + main_uart_rx_old_trigger <= 1'd0; + main_uart_eventmanager_storage <= 2'd0; + main_uart_eventmanager_re <= 1'd0; + main_uart_tx_fifo_readable <= 1'd0; + main_uart_tx_fifo_level0 <= 5'd0; + main_uart_tx_fifo_produce <= 4'd0; + main_uart_tx_fifo_consume <= 4'd0; + main_uart_rx_fifo_readable <= 1'd0; + main_uart_rx_fifo_level0 <= 5'd0; + main_uart_rx_fifo_produce <= 4'd0; + main_uart_rx_fifo_consume <= 4'd0; + main_timer0_load_storage <= 32'd0; + main_timer0_load_re <= 1'd0; + main_timer0_reload_storage <= 32'd0; + main_timer0_reload_re <= 1'd0; + main_timer0_en_storage <= 1'd0; + main_timer0_en_re <= 1'd0; + main_timer0_update_value_storage <= 1'd0; + main_timer0_update_value_re <= 1'd0; + main_timer0_value_status <= 32'd0; + main_timer0_zero_pending <= 1'd0; + main_timer0_zero_old_trigger <= 1'd0; + main_timer0_eventmanager_storage <= 1'd0; + main_timer0_eventmanager_re <= 1'd0; + main_timer0_value <= 32'd0; + main_a7ddrphy_half_sys8x_taps_storage <= 5'd16; + main_a7ddrphy_half_sys8x_taps_re <= 1'd0; + main_a7ddrphy_dly_sel_storage <= 2'd0; + main_a7ddrphy_dly_sel_re <= 1'd0; + main_a7ddrphy_dfi_p0_rddata_valid <= 1'd0; + main_a7ddrphy_dfi_p1_rddata_valid <= 1'd0; + main_a7ddrphy_dfi_p2_rddata_valid <= 1'd0; + main_a7ddrphy_dfi_p3_rddata_valid <= 1'd0; + main_a7ddrphy_oe_dqs <= 1'd0; + main_a7ddrphy_oe_dq <= 1'd0; + main_a7ddrphy_bitslip0_o <= 8'd0; + main_a7ddrphy_bitslip0_value <= 3'd0; + main_a7ddrphy_bitslip0_r <= 16'd0; + main_a7ddrphy_bitslip1_o <= 8'd0; + main_a7ddrphy_bitslip1_value <= 3'd0; + main_a7ddrphy_bitslip1_r <= 16'd0; + main_a7ddrphy_bitslip2_o <= 8'd0; + main_a7ddrphy_bitslip2_value <= 3'd0; + main_a7ddrphy_bitslip2_r <= 16'd0; + main_a7ddrphy_bitslip3_o <= 8'd0; + main_a7ddrphy_bitslip3_value <= 3'd0; + main_a7ddrphy_bitslip3_r <= 16'd0; + main_a7ddrphy_bitslip4_o <= 8'd0; + main_a7ddrphy_bitslip4_value <= 3'd0; + main_a7ddrphy_bitslip4_r <= 16'd0; + main_a7ddrphy_bitslip5_o <= 8'd0; + main_a7ddrphy_bitslip5_value <= 3'd0; + main_a7ddrphy_bitslip5_r <= 16'd0; + main_a7ddrphy_bitslip6_o <= 8'd0; + main_a7ddrphy_bitslip6_value <= 3'd0; + main_a7ddrphy_bitslip6_r <= 16'd0; + main_a7ddrphy_bitslip7_o <= 8'd0; + main_a7ddrphy_bitslip7_value <= 3'd0; + main_a7ddrphy_bitslip7_r <= 16'd0; + main_a7ddrphy_bitslip8_o <= 8'd0; + main_a7ddrphy_bitslip8_value <= 3'd0; + main_a7ddrphy_bitslip8_r <= 16'd0; + main_a7ddrphy_bitslip9_o <= 8'd0; + main_a7ddrphy_bitslip9_value <= 3'd0; + main_a7ddrphy_bitslip9_r <= 16'd0; + main_a7ddrphy_bitslip10_o <= 8'd0; + main_a7ddrphy_bitslip10_value <= 3'd0; + main_a7ddrphy_bitslip10_r <= 16'd0; + main_a7ddrphy_bitslip11_o <= 8'd0; + main_a7ddrphy_bitslip11_value <= 3'd0; + main_a7ddrphy_bitslip11_r <= 16'd0; + main_a7ddrphy_bitslip12_o <= 8'd0; + main_a7ddrphy_bitslip12_value <= 3'd0; + main_a7ddrphy_bitslip12_r <= 16'd0; + main_a7ddrphy_bitslip13_o <= 8'd0; + main_a7ddrphy_bitslip13_value <= 3'd0; + main_a7ddrphy_bitslip13_r <= 16'd0; + main_a7ddrphy_bitslip14_o <= 8'd0; + main_a7ddrphy_bitslip14_value <= 3'd0; + main_a7ddrphy_bitslip14_r <= 16'd0; + main_a7ddrphy_bitslip15_o <= 8'd0; + main_a7ddrphy_bitslip15_value <= 3'd0; + main_a7ddrphy_bitslip15_r <= 16'd0; + main_a7ddrphy_n_rddata_en0 <= 1'd0; + main_a7ddrphy_n_rddata_en1 <= 1'd0; + main_a7ddrphy_n_rddata_en2 <= 1'd0; + main_a7ddrphy_n_rddata_en3 <= 1'd0; + main_a7ddrphy_n_rddata_en4 <= 1'd0; + main_a7ddrphy_n_rddata_en5 <= 1'd0; + main_a7ddrphy_n_rddata_en6 <= 1'd0; + main_a7ddrphy_n_rddata_en7 <= 1'd0; + main_a7ddrphy_last_wrdata_en <= 4'd0; + main_sdram_storage <= 4'd0; + main_sdram_re <= 1'd0; + main_sdram_phaseinjector0_command_storage <= 6'd0; + main_sdram_phaseinjector0_command_re <= 1'd0; + main_sdram_phaseinjector0_address_storage <= 14'd0; + main_sdram_phaseinjector0_address_re <= 1'd0; + main_sdram_phaseinjector0_baddress_storage <= 3'd0; + main_sdram_phaseinjector0_baddress_re <= 1'd0; + main_sdram_phaseinjector0_wrdata_storage <= 32'd0; + main_sdram_phaseinjector0_wrdata_re <= 1'd0; + main_sdram_phaseinjector0_status <= 32'd0; + main_sdram_phaseinjector1_command_storage <= 6'd0; + main_sdram_phaseinjector1_command_re <= 1'd0; + main_sdram_phaseinjector1_address_storage <= 14'd0; + main_sdram_phaseinjector1_address_re <= 1'd0; + main_sdram_phaseinjector1_baddress_storage <= 3'd0; + main_sdram_phaseinjector1_baddress_re <= 1'd0; + main_sdram_phaseinjector1_wrdata_storage <= 32'd0; + main_sdram_phaseinjector1_wrdata_re <= 1'd0; + main_sdram_phaseinjector1_status <= 32'd0; + main_sdram_phaseinjector2_command_storage <= 6'd0; + main_sdram_phaseinjector2_command_re <= 1'd0; + main_sdram_phaseinjector2_address_storage <= 14'd0; + main_sdram_phaseinjector2_address_re <= 1'd0; + main_sdram_phaseinjector2_baddress_storage <= 3'd0; + main_sdram_phaseinjector2_baddress_re <= 1'd0; + main_sdram_phaseinjector2_wrdata_storage <= 32'd0; + main_sdram_phaseinjector2_wrdata_re <= 1'd0; + main_sdram_phaseinjector2_status <= 32'd0; + main_sdram_phaseinjector3_command_storage <= 6'd0; + main_sdram_phaseinjector3_command_re <= 1'd0; + main_sdram_phaseinjector3_address_storage <= 14'd0; + main_sdram_phaseinjector3_address_re <= 1'd0; + main_sdram_phaseinjector3_baddress_storage <= 3'd0; + main_sdram_phaseinjector3_baddress_re <= 1'd0; + main_sdram_phaseinjector3_wrdata_storage <= 32'd0; + main_sdram_phaseinjector3_wrdata_re <= 1'd0; + main_sdram_phaseinjector3_status <= 32'd0; + main_sdram_dfi_p0_address <= 14'd0; + main_sdram_dfi_p0_bank <= 3'd0; + main_sdram_dfi_p0_cas_n <= 1'd1; + main_sdram_dfi_p0_cs_n <= 1'd1; + main_sdram_dfi_p0_ras_n <= 1'd1; + main_sdram_dfi_p0_we_n <= 1'd1; + main_sdram_dfi_p0_wrdata_en <= 1'd0; + main_sdram_dfi_p0_rddata_en <= 1'd0; + main_sdram_dfi_p1_address <= 14'd0; + main_sdram_dfi_p1_bank <= 3'd0; + main_sdram_dfi_p1_cas_n <= 1'd1; + main_sdram_dfi_p1_cs_n <= 1'd1; + main_sdram_dfi_p1_ras_n <= 1'd1; + main_sdram_dfi_p1_we_n <= 1'd1; + main_sdram_dfi_p1_wrdata_en <= 1'd0; + main_sdram_dfi_p1_rddata_en <= 1'd0; + main_sdram_dfi_p2_address <= 14'd0; + main_sdram_dfi_p2_bank <= 3'd0; + main_sdram_dfi_p2_cas_n <= 1'd1; + main_sdram_dfi_p2_cs_n <= 1'd1; + main_sdram_dfi_p2_ras_n <= 1'd1; + main_sdram_dfi_p2_we_n <= 1'd1; + main_sdram_dfi_p2_wrdata_en <= 1'd0; + main_sdram_dfi_p2_rddata_en <= 1'd0; + main_sdram_dfi_p3_address <= 14'd0; + main_sdram_dfi_p3_bank <= 3'd0; + main_sdram_dfi_p3_cas_n <= 1'd1; + main_sdram_dfi_p3_cs_n <= 1'd1; + main_sdram_dfi_p3_ras_n <= 1'd1; + main_sdram_dfi_p3_we_n <= 1'd1; + main_sdram_dfi_p3_wrdata_en <= 1'd0; + main_sdram_dfi_p3_rddata_en <= 1'd0; + main_sdram_cmd_payload_a <= 14'd0; + main_sdram_cmd_payload_ba <= 3'd0; + main_sdram_cmd_payload_cas <= 1'd0; + main_sdram_cmd_payload_ras <= 1'd0; + main_sdram_cmd_payload_we <= 1'd0; + main_sdram_timer_count1 <= 9'd390; + main_sdram_postponer_req_o <= 1'd0; + main_sdram_postponer_count <= 1'd0; + main_sdram_sequencer_done1 <= 1'd0; + main_sdram_sequencer_counter <= 6'd0; + main_sdram_sequencer_count <= 1'd0; + main_sdram_zqcs_timer_count1 <= 26'd49999999; + main_sdram_zqcs_executer_done <= 1'd0; + main_sdram_zqcs_executer_counter <= 5'd0; + main_sdram_bankmachine0_cmd_buffer_lookahead_level <= 4'd0; + main_sdram_bankmachine0_cmd_buffer_lookahead_produce <= 3'd0; + main_sdram_bankmachine0_cmd_buffer_lookahead_consume <= 3'd0; + main_sdram_bankmachine0_cmd_buffer_source_payload_we <= 1'd0; + main_sdram_bankmachine0_cmd_buffer_source_payload_addr <= 21'd0; + main_sdram_bankmachine0_cmd_buffer_valid_n <= 1'd0; + main_sdram_bankmachine0_cmd_buffer_first_n <= 1'd0; + main_sdram_bankmachine0_cmd_buffer_last_n <= 1'd0; + main_sdram_bankmachine0_row <= 14'd0; + main_sdram_bankmachine0_row_opened <= 1'd0; + main_sdram_bankmachine0_twtpcon_ready <= 1'd1; + main_sdram_bankmachine0_twtpcon_count <= 3'd0; + main_sdram_bankmachine0_trccon_ready <= 1'd1; + main_sdram_bankmachine0_trccon_count <= 2'd0; + main_sdram_bankmachine0_trascon_ready <= 1'd1; + main_sdram_bankmachine0_trascon_count <= 2'd0; + main_sdram_bankmachine1_cmd_buffer_lookahead_level <= 4'd0; + main_sdram_bankmachine1_cmd_buffer_lookahead_produce <= 3'd0; + main_sdram_bankmachine1_cmd_buffer_lookahead_consume <= 3'd0; + main_sdram_bankmachine1_cmd_buffer_source_payload_we <= 1'd0; + main_sdram_bankmachine1_cmd_buffer_source_payload_addr <= 21'd0; + main_sdram_bankmachine1_cmd_buffer_valid_n <= 1'd0; + main_sdram_bankmachine1_cmd_buffer_first_n <= 1'd0; + main_sdram_bankmachine1_cmd_buffer_last_n <= 1'd0; + main_sdram_bankmachine1_row <= 14'd0; + main_sdram_bankmachine1_row_opened <= 1'd0; + main_sdram_bankmachine1_twtpcon_ready <= 1'd1; + main_sdram_bankmachine1_twtpcon_count <= 3'd0; + main_sdram_bankmachine1_trccon_ready <= 1'd1; + main_sdram_bankmachine1_trccon_count <= 2'd0; + main_sdram_bankmachine1_trascon_ready <= 1'd1; + main_sdram_bankmachine1_trascon_count <= 2'd0; + main_sdram_bankmachine2_cmd_buffer_lookahead_level <= 4'd0; + main_sdram_bankmachine2_cmd_buffer_lookahead_produce <= 3'd0; + main_sdram_bankmachine2_cmd_buffer_lookahead_consume <= 3'd0; + main_sdram_bankmachine2_cmd_buffer_source_payload_we <= 1'd0; + main_sdram_bankmachine2_cmd_buffer_source_payload_addr <= 21'd0; + main_sdram_bankmachine2_cmd_buffer_valid_n <= 1'd0; + main_sdram_bankmachine2_cmd_buffer_first_n <= 1'd0; + main_sdram_bankmachine2_cmd_buffer_last_n <= 1'd0; + main_sdram_bankmachine2_row <= 14'd0; + main_sdram_bankmachine2_row_opened <= 1'd0; + main_sdram_bankmachine2_twtpcon_ready <= 1'd1; + main_sdram_bankmachine2_twtpcon_count <= 3'd0; + main_sdram_bankmachine2_trccon_ready <= 1'd1; + main_sdram_bankmachine2_trccon_count <= 2'd0; + main_sdram_bankmachine2_trascon_ready <= 1'd1; + main_sdram_bankmachine2_trascon_count <= 2'd0; + main_sdram_bankmachine3_cmd_buffer_lookahead_level <= 4'd0; + main_sdram_bankmachine3_cmd_buffer_lookahead_produce <= 3'd0; + main_sdram_bankmachine3_cmd_buffer_lookahead_consume <= 3'd0; + main_sdram_bankmachine3_cmd_buffer_source_payload_we <= 1'd0; + main_sdram_bankmachine3_cmd_buffer_source_payload_addr <= 21'd0; + main_sdram_bankmachine3_cmd_buffer_valid_n <= 1'd0; + main_sdram_bankmachine3_cmd_buffer_first_n <= 1'd0; + main_sdram_bankmachine3_cmd_buffer_last_n <= 1'd0; + main_sdram_bankmachine3_row <= 14'd0; + main_sdram_bankmachine3_row_opened <= 1'd0; + main_sdram_bankmachine3_twtpcon_ready <= 1'd1; + main_sdram_bankmachine3_twtpcon_count <= 3'd0; + main_sdram_bankmachine3_trccon_ready <= 1'd1; + main_sdram_bankmachine3_trccon_count <= 2'd0; + main_sdram_bankmachine3_trascon_ready <= 1'd1; + main_sdram_bankmachine3_trascon_count <= 2'd0; + main_sdram_bankmachine4_cmd_buffer_lookahead_level <= 4'd0; + main_sdram_bankmachine4_cmd_buffer_lookahead_produce <= 3'd0; + main_sdram_bankmachine4_cmd_buffer_lookahead_consume <= 3'd0; + main_sdram_bankmachine4_cmd_buffer_source_payload_we <= 1'd0; + main_sdram_bankmachine4_cmd_buffer_source_payload_addr <= 21'd0; + main_sdram_bankmachine4_cmd_buffer_valid_n <= 1'd0; + main_sdram_bankmachine4_cmd_buffer_first_n <= 1'd0; + main_sdram_bankmachine4_cmd_buffer_last_n <= 1'd0; + main_sdram_bankmachine4_row <= 14'd0; + main_sdram_bankmachine4_row_opened <= 1'd0; + main_sdram_bankmachine4_twtpcon_ready <= 1'd1; + main_sdram_bankmachine4_twtpcon_count <= 3'd0; + main_sdram_bankmachine4_trccon_ready <= 1'd1; + main_sdram_bankmachine4_trccon_count <= 2'd0; + main_sdram_bankmachine4_trascon_ready <= 1'd1; + main_sdram_bankmachine4_trascon_count <= 2'd0; + main_sdram_bankmachine5_cmd_buffer_lookahead_level <= 4'd0; + main_sdram_bankmachine5_cmd_buffer_lookahead_produce <= 3'd0; + main_sdram_bankmachine5_cmd_buffer_lookahead_consume <= 3'd0; + main_sdram_bankmachine5_cmd_buffer_source_payload_we <= 1'd0; + main_sdram_bankmachine5_cmd_buffer_source_payload_addr <= 21'd0; + main_sdram_bankmachine5_cmd_buffer_valid_n <= 1'd0; + main_sdram_bankmachine5_cmd_buffer_first_n <= 1'd0; + main_sdram_bankmachine5_cmd_buffer_last_n <= 1'd0; + main_sdram_bankmachine5_row <= 14'd0; + main_sdram_bankmachine5_row_opened <= 1'd0; + main_sdram_bankmachine5_twtpcon_ready <= 1'd1; + main_sdram_bankmachine5_twtpcon_count <= 3'd0; + main_sdram_bankmachine5_trccon_ready <= 1'd1; + main_sdram_bankmachine5_trccon_count <= 2'd0; + main_sdram_bankmachine5_trascon_ready <= 1'd1; + main_sdram_bankmachine5_trascon_count <= 2'd0; + main_sdram_bankmachine6_cmd_buffer_lookahead_level <= 4'd0; + main_sdram_bankmachine6_cmd_buffer_lookahead_produce <= 3'd0; + main_sdram_bankmachine6_cmd_buffer_lookahead_consume <= 3'd0; + main_sdram_bankmachine6_cmd_buffer_source_payload_we <= 1'd0; + main_sdram_bankmachine6_cmd_buffer_source_payload_addr <= 21'd0; + main_sdram_bankmachine6_cmd_buffer_valid_n <= 1'd0; + main_sdram_bankmachine6_cmd_buffer_first_n <= 1'd0; + main_sdram_bankmachine6_cmd_buffer_last_n <= 1'd0; + main_sdram_bankmachine6_row <= 14'd0; + main_sdram_bankmachine6_row_opened <= 1'd0; + main_sdram_bankmachine6_twtpcon_ready <= 1'd1; + main_sdram_bankmachine6_twtpcon_count <= 3'd0; + main_sdram_bankmachine6_trccon_ready <= 1'd1; + main_sdram_bankmachine6_trccon_count <= 2'd0; + main_sdram_bankmachine6_trascon_ready <= 1'd1; + main_sdram_bankmachine6_trascon_count <= 2'd0; + main_sdram_bankmachine7_cmd_buffer_lookahead_level <= 4'd0; + main_sdram_bankmachine7_cmd_buffer_lookahead_produce <= 3'd0; + main_sdram_bankmachine7_cmd_buffer_lookahead_consume <= 3'd0; + main_sdram_bankmachine7_cmd_buffer_source_payload_we <= 1'd0; + main_sdram_bankmachine7_cmd_buffer_source_payload_addr <= 21'd0; + main_sdram_bankmachine7_cmd_buffer_valid_n <= 1'd0; + main_sdram_bankmachine7_cmd_buffer_first_n <= 1'd0; + main_sdram_bankmachine7_cmd_buffer_last_n <= 1'd0; + main_sdram_bankmachine7_row <= 14'd0; + main_sdram_bankmachine7_row_opened <= 1'd0; + main_sdram_bankmachine7_twtpcon_ready <= 1'd1; + main_sdram_bankmachine7_twtpcon_count <= 3'd0; + main_sdram_bankmachine7_trccon_ready <= 1'd1; + main_sdram_bankmachine7_trccon_count <= 2'd0; + main_sdram_bankmachine7_trascon_ready <= 1'd1; + main_sdram_bankmachine7_trascon_count <= 2'd0; + main_sdram_choose_cmd_grant <= 3'd0; + main_sdram_choose_req_grant <= 3'd0; + main_sdram_trrdcon_ready <= 1'd1; + main_sdram_trrdcon_count <= 1'd0; + main_sdram_tfawcon_ready <= 1'd1; + main_sdram_tfawcon_window <= 3'd0; + main_sdram_tccdcon_ready <= 1'd1; + main_sdram_tccdcon_count <= 1'd0; + main_sdram_twtrcon_ready <= 1'd1; + main_sdram_twtrcon_count <= 3'd0; + main_sdram_time0 <= 5'd0; + main_sdram_time1 <= 4'd0; + main_adr_offset_r <= 2'd0; + builder_wb2csr_state <= 1'd0; + builder_refresher_state <= 2'd0; + builder_bankmachine0_state <= 3'd0; + builder_bankmachine1_state <= 3'd0; + builder_bankmachine2_state <= 3'd0; + builder_bankmachine3_state <= 3'd0; + builder_bankmachine4_state <= 3'd0; + builder_bankmachine5_state <= 3'd0; + builder_bankmachine6_state <= 3'd0; + builder_bankmachine7_state <= 3'd0; + builder_multiplexer_state <= 4'd0; + builder_rbank <= 3'd0; + builder_wbank <= 3'd0; + builder_new_master_wdata_ready0 <= 1'd0; + builder_new_master_wdata_ready1 <= 1'd0; + builder_new_master_wdata_ready2 <= 1'd0; + builder_new_master_rdata_valid0 <= 1'd0; + builder_new_master_rdata_valid1 <= 1'd0; + builder_new_master_rdata_valid2 <= 1'd0; + builder_new_master_rdata_valid3 <= 1'd0; + builder_new_master_rdata_valid4 <= 1'd0; + builder_new_master_rdata_valid5 <= 1'd0; + builder_new_master_rdata_valid6 <= 1'd0; + builder_new_master_rdata_valid7 <= 1'd0; + builder_new_master_rdata_valid8 <= 1'd0; + builder_new_master_rdata_valid9 <= 1'd0; + builder_fullmemorywe_state <= 3'd0; + builder_litedramwishbone2native_state <= 2'd0; + builder_minsoc_grant <= 1'd0; + builder_minsoc_slave_sel_r <= 4'd0; + builder_minsoc_count <= 20'd1000000; + builder_minsoc_interface0_bank_bus_dat_r <= 8'd0; + builder_minsoc_interface1_bank_bus_dat_r <= 8'd0; + builder_minsoc_interface2_bank_bus_dat_r <= 8'd0; + builder_minsoc_interface3_bank_bus_dat_r <= 8'd0; + builder_minsoc_interface4_bank_bus_dat_r <= 8'd0; + builder_minsoc_interface5_bank_bus_dat_r <= 8'd0; + end + builder_regs0 <= serial_rx; + builder_regs1 <= builder_regs0; +end + +reg [31:0] mem[0:8191]; +reg [31:0] memdat; +always @(posedge sys_clk) begin + memdat <= mem[main_rom_adr]; +end + +assign main_rom_dat_r = memdat; + +initial begin + $readmemh("mem.init", mem); +end + +reg [31:0] mem_1[0:8191]; +reg [12:0] memadr; +always @(posedge sys_clk) begin + if (main_sram_we[0]) + mem_1[main_sram_adr][7:0] <= main_sram_dat_w[7:0]; + if (main_sram_we[1]) + mem_1[main_sram_adr][15:8] <= main_sram_dat_w[15:8]; + if (main_sram_we[2]) + mem_1[main_sram_adr][23:16] <= main_sram_dat_w[23:16]; + if (main_sram_we[3]) + mem_1[main_sram_adr][31:24] <= main_sram_dat_w[31:24]; + memadr <= main_sram_adr; +end + +assign main_sram_dat_r = mem_1[memadr]; + +initial begin + $readmemh("mem_1.init", mem_1); +end + +reg [9:0] storage[0:15]; +reg [9:0] memdat_1; +reg [9:0] memdat_2; +always @(posedge sys_clk) begin + if (main_uart_tx_fifo_wrport_we) + storage[main_uart_tx_fifo_wrport_adr] <= main_uart_tx_fifo_wrport_dat_w; + memdat_1 <= storage[main_uart_tx_fifo_wrport_adr]; +end + +always @(posedge sys_clk) begin + if (main_uart_tx_fifo_rdport_re) + memdat_2 <= storage[main_uart_tx_fifo_rdport_adr]; +end + +assign main_uart_tx_fifo_wrport_dat_r = memdat_1; +assign main_uart_tx_fifo_rdport_dat_r = memdat_2; + +reg [9:0] storage_1[0:15]; +reg [9:0] memdat_3; +reg [9:0] memdat_4; +always @(posedge sys_clk) begin + if (main_uart_rx_fifo_wrport_we) + storage_1[main_uart_rx_fifo_wrport_adr] <= main_uart_rx_fifo_wrport_dat_w; + memdat_3 <= storage_1[main_uart_rx_fifo_wrport_adr]; +end + +always @(posedge sys_clk) begin + if (main_uart_rx_fifo_rdport_re) + memdat_4 <= storage_1[main_uart_rx_fifo_rdport_adr]; +end + +assign main_uart_rx_fifo_wrport_dat_r = memdat_3; +assign main_uart_rx_fifo_rdport_dat_r = memdat_4; + +BUFG BUFG( + .I(clk100), + .O(main_pll_clkin) +); + +BUFG BUFG_1( + .I(main_clkout0), + .O(main_clkout_buf0) +); + +BUFG BUFG_2( + .I(main_clkout1), + .O(main_clkout_buf1) +); + +BUFG BUFG_3( + .I(main_clkout2), + .O(main_clkout_buf2) +); + +BUFG BUFG_4( + .I(main_clkout3), + .O(main_clkout_buf3) +); + +IDELAYCTRL IDELAYCTRL( + .REFCLK(clk200_clk), + .RST(main_ic_reset) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(1'd0), + .D2(1'd1), + .D3(1'd0), + .D4(1'd1), + .D5(1'd0), + .D6(1'd1), + .D7(1'd0), + .D8(1'd1), + .OCE(1'd1), + .RST(sys_rst), + .OQ(main_a7ddrphy_sd_clk_se_nodelay) +); + +OBUFDS OBUFDS( + .I(main_a7ddrphy_sd_clk_se_nodelay), + .O(ddram_clk_p), + .OB(ddram_clk_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_1 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_address[0]), + .D2(main_a7ddrphy_dfi_p0_address[0]), + .D3(main_a7ddrphy_dfi_p1_address[0]), + .D4(main_a7ddrphy_dfi_p1_address[0]), + .D5(main_a7ddrphy_dfi_p2_address[0]), + .D6(main_a7ddrphy_dfi_p2_address[0]), + .D7(main_a7ddrphy_dfi_p3_address[0]), + .D8(main_a7ddrphy_dfi_p3_address[0]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[0]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_2 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_address[1]), + .D2(main_a7ddrphy_dfi_p0_address[1]), + .D3(main_a7ddrphy_dfi_p1_address[1]), + .D4(main_a7ddrphy_dfi_p1_address[1]), + .D5(main_a7ddrphy_dfi_p2_address[1]), + .D6(main_a7ddrphy_dfi_p2_address[1]), + .D7(main_a7ddrphy_dfi_p3_address[1]), + .D8(main_a7ddrphy_dfi_p3_address[1]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[1]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_3 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_address[2]), + .D2(main_a7ddrphy_dfi_p0_address[2]), + .D3(main_a7ddrphy_dfi_p1_address[2]), + .D4(main_a7ddrphy_dfi_p1_address[2]), + .D5(main_a7ddrphy_dfi_p2_address[2]), + .D6(main_a7ddrphy_dfi_p2_address[2]), + .D7(main_a7ddrphy_dfi_p3_address[2]), + .D8(main_a7ddrphy_dfi_p3_address[2]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[2]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_4 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_address[3]), + .D2(main_a7ddrphy_dfi_p0_address[3]), + .D3(main_a7ddrphy_dfi_p1_address[3]), + .D4(main_a7ddrphy_dfi_p1_address[3]), + .D5(main_a7ddrphy_dfi_p2_address[3]), + .D6(main_a7ddrphy_dfi_p2_address[3]), + .D7(main_a7ddrphy_dfi_p3_address[3]), + .D8(main_a7ddrphy_dfi_p3_address[3]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[3]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_5 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_address[4]), + .D2(main_a7ddrphy_dfi_p0_address[4]), + .D3(main_a7ddrphy_dfi_p1_address[4]), + .D4(main_a7ddrphy_dfi_p1_address[4]), + .D5(main_a7ddrphy_dfi_p2_address[4]), + .D6(main_a7ddrphy_dfi_p2_address[4]), + .D7(main_a7ddrphy_dfi_p3_address[4]), + .D8(main_a7ddrphy_dfi_p3_address[4]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[4]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_6 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_address[5]), + .D2(main_a7ddrphy_dfi_p0_address[5]), + .D3(main_a7ddrphy_dfi_p1_address[5]), + .D4(main_a7ddrphy_dfi_p1_address[5]), + .D5(main_a7ddrphy_dfi_p2_address[5]), + .D6(main_a7ddrphy_dfi_p2_address[5]), + .D7(main_a7ddrphy_dfi_p3_address[5]), + .D8(main_a7ddrphy_dfi_p3_address[5]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[5]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_7 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_address[6]), + .D2(main_a7ddrphy_dfi_p0_address[6]), + .D3(main_a7ddrphy_dfi_p1_address[6]), + .D4(main_a7ddrphy_dfi_p1_address[6]), + .D5(main_a7ddrphy_dfi_p2_address[6]), + .D6(main_a7ddrphy_dfi_p2_address[6]), + .D7(main_a7ddrphy_dfi_p3_address[6]), + .D8(main_a7ddrphy_dfi_p3_address[6]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[6]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_8 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_address[7]), + .D2(main_a7ddrphy_dfi_p0_address[7]), + .D3(main_a7ddrphy_dfi_p1_address[7]), + .D4(main_a7ddrphy_dfi_p1_address[7]), + .D5(main_a7ddrphy_dfi_p2_address[7]), + .D6(main_a7ddrphy_dfi_p2_address[7]), + .D7(main_a7ddrphy_dfi_p3_address[7]), + .D8(main_a7ddrphy_dfi_p3_address[7]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[7]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_9 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_address[8]), + .D2(main_a7ddrphy_dfi_p0_address[8]), + .D3(main_a7ddrphy_dfi_p1_address[8]), + .D4(main_a7ddrphy_dfi_p1_address[8]), + .D5(main_a7ddrphy_dfi_p2_address[8]), + .D6(main_a7ddrphy_dfi_p2_address[8]), + .D7(main_a7ddrphy_dfi_p3_address[8]), + .D8(main_a7ddrphy_dfi_p3_address[8]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[8]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_10 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_address[9]), + .D2(main_a7ddrphy_dfi_p0_address[9]), + .D3(main_a7ddrphy_dfi_p1_address[9]), + .D4(main_a7ddrphy_dfi_p1_address[9]), + .D5(main_a7ddrphy_dfi_p2_address[9]), + .D6(main_a7ddrphy_dfi_p2_address[9]), + .D7(main_a7ddrphy_dfi_p3_address[9]), + .D8(main_a7ddrphy_dfi_p3_address[9]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[9]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_11 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_address[10]), + .D2(main_a7ddrphy_dfi_p0_address[10]), + .D3(main_a7ddrphy_dfi_p1_address[10]), + .D4(main_a7ddrphy_dfi_p1_address[10]), + .D5(main_a7ddrphy_dfi_p2_address[10]), + .D6(main_a7ddrphy_dfi_p2_address[10]), + .D7(main_a7ddrphy_dfi_p3_address[10]), + .D8(main_a7ddrphy_dfi_p3_address[10]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[10]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_12 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_address[11]), + .D2(main_a7ddrphy_dfi_p0_address[11]), + .D3(main_a7ddrphy_dfi_p1_address[11]), + .D4(main_a7ddrphy_dfi_p1_address[11]), + .D5(main_a7ddrphy_dfi_p2_address[11]), + .D6(main_a7ddrphy_dfi_p2_address[11]), + .D7(main_a7ddrphy_dfi_p3_address[11]), + .D8(main_a7ddrphy_dfi_p3_address[11]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[11]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_13 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_address[12]), + .D2(main_a7ddrphy_dfi_p0_address[12]), + .D3(main_a7ddrphy_dfi_p1_address[12]), + .D4(main_a7ddrphy_dfi_p1_address[12]), + .D5(main_a7ddrphy_dfi_p2_address[12]), + .D6(main_a7ddrphy_dfi_p2_address[12]), + .D7(main_a7ddrphy_dfi_p3_address[12]), + .D8(main_a7ddrphy_dfi_p3_address[12]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[12]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_14 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_address[13]), + .D2(main_a7ddrphy_dfi_p0_address[13]), + .D3(main_a7ddrphy_dfi_p1_address[13]), + .D4(main_a7ddrphy_dfi_p1_address[13]), + .D5(main_a7ddrphy_dfi_p2_address[13]), + .D6(main_a7ddrphy_dfi_p2_address[13]), + .D7(main_a7ddrphy_dfi_p3_address[13]), + .D8(main_a7ddrphy_dfi_p3_address[13]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_a[13]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_15 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_bank[0]), + .D2(main_a7ddrphy_dfi_p0_bank[0]), + .D3(main_a7ddrphy_dfi_p1_bank[0]), + .D4(main_a7ddrphy_dfi_p1_bank[0]), + .D5(main_a7ddrphy_dfi_p2_bank[0]), + .D6(main_a7ddrphy_dfi_p2_bank[0]), + .D7(main_a7ddrphy_dfi_p3_bank[0]), + .D8(main_a7ddrphy_dfi_p3_bank[0]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_ba[0]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_16 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_bank[1]), + .D2(main_a7ddrphy_dfi_p0_bank[1]), + .D3(main_a7ddrphy_dfi_p1_bank[1]), + .D4(main_a7ddrphy_dfi_p1_bank[1]), + .D5(main_a7ddrphy_dfi_p2_bank[1]), + .D6(main_a7ddrphy_dfi_p2_bank[1]), + .D7(main_a7ddrphy_dfi_p3_bank[1]), + .D8(main_a7ddrphy_dfi_p3_bank[1]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_ba[1]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_17 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_bank[2]), + .D2(main_a7ddrphy_dfi_p0_bank[2]), + .D3(main_a7ddrphy_dfi_p1_bank[2]), + .D4(main_a7ddrphy_dfi_p1_bank[2]), + .D5(main_a7ddrphy_dfi_p2_bank[2]), + .D6(main_a7ddrphy_dfi_p2_bank[2]), + .D7(main_a7ddrphy_dfi_p3_bank[2]), + .D8(main_a7ddrphy_dfi_p3_bank[2]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_ba[2]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_18 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_ras_n), + .D2(main_a7ddrphy_dfi_p0_ras_n), + .D3(main_a7ddrphy_dfi_p1_ras_n), + .D4(main_a7ddrphy_dfi_p1_ras_n), + .D5(main_a7ddrphy_dfi_p2_ras_n), + .D6(main_a7ddrphy_dfi_p2_ras_n), + .D7(main_a7ddrphy_dfi_p3_ras_n), + .D8(main_a7ddrphy_dfi_p3_ras_n), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_ras_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_19 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_cas_n), + .D2(main_a7ddrphy_dfi_p0_cas_n), + .D3(main_a7ddrphy_dfi_p1_cas_n), + .D4(main_a7ddrphy_dfi_p1_cas_n), + .D5(main_a7ddrphy_dfi_p2_cas_n), + .D6(main_a7ddrphy_dfi_p2_cas_n), + .D7(main_a7ddrphy_dfi_p3_cas_n), + .D8(main_a7ddrphy_dfi_p3_cas_n), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_cas_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_20 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_we_n), + .D2(main_a7ddrphy_dfi_p0_we_n), + .D3(main_a7ddrphy_dfi_p1_we_n), + .D4(main_a7ddrphy_dfi_p1_we_n), + .D5(main_a7ddrphy_dfi_p2_we_n), + .D6(main_a7ddrphy_dfi_p2_we_n), + .D7(main_a7ddrphy_dfi_p3_we_n), + .D8(main_a7ddrphy_dfi_p3_we_n), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_we_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_21 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_cke), + .D2(main_a7ddrphy_dfi_p0_cke), + .D3(main_a7ddrphy_dfi_p1_cke), + .D4(main_a7ddrphy_dfi_p1_cke), + .D5(main_a7ddrphy_dfi_p2_cke), + .D6(main_a7ddrphy_dfi_p2_cke), + .D7(main_a7ddrphy_dfi_p3_cke), + .D8(main_a7ddrphy_dfi_p3_cke), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_cke) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_22 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_odt), + .D2(main_a7ddrphy_dfi_p0_odt), + .D3(main_a7ddrphy_dfi_p1_odt), + .D4(main_a7ddrphy_dfi_p1_odt), + .D5(main_a7ddrphy_dfi_p2_odt), + .D6(main_a7ddrphy_dfi_p2_odt), + .D7(main_a7ddrphy_dfi_p3_odt), + .D8(main_a7ddrphy_dfi_p3_odt), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_odt) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_23 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_reset_n), + .D2(main_a7ddrphy_dfi_p0_reset_n), + .D3(main_a7ddrphy_dfi_p1_reset_n), + .D4(main_a7ddrphy_dfi_p1_reset_n), + .D5(main_a7ddrphy_dfi_p2_reset_n), + .D6(main_a7ddrphy_dfi_p2_reset_n), + .D7(main_a7ddrphy_dfi_p3_reset_n), + .D8(main_a7ddrphy_dfi_p3_reset_n), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_reset_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_24 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_cs_n), + .D2(main_a7ddrphy_dfi_p0_cs_n), + .D3(main_a7ddrphy_dfi_p1_cs_n), + .D4(main_a7ddrphy_dfi_p1_cs_n), + .D5(main_a7ddrphy_dfi_p2_cs_n), + .D6(main_a7ddrphy_dfi_p2_cs_n), + .D7(main_a7ddrphy_dfi_p3_cs_n), + .D8(main_a7ddrphy_dfi_p3_cs_n), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_cs_n) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_25 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_wrdata_mask[0]), + .D2(main_a7ddrphy_dfi_p0_wrdata_mask[2]), + .D3(main_a7ddrphy_dfi_p1_wrdata_mask[0]), + .D4(main_a7ddrphy_dfi_p1_wrdata_mask[2]), + .D5(main_a7ddrphy_dfi_p2_wrdata_mask[0]), + .D6(main_a7ddrphy_dfi_p2_wrdata_mask[2]), + .D7(main_a7ddrphy_dfi_p3_wrdata_mask[0]), + .D8(main_a7ddrphy_dfi_p3_wrdata_mask[2]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_dm[0]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_26 ( + .CLK(sys4x_dqs_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dqs_serdes_pattern[0]), + .D2(main_a7ddrphy_dqs_serdes_pattern[1]), + .D3(main_a7ddrphy_dqs_serdes_pattern[2]), + .D4(main_a7ddrphy_dqs_serdes_pattern[3]), + .D5(main_a7ddrphy_dqs_serdes_pattern[4]), + .D6(main_a7ddrphy_dqs_serdes_pattern[5]), + .D7(main_a7ddrphy_dqs_serdes_pattern[6]), + .D8(main_a7ddrphy_dqs_serdes_pattern[7]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~main_a7ddrphy_oe_dqs)), + .TCE(1'd1), + .OFB(main_a7ddrphy0), + .OQ(main_a7ddrphy_dqs_nodelay0), + .TQ(main_a7ddrphy_dqs_t0) +); + +OBUFTDS OBUFTDS( + .I(main_a7ddrphy_dqs_nodelay0), + .T(main_a7ddrphy_dqs_t0), + .O(ddram_dqs_p[0]), + .OB(ddram_dqs_n[0]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_27 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_wrdata_mask[1]), + .D2(main_a7ddrphy_dfi_p0_wrdata_mask[3]), + .D3(main_a7ddrphy_dfi_p1_wrdata_mask[1]), + .D4(main_a7ddrphy_dfi_p1_wrdata_mask[3]), + .D5(main_a7ddrphy_dfi_p2_wrdata_mask[1]), + .D6(main_a7ddrphy_dfi_p2_wrdata_mask[3]), + .D7(main_a7ddrphy_dfi_p3_wrdata_mask[1]), + .D8(main_a7ddrphy_dfi_p3_wrdata_mask[3]), + .OCE(1'd1), + .RST(sys_rst), + .OQ(ddram_dm[1]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_28 ( + .CLK(sys4x_dqs_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dqs_serdes_pattern[0]), + .D2(main_a7ddrphy_dqs_serdes_pattern[1]), + .D3(main_a7ddrphy_dqs_serdes_pattern[2]), + .D4(main_a7ddrphy_dqs_serdes_pattern[3]), + .D5(main_a7ddrphy_dqs_serdes_pattern[4]), + .D6(main_a7ddrphy_dqs_serdes_pattern[5]), + .D7(main_a7ddrphy_dqs_serdes_pattern[6]), + .D8(main_a7ddrphy_dqs_serdes_pattern[7]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~main_a7ddrphy_oe_dqs)), + .TCE(1'd1), + .OFB(main_a7ddrphy1), + .OQ(main_a7ddrphy_dqs_nodelay1), + .TQ(main_a7ddrphy_dqs_t1) +); + +OBUFTDS OBUFTDS_1( + .I(main_a7ddrphy_dqs_nodelay1), + .T(main_a7ddrphy_dqs_t1), + .O(ddram_dqs_p[1]), + .OB(ddram_dqs_n[1]) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_29 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_wrdata[0]), + .D2(main_a7ddrphy_dfi_p0_wrdata[16]), + .D3(main_a7ddrphy_dfi_p1_wrdata[0]), + .D4(main_a7ddrphy_dfi_p1_wrdata[16]), + .D5(main_a7ddrphy_dfi_p2_wrdata[0]), + .D6(main_a7ddrphy_dfi_p2_wrdata[16]), + .D7(main_a7ddrphy_dfi_p3_wrdata[0]), + .D8(main_a7ddrphy_dfi_p3_wrdata[16]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~main_a7ddrphy_oe_dq)), + .TCE(1'd1), + .OQ(main_a7ddrphy_dq_o_nodelay0), + .TQ(main_a7ddrphy_dq_t0) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(main_a7ddrphy_dq_i_delayed0), + .RST(sys_rst), + .Q1(main_a7ddrphy_dq_i_data0[7]), + .Q2(main_a7ddrphy_dq_i_data0[6]), + .Q3(main_a7ddrphy_dq_i_data0[5]), + .Q4(main_a7ddrphy_dq_i_data0[4]), + .Q5(main_a7ddrphy_dq_i_data0[3]), + .Q6(main_a7ddrphy_dq_i_data0[2]), + .Q7(main_a7ddrphy_dq_i_data0[1]), + .Q8(main_a7ddrphy_dq_i_data0[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2 ( + .C(sys_clk), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay0), + .INC(1'd1), + .LD((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(main_a7ddrphy_dq_i_delayed0) +); + +IOBUF IOBUF( + .I(main_a7ddrphy_dq_o_nodelay0), + .T(main_a7ddrphy_dq_t0), + .IO(ddram_dq[0]), + .O(main_a7ddrphy_dq_i_nodelay0) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_30 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_wrdata[1]), + .D2(main_a7ddrphy_dfi_p0_wrdata[17]), + .D3(main_a7ddrphy_dfi_p1_wrdata[1]), + .D4(main_a7ddrphy_dfi_p1_wrdata[17]), + .D5(main_a7ddrphy_dfi_p2_wrdata[1]), + .D6(main_a7ddrphy_dfi_p2_wrdata[17]), + .D7(main_a7ddrphy_dfi_p3_wrdata[1]), + .D8(main_a7ddrphy_dfi_p3_wrdata[17]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~main_a7ddrphy_oe_dq)), + .TCE(1'd1), + .OQ(main_a7ddrphy_dq_o_nodelay1), + .TQ(main_a7ddrphy_dq_t1) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_1 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(main_a7ddrphy_dq_i_delayed1), + .RST(sys_rst), + .Q1(main_a7ddrphy_dq_i_data1[7]), + .Q2(main_a7ddrphy_dq_i_data1[6]), + .Q3(main_a7ddrphy_dq_i_data1[5]), + .Q4(main_a7ddrphy_dq_i_data1[4]), + .Q5(main_a7ddrphy_dq_i_data1[3]), + .Q6(main_a7ddrphy_dq_i_data1[2]), + .Q7(main_a7ddrphy_dq_i_data1[1]), + .Q8(main_a7ddrphy_dq_i_data1[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_1 ( + .C(sys_clk), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay1), + .INC(1'd1), + .LD((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(main_a7ddrphy_dq_i_delayed1) +); + +IOBUF IOBUF_1( + .I(main_a7ddrphy_dq_o_nodelay1), + .T(main_a7ddrphy_dq_t1), + .IO(ddram_dq[1]), + .O(main_a7ddrphy_dq_i_nodelay1) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_31 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_wrdata[2]), + .D2(main_a7ddrphy_dfi_p0_wrdata[18]), + .D3(main_a7ddrphy_dfi_p1_wrdata[2]), + .D4(main_a7ddrphy_dfi_p1_wrdata[18]), + .D5(main_a7ddrphy_dfi_p2_wrdata[2]), + .D6(main_a7ddrphy_dfi_p2_wrdata[18]), + .D7(main_a7ddrphy_dfi_p3_wrdata[2]), + .D8(main_a7ddrphy_dfi_p3_wrdata[18]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~main_a7ddrphy_oe_dq)), + .TCE(1'd1), + .OQ(main_a7ddrphy_dq_o_nodelay2), + .TQ(main_a7ddrphy_dq_t2) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_2 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(main_a7ddrphy_dq_i_delayed2), + .RST(sys_rst), + .Q1(main_a7ddrphy_dq_i_data2[7]), + .Q2(main_a7ddrphy_dq_i_data2[6]), + .Q3(main_a7ddrphy_dq_i_data2[5]), + .Q4(main_a7ddrphy_dq_i_data2[4]), + .Q5(main_a7ddrphy_dq_i_data2[3]), + .Q6(main_a7ddrphy_dq_i_data2[2]), + .Q7(main_a7ddrphy_dq_i_data2[1]), + .Q8(main_a7ddrphy_dq_i_data2[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_2 ( + .C(sys_clk), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay2), + .INC(1'd1), + .LD((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(main_a7ddrphy_dq_i_delayed2) +); + +IOBUF IOBUF_2( + .I(main_a7ddrphy_dq_o_nodelay2), + .T(main_a7ddrphy_dq_t2), + .IO(ddram_dq[2]), + .O(main_a7ddrphy_dq_i_nodelay2) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_32 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_wrdata[3]), + .D2(main_a7ddrphy_dfi_p0_wrdata[19]), + .D3(main_a7ddrphy_dfi_p1_wrdata[3]), + .D4(main_a7ddrphy_dfi_p1_wrdata[19]), + .D5(main_a7ddrphy_dfi_p2_wrdata[3]), + .D6(main_a7ddrphy_dfi_p2_wrdata[19]), + .D7(main_a7ddrphy_dfi_p3_wrdata[3]), + .D8(main_a7ddrphy_dfi_p3_wrdata[19]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~main_a7ddrphy_oe_dq)), + .TCE(1'd1), + .OQ(main_a7ddrphy_dq_o_nodelay3), + .TQ(main_a7ddrphy_dq_t3) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_3 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(main_a7ddrphy_dq_i_delayed3), + .RST(sys_rst), + .Q1(main_a7ddrphy_dq_i_data3[7]), + .Q2(main_a7ddrphy_dq_i_data3[6]), + .Q3(main_a7ddrphy_dq_i_data3[5]), + .Q4(main_a7ddrphy_dq_i_data3[4]), + .Q5(main_a7ddrphy_dq_i_data3[3]), + .Q6(main_a7ddrphy_dq_i_data3[2]), + .Q7(main_a7ddrphy_dq_i_data3[1]), + .Q8(main_a7ddrphy_dq_i_data3[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_3 ( + .C(sys_clk), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay3), + .INC(1'd1), + .LD((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(main_a7ddrphy_dq_i_delayed3) +); + +IOBUF IOBUF_3( + .I(main_a7ddrphy_dq_o_nodelay3), + .T(main_a7ddrphy_dq_t3), + .IO(ddram_dq[3]), + .O(main_a7ddrphy_dq_i_nodelay3) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_33 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_wrdata[4]), + .D2(main_a7ddrphy_dfi_p0_wrdata[20]), + .D3(main_a7ddrphy_dfi_p1_wrdata[4]), + .D4(main_a7ddrphy_dfi_p1_wrdata[20]), + .D5(main_a7ddrphy_dfi_p2_wrdata[4]), + .D6(main_a7ddrphy_dfi_p2_wrdata[20]), + .D7(main_a7ddrphy_dfi_p3_wrdata[4]), + .D8(main_a7ddrphy_dfi_p3_wrdata[20]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~main_a7ddrphy_oe_dq)), + .TCE(1'd1), + .OQ(main_a7ddrphy_dq_o_nodelay4), + .TQ(main_a7ddrphy_dq_t4) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_4 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(main_a7ddrphy_dq_i_delayed4), + .RST(sys_rst), + .Q1(main_a7ddrphy_dq_i_data4[7]), + .Q2(main_a7ddrphy_dq_i_data4[6]), + .Q3(main_a7ddrphy_dq_i_data4[5]), + .Q4(main_a7ddrphy_dq_i_data4[4]), + .Q5(main_a7ddrphy_dq_i_data4[3]), + .Q6(main_a7ddrphy_dq_i_data4[2]), + .Q7(main_a7ddrphy_dq_i_data4[1]), + .Q8(main_a7ddrphy_dq_i_data4[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_4 ( + .C(sys_clk), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay4), + .INC(1'd1), + .LD((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(main_a7ddrphy_dq_i_delayed4) +); + +IOBUF IOBUF_4( + .I(main_a7ddrphy_dq_o_nodelay4), + .T(main_a7ddrphy_dq_t4), + .IO(ddram_dq[4]), + .O(main_a7ddrphy_dq_i_nodelay4) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_34 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_wrdata[5]), + .D2(main_a7ddrphy_dfi_p0_wrdata[21]), + .D3(main_a7ddrphy_dfi_p1_wrdata[5]), + .D4(main_a7ddrphy_dfi_p1_wrdata[21]), + .D5(main_a7ddrphy_dfi_p2_wrdata[5]), + .D6(main_a7ddrphy_dfi_p2_wrdata[21]), + .D7(main_a7ddrphy_dfi_p3_wrdata[5]), + .D8(main_a7ddrphy_dfi_p3_wrdata[21]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~main_a7ddrphy_oe_dq)), + .TCE(1'd1), + .OQ(main_a7ddrphy_dq_o_nodelay5), + .TQ(main_a7ddrphy_dq_t5) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_5 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(main_a7ddrphy_dq_i_delayed5), + .RST(sys_rst), + .Q1(main_a7ddrphy_dq_i_data5[7]), + .Q2(main_a7ddrphy_dq_i_data5[6]), + .Q3(main_a7ddrphy_dq_i_data5[5]), + .Q4(main_a7ddrphy_dq_i_data5[4]), + .Q5(main_a7ddrphy_dq_i_data5[3]), + .Q6(main_a7ddrphy_dq_i_data5[2]), + .Q7(main_a7ddrphy_dq_i_data5[1]), + .Q8(main_a7ddrphy_dq_i_data5[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_5 ( + .C(sys_clk), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay5), + .INC(1'd1), + .LD((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(main_a7ddrphy_dq_i_delayed5) +); + +IOBUF IOBUF_5( + .I(main_a7ddrphy_dq_o_nodelay5), + .T(main_a7ddrphy_dq_t5), + .IO(ddram_dq[5]), + .O(main_a7ddrphy_dq_i_nodelay5) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_35 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_wrdata[6]), + .D2(main_a7ddrphy_dfi_p0_wrdata[22]), + .D3(main_a7ddrphy_dfi_p1_wrdata[6]), + .D4(main_a7ddrphy_dfi_p1_wrdata[22]), + .D5(main_a7ddrphy_dfi_p2_wrdata[6]), + .D6(main_a7ddrphy_dfi_p2_wrdata[22]), + .D7(main_a7ddrphy_dfi_p3_wrdata[6]), + .D8(main_a7ddrphy_dfi_p3_wrdata[22]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~main_a7ddrphy_oe_dq)), + .TCE(1'd1), + .OQ(main_a7ddrphy_dq_o_nodelay6), + .TQ(main_a7ddrphy_dq_t6) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_6 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(main_a7ddrphy_dq_i_delayed6), + .RST(sys_rst), + .Q1(main_a7ddrphy_dq_i_data6[7]), + .Q2(main_a7ddrphy_dq_i_data6[6]), + .Q3(main_a7ddrphy_dq_i_data6[5]), + .Q4(main_a7ddrphy_dq_i_data6[4]), + .Q5(main_a7ddrphy_dq_i_data6[3]), + .Q6(main_a7ddrphy_dq_i_data6[2]), + .Q7(main_a7ddrphy_dq_i_data6[1]), + .Q8(main_a7ddrphy_dq_i_data6[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_6 ( + .C(sys_clk), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay6), + .INC(1'd1), + .LD((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(main_a7ddrphy_dq_i_delayed6) +); + +IOBUF IOBUF_6( + .I(main_a7ddrphy_dq_o_nodelay6), + .T(main_a7ddrphy_dq_t6), + .IO(ddram_dq[6]), + .O(main_a7ddrphy_dq_i_nodelay6) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_36 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_wrdata[7]), + .D2(main_a7ddrphy_dfi_p0_wrdata[23]), + .D3(main_a7ddrphy_dfi_p1_wrdata[7]), + .D4(main_a7ddrphy_dfi_p1_wrdata[23]), + .D5(main_a7ddrphy_dfi_p2_wrdata[7]), + .D6(main_a7ddrphy_dfi_p2_wrdata[23]), + .D7(main_a7ddrphy_dfi_p3_wrdata[7]), + .D8(main_a7ddrphy_dfi_p3_wrdata[23]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~main_a7ddrphy_oe_dq)), + .TCE(1'd1), + .OQ(main_a7ddrphy_dq_o_nodelay7), + .TQ(main_a7ddrphy_dq_t7) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_7 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(main_a7ddrphy_dq_i_delayed7), + .RST(sys_rst), + .Q1(main_a7ddrphy_dq_i_data7[7]), + .Q2(main_a7ddrphy_dq_i_data7[6]), + .Q3(main_a7ddrphy_dq_i_data7[5]), + .Q4(main_a7ddrphy_dq_i_data7[4]), + .Q5(main_a7ddrphy_dq_i_data7[3]), + .Q6(main_a7ddrphy_dq_i_data7[2]), + .Q7(main_a7ddrphy_dq_i_data7[1]), + .Q8(main_a7ddrphy_dq_i_data7[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_7 ( + .C(sys_clk), + .CE((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay7), + .INC(1'd1), + .LD((main_a7ddrphy_dly_sel_storage[0] & main_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(main_a7ddrphy_dq_i_delayed7) +); + +IOBUF IOBUF_7( + .I(main_a7ddrphy_dq_o_nodelay7), + .T(main_a7ddrphy_dq_t7), + .IO(ddram_dq[7]), + .O(main_a7ddrphy_dq_i_nodelay7) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_37 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_wrdata[8]), + .D2(main_a7ddrphy_dfi_p0_wrdata[24]), + .D3(main_a7ddrphy_dfi_p1_wrdata[8]), + .D4(main_a7ddrphy_dfi_p1_wrdata[24]), + .D5(main_a7ddrphy_dfi_p2_wrdata[8]), + .D6(main_a7ddrphy_dfi_p2_wrdata[24]), + .D7(main_a7ddrphy_dfi_p3_wrdata[8]), + .D8(main_a7ddrphy_dfi_p3_wrdata[24]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~main_a7ddrphy_oe_dq)), + .TCE(1'd1), + .OQ(main_a7ddrphy_dq_o_nodelay8), + .TQ(main_a7ddrphy_dq_t8) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_8 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(main_a7ddrphy_dq_i_delayed8), + .RST(sys_rst), + .Q1(main_a7ddrphy_dq_i_data8[7]), + .Q2(main_a7ddrphy_dq_i_data8[6]), + .Q3(main_a7ddrphy_dq_i_data8[5]), + .Q4(main_a7ddrphy_dq_i_data8[4]), + .Q5(main_a7ddrphy_dq_i_data8[3]), + .Q6(main_a7ddrphy_dq_i_data8[2]), + .Q7(main_a7ddrphy_dq_i_data8[1]), + .Q8(main_a7ddrphy_dq_i_data8[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_8 ( + .C(sys_clk), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay8), + .INC(1'd1), + .LD((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(main_a7ddrphy_dq_i_delayed8) +); + +IOBUF IOBUF_8( + .I(main_a7ddrphy_dq_o_nodelay8), + .T(main_a7ddrphy_dq_t8), + .IO(ddram_dq[8]), + .O(main_a7ddrphy_dq_i_nodelay8) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_38 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_wrdata[9]), + .D2(main_a7ddrphy_dfi_p0_wrdata[25]), + .D3(main_a7ddrphy_dfi_p1_wrdata[9]), + .D4(main_a7ddrphy_dfi_p1_wrdata[25]), + .D5(main_a7ddrphy_dfi_p2_wrdata[9]), + .D6(main_a7ddrphy_dfi_p2_wrdata[25]), + .D7(main_a7ddrphy_dfi_p3_wrdata[9]), + .D8(main_a7ddrphy_dfi_p3_wrdata[25]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~main_a7ddrphy_oe_dq)), + .TCE(1'd1), + .OQ(main_a7ddrphy_dq_o_nodelay9), + .TQ(main_a7ddrphy_dq_t9) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_9 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(main_a7ddrphy_dq_i_delayed9), + .RST(sys_rst), + .Q1(main_a7ddrphy_dq_i_data9[7]), + .Q2(main_a7ddrphy_dq_i_data9[6]), + .Q3(main_a7ddrphy_dq_i_data9[5]), + .Q4(main_a7ddrphy_dq_i_data9[4]), + .Q5(main_a7ddrphy_dq_i_data9[3]), + .Q6(main_a7ddrphy_dq_i_data9[2]), + .Q7(main_a7ddrphy_dq_i_data9[1]), + .Q8(main_a7ddrphy_dq_i_data9[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_9 ( + .C(sys_clk), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay9), + .INC(1'd1), + .LD((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(main_a7ddrphy_dq_i_delayed9) +); + +IOBUF IOBUF_9( + .I(main_a7ddrphy_dq_o_nodelay9), + .T(main_a7ddrphy_dq_t9), + .IO(ddram_dq[9]), + .O(main_a7ddrphy_dq_i_nodelay9) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_39 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_wrdata[10]), + .D2(main_a7ddrphy_dfi_p0_wrdata[26]), + .D3(main_a7ddrphy_dfi_p1_wrdata[10]), + .D4(main_a7ddrphy_dfi_p1_wrdata[26]), + .D5(main_a7ddrphy_dfi_p2_wrdata[10]), + .D6(main_a7ddrphy_dfi_p2_wrdata[26]), + .D7(main_a7ddrphy_dfi_p3_wrdata[10]), + .D8(main_a7ddrphy_dfi_p3_wrdata[26]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~main_a7ddrphy_oe_dq)), + .TCE(1'd1), + .OQ(main_a7ddrphy_dq_o_nodelay10), + .TQ(main_a7ddrphy_dq_t10) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_10 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(main_a7ddrphy_dq_i_delayed10), + .RST(sys_rst), + .Q1(main_a7ddrphy_dq_i_data10[7]), + .Q2(main_a7ddrphy_dq_i_data10[6]), + .Q3(main_a7ddrphy_dq_i_data10[5]), + .Q4(main_a7ddrphy_dq_i_data10[4]), + .Q5(main_a7ddrphy_dq_i_data10[3]), + .Q6(main_a7ddrphy_dq_i_data10[2]), + .Q7(main_a7ddrphy_dq_i_data10[1]), + .Q8(main_a7ddrphy_dq_i_data10[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_10 ( + .C(sys_clk), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay10), + .INC(1'd1), + .LD((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(main_a7ddrphy_dq_i_delayed10) +); + +IOBUF IOBUF_10( + .I(main_a7ddrphy_dq_o_nodelay10), + .T(main_a7ddrphy_dq_t10), + .IO(ddram_dq[10]), + .O(main_a7ddrphy_dq_i_nodelay10) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_40 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_wrdata[11]), + .D2(main_a7ddrphy_dfi_p0_wrdata[27]), + .D3(main_a7ddrphy_dfi_p1_wrdata[11]), + .D4(main_a7ddrphy_dfi_p1_wrdata[27]), + .D5(main_a7ddrphy_dfi_p2_wrdata[11]), + .D6(main_a7ddrphy_dfi_p2_wrdata[27]), + .D7(main_a7ddrphy_dfi_p3_wrdata[11]), + .D8(main_a7ddrphy_dfi_p3_wrdata[27]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~main_a7ddrphy_oe_dq)), + .TCE(1'd1), + .OQ(main_a7ddrphy_dq_o_nodelay11), + .TQ(main_a7ddrphy_dq_t11) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_11 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(main_a7ddrphy_dq_i_delayed11), + .RST(sys_rst), + .Q1(main_a7ddrphy_dq_i_data11[7]), + .Q2(main_a7ddrphy_dq_i_data11[6]), + .Q3(main_a7ddrphy_dq_i_data11[5]), + .Q4(main_a7ddrphy_dq_i_data11[4]), + .Q5(main_a7ddrphy_dq_i_data11[3]), + .Q6(main_a7ddrphy_dq_i_data11[2]), + .Q7(main_a7ddrphy_dq_i_data11[1]), + .Q8(main_a7ddrphy_dq_i_data11[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_11 ( + .C(sys_clk), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay11), + .INC(1'd1), + .LD((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(main_a7ddrphy_dq_i_delayed11) +); + +IOBUF IOBUF_11( + .I(main_a7ddrphy_dq_o_nodelay11), + .T(main_a7ddrphy_dq_t11), + .IO(ddram_dq[11]), + .O(main_a7ddrphy_dq_i_nodelay11) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_41 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_wrdata[12]), + .D2(main_a7ddrphy_dfi_p0_wrdata[28]), + .D3(main_a7ddrphy_dfi_p1_wrdata[12]), + .D4(main_a7ddrphy_dfi_p1_wrdata[28]), + .D5(main_a7ddrphy_dfi_p2_wrdata[12]), + .D6(main_a7ddrphy_dfi_p2_wrdata[28]), + .D7(main_a7ddrphy_dfi_p3_wrdata[12]), + .D8(main_a7ddrphy_dfi_p3_wrdata[28]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~main_a7ddrphy_oe_dq)), + .TCE(1'd1), + .OQ(main_a7ddrphy_dq_o_nodelay12), + .TQ(main_a7ddrphy_dq_t12) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_12 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(main_a7ddrphy_dq_i_delayed12), + .RST(sys_rst), + .Q1(main_a7ddrphy_dq_i_data12[7]), + .Q2(main_a7ddrphy_dq_i_data12[6]), + .Q3(main_a7ddrphy_dq_i_data12[5]), + .Q4(main_a7ddrphy_dq_i_data12[4]), + .Q5(main_a7ddrphy_dq_i_data12[3]), + .Q6(main_a7ddrphy_dq_i_data12[2]), + .Q7(main_a7ddrphy_dq_i_data12[1]), + .Q8(main_a7ddrphy_dq_i_data12[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_12 ( + .C(sys_clk), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay12), + .INC(1'd1), + .LD((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(main_a7ddrphy_dq_i_delayed12) +); + +IOBUF IOBUF_12( + .I(main_a7ddrphy_dq_o_nodelay12), + .T(main_a7ddrphy_dq_t12), + .IO(ddram_dq[12]), + .O(main_a7ddrphy_dq_i_nodelay12) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_42 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_wrdata[13]), + .D2(main_a7ddrphy_dfi_p0_wrdata[29]), + .D3(main_a7ddrphy_dfi_p1_wrdata[13]), + .D4(main_a7ddrphy_dfi_p1_wrdata[29]), + .D5(main_a7ddrphy_dfi_p2_wrdata[13]), + .D6(main_a7ddrphy_dfi_p2_wrdata[29]), + .D7(main_a7ddrphy_dfi_p3_wrdata[13]), + .D8(main_a7ddrphy_dfi_p3_wrdata[29]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~main_a7ddrphy_oe_dq)), + .TCE(1'd1), + .OQ(main_a7ddrphy_dq_o_nodelay13), + .TQ(main_a7ddrphy_dq_t13) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_13 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(main_a7ddrphy_dq_i_delayed13), + .RST(sys_rst), + .Q1(main_a7ddrphy_dq_i_data13[7]), + .Q2(main_a7ddrphy_dq_i_data13[6]), + .Q3(main_a7ddrphy_dq_i_data13[5]), + .Q4(main_a7ddrphy_dq_i_data13[4]), + .Q5(main_a7ddrphy_dq_i_data13[3]), + .Q6(main_a7ddrphy_dq_i_data13[2]), + .Q7(main_a7ddrphy_dq_i_data13[1]), + .Q8(main_a7ddrphy_dq_i_data13[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_13 ( + .C(sys_clk), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay13), + .INC(1'd1), + .LD((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(main_a7ddrphy_dq_i_delayed13) +); + +IOBUF IOBUF_13( + .I(main_a7ddrphy_dq_o_nodelay13), + .T(main_a7ddrphy_dq_t13), + .IO(ddram_dq[13]), + .O(main_a7ddrphy_dq_i_nodelay13) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_43 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_wrdata[14]), + .D2(main_a7ddrphy_dfi_p0_wrdata[30]), + .D3(main_a7ddrphy_dfi_p1_wrdata[14]), + .D4(main_a7ddrphy_dfi_p1_wrdata[30]), + .D5(main_a7ddrphy_dfi_p2_wrdata[14]), + .D6(main_a7ddrphy_dfi_p2_wrdata[30]), + .D7(main_a7ddrphy_dfi_p3_wrdata[14]), + .D8(main_a7ddrphy_dfi_p3_wrdata[30]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~main_a7ddrphy_oe_dq)), + .TCE(1'd1), + .OQ(main_a7ddrphy_dq_o_nodelay14), + .TQ(main_a7ddrphy_dq_t14) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_14 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(main_a7ddrphy_dq_i_delayed14), + .RST(sys_rst), + .Q1(main_a7ddrphy_dq_i_data14[7]), + .Q2(main_a7ddrphy_dq_i_data14[6]), + .Q3(main_a7ddrphy_dq_i_data14[5]), + .Q4(main_a7ddrphy_dq_i_data14[4]), + .Q5(main_a7ddrphy_dq_i_data14[3]), + .Q6(main_a7ddrphy_dq_i_data14[2]), + .Q7(main_a7ddrphy_dq_i_data14[1]), + .Q8(main_a7ddrphy_dq_i_data14[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_14 ( + .C(sys_clk), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay14), + .INC(1'd1), + .LD((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(main_a7ddrphy_dq_i_delayed14) +); + +IOBUF IOBUF_14( + .I(main_a7ddrphy_dq_o_nodelay14), + .T(main_a7ddrphy_dq_t14), + .IO(ddram_dq[14]), + .O(main_a7ddrphy_dq_i_nodelay14) +); + +OSERDESE2 #( + .DATA_RATE_OQ("DDR"), + .DATA_RATE_TQ("BUF"), + .DATA_WIDTH(4'd8), + .SERDES_MODE("MASTER"), + .TRISTATE_WIDTH(1'd1) +) OSERDESE2_44 ( + .CLK(sys4x_clk), + .CLKDIV(sys_clk), + .D1(main_a7ddrphy_dfi_p0_wrdata[15]), + .D2(main_a7ddrphy_dfi_p0_wrdata[31]), + .D3(main_a7ddrphy_dfi_p1_wrdata[15]), + .D4(main_a7ddrphy_dfi_p1_wrdata[31]), + .D5(main_a7ddrphy_dfi_p2_wrdata[15]), + .D6(main_a7ddrphy_dfi_p2_wrdata[31]), + .D7(main_a7ddrphy_dfi_p3_wrdata[15]), + .D8(main_a7ddrphy_dfi_p3_wrdata[31]), + .OCE(1'd1), + .RST(sys_rst), + .T1((~main_a7ddrphy_oe_dq)), + .TCE(1'd1), + .OQ(main_a7ddrphy_dq_o_nodelay15), + .TQ(main_a7ddrphy_dq_t15) +); + +ISERDESE2 #( + .DATA_RATE("DDR"), + .DATA_WIDTH(4'd8), + .INTERFACE_TYPE("NETWORKING"), + .IOBDELAY("IFD"), + .NUM_CE(1'd1), + .SERDES_MODE("MASTER") +) ISERDESE2_15 ( + .BITSLIP(1'd0), + .CE1(1'd1), + .CLK(sys4x_clk), + .CLKB((~sys4x_clk)), + .CLKDIV(sys_clk), + .DDLY(main_a7ddrphy_dq_i_delayed15), + .RST(sys_rst), + .Q1(main_a7ddrphy_dq_i_data15[7]), + .Q2(main_a7ddrphy_dq_i_data15[6]), + .Q3(main_a7ddrphy_dq_i_data15[5]), + .Q4(main_a7ddrphy_dq_i_data15[4]), + .Q5(main_a7ddrphy_dq_i_data15[3]), + .Q6(main_a7ddrphy_dq_i_data15[2]), + .Q7(main_a7ddrphy_dq_i_data15[1]), + .Q8(main_a7ddrphy_dq_i_data15[0]) +); + +IDELAYE2 #( + .CINVCTRL_SEL("FALSE"), + .DELAY_SRC("IDATAIN"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .IDELAY_TYPE("VARIABLE"), + .IDELAY_VALUE(1'd0), + .PIPE_SEL("FALSE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA") +) IDELAYE2_15 ( + .C(sys_clk), + .CE((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_inc_re)), + .IDATAIN(main_a7ddrphy_dq_i_nodelay15), + .INC(1'd1), + .LD((main_a7ddrphy_dly_sel_storage[1] & main_a7ddrphy_rdly_dq_rst_re)), + .LDPIPEEN(1'd0), + .DATAOUT(main_a7ddrphy_dq_i_delayed15) +); + +IOBUF IOBUF_15( + .I(main_a7ddrphy_dq_o_nodelay15), + .T(main_a7ddrphy_dq_t15), + .IO(ddram_dq[15]), + .O(main_a7ddrphy_dq_i_nodelay15) +); + +reg [23:0] storage_2[0:7]; +reg [23:0] memdat_5; +always @(posedge sys_clk) begin + if (main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we) + storage_2[main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w; + memdat_5 <= storage_2[main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat_5; +assign main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage_2[main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_3[0:7]; +reg [23:0] memdat_6; +always @(posedge sys_clk) begin + if (main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we) + storage_3[main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w; + memdat_6 <= storage_3[main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_6; +assign main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_3[main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_4[0:7]; +reg [23:0] memdat_7; +always @(posedge sys_clk) begin + if (main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we) + storage_4[main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w; + memdat_7 <= storage_4[main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_7; +assign main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_4[main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_5[0:7]; +reg [23:0] memdat_8; +always @(posedge sys_clk) begin + if (main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we) + storage_5[main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w; + memdat_8 <= storage_5[main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_8; +assign main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_5[main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_6[0:7]; +reg [23:0] memdat_9; +always @(posedge sys_clk) begin + if (main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we) + storage_6[main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w; + memdat_9 <= storage_6[main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign main_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_9; +assign main_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_6[main_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_7[0:7]; +reg [23:0] memdat_10; +always @(posedge sys_clk) begin + if (main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we) + storage_7[main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w; + memdat_10 <= storage_7[main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign main_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_10; +assign main_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_7[main_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_8[0:7]; +reg [23:0] memdat_11; +always @(posedge sys_clk) begin + if (main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we) + storage_8[main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w; + memdat_11 <= storage_8[main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign main_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_11; +assign main_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_8[main_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] storage_9[0:7]; +reg [23:0] memdat_12; +always @(posedge sys_clk) begin + if (main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we) + storage_9[main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w; + memdat_12 <= storage_9[main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr]; +end + +always @(posedge sys_clk) begin +end + +assign main_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_12; +assign main_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_9[main_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr]; + +reg [23:0] tag_mem[0:511]; +reg [8:0] memadr_1; +always @(posedge sys_clk) begin + if (main_tag_port_we) + tag_mem[main_tag_port_adr] <= main_tag_port_dat_w; + memadr_1 <= main_tag_port_adr; +end + +assign main_tag_port_dat_r = tag_mem[memadr_1]; + +VexRiscv VexRiscv( + .clk(sys_clk), + .dBusWishbone_ACK(main_cpu_dbus_ack), + .dBusWishbone_DAT_MISO(main_cpu_dbus_dat_r), + .dBusWishbone_ERR(main_cpu_dbus_err), + .externalInterruptArray(main_cpu_interrupt), + .externalResetVector(1'd0), + .iBusWishbone_ACK(main_cpu_ibus_ack), + .iBusWishbone_DAT_MISO(main_cpu_ibus_dat_r), + .iBusWishbone_ERR(main_cpu_ibus_err), + .reset((sys_rst | main_cpu_reset)), + .softwareInterrupt(1'd0), + .timerInterrupt(1'd0), + .dBusWishbone_ADR(main_cpu_dbus_adr), + .dBusWishbone_BTE(main_cpu_dbus_bte), + .dBusWishbone_CTI(main_cpu_dbus_cti), + .dBusWishbone_CYC(main_cpu_dbus_cyc), + .dBusWishbone_DAT_MOSI(main_cpu_dbus_dat_w), + .dBusWishbone_SEL(main_cpu_dbus_sel), + .dBusWishbone_STB(main_cpu_dbus_stb), + .dBusWishbone_WE(main_cpu_dbus_we), + .iBusWishbone_ADR(main_cpu_ibus_adr), + .iBusWishbone_BTE(main_cpu_ibus_bte), + .iBusWishbone_CTI(main_cpu_ibus_cti), + .iBusWishbone_CYC(main_cpu_ibus_cyc), + .iBusWishbone_DAT_MOSI(main_cpu_ibus_dat_w), + .iBusWishbone_SEL(main_cpu_ibus_sel), + .iBusWishbone_STB(main_cpu_ibus_stb), + .iBusWishbone_WE(main_cpu_ibus_we) +); + +PLLE2_ADV #( + .CLKFBOUT_MULT(5'd16), + .CLKIN1_PERIOD(10.0), + .CLKOUT0_DIVIDE(6'd32), + .CLKOUT0_PHASE(1'd0), + .CLKOUT1_DIVIDE(4'd8), + .CLKOUT1_PHASE(1'd0), + .CLKOUT2_DIVIDE(4'd8), + .CLKOUT2_PHASE(7'd90), + .CLKOUT3_DIVIDE(4'd8), + .CLKOUT3_PHASE(1'd0), + .DIVCLK_DIVIDE(1'd1), + .REF_JITTER1(0.01), + .STARTUP_WAIT("FALSE") +) PLLE2_ADV ( + .CLKFBIN(builder_pll_fb), + .CLKIN1(main_clkin), + .RST(main_reset), + .CLKFBOUT(builder_pll_fb), + .CLKOUT0(main_clkout0), + .CLKOUT1(main_clkout1), + .CLKOUT2(main_clkout2), + .CLKOUT3(main_clkout3), + .LOCKED(main_locked) +); + +reg [7:0] data_mem_grain0[0:511]; +reg [8:0] memadr_2; +always @(posedge sys_clk) begin + if (main_data_port_we[0]) + data_mem_grain0[main_data_port_adr] <= main_data_port_dat_w[7:0]; + memadr_2 <= main_data_port_adr; +end + +assign main_data_port_dat_r[7:0] = data_mem_grain0[memadr_2]; + +reg [7:0] data_mem_grain1[0:511]; +reg [8:0] memadr_3; +always @(posedge sys_clk) begin + if (main_data_port_we[1]) + data_mem_grain1[main_data_port_adr] <= main_data_port_dat_w[15:8]; + memadr_3 <= main_data_port_adr; +end + +assign main_data_port_dat_r[15:8] = data_mem_grain1[memadr_3]; + +reg [7:0] data_mem_grain2[0:511]; +reg [8:0] memadr_4; +always @(posedge sys_clk) begin + if (main_data_port_we[2]) + data_mem_grain2[main_data_port_adr] <= main_data_port_dat_w[23:16]; + memadr_4 <= main_data_port_adr; +end + +assign main_data_port_dat_r[23:16] = data_mem_grain2[memadr_4]; + +reg [7:0] data_mem_grain3[0:511]; +reg [8:0] memadr_5; +always @(posedge sys_clk) begin + if (main_data_port_we[3]) + data_mem_grain3[main_data_port_adr] <= main_data_port_dat_w[31:24]; + memadr_5 <= main_data_port_adr; +end + +assign main_data_port_dat_r[31:24] = data_mem_grain3[memadr_5]; + +reg [7:0] data_mem_grain4[0:511]; +reg [8:0] memadr_6; +always @(posedge sys_clk) begin + if (main_data_port_we[4]) + data_mem_grain4[main_data_port_adr] <= main_data_port_dat_w[39:32]; + memadr_6 <= main_data_port_adr; +end + +assign main_data_port_dat_r[39:32] = data_mem_grain4[memadr_6]; + +reg [7:0] data_mem_grain5[0:511]; +reg [8:0] memadr_7; +always @(posedge sys_clk) begin + if (main_data_port_we[5]) + data_mem_grain5[main_data_port_adr] <= main_data_port_dat_w[47:40]; + memadr_7 <= main_data_port_adr; +end + +assign main_data_port_dat_r[47:40] = data_mem_grain5[memadr_7]; + +reg [7:0] data_mem_grain6[0:511]; +reg [8:0] memadr_8; +always @(posedge sys_clk) begin + if (main_data_port_we[6]) + data_mem_grain6[main_data_port_adr] <= main_data_port_dat_w[55:48]; + memadr_8 <= main_data_port_adr; +end + +assign main_data_port_dat_r[55:48] = data_mem_grain6[memadr_8]; + +reg [7:0] data_mem_grain7[0:511]; +reg [8:0] memadr_9; +always @(posedge sys_clk) begin + if (main_data_port_we[7]) + data_mem_grain7[main_data_port_adr] <= main_data_port_dat_w[63:56]; + memadr_9 <= main_data_port_adr; +end + +assign main_data_port_dat_r[63:56] = data_mem_grain7[memadr_9]; + +reg [7:0] data_mem_grain8[0:511]; +reg [8:0] memadr_10; +always @(posedge sys_clk) begin + if (main_data_port_we[8]) + data_mem_grain8[main_data_port_adr] <= main_data_port_dat_w[71:64]; + memadr_10 <= main_data_port_adr; +end + +assign main_data_port_dat_r[71:64] = data_mem_grain8[memadr_10]; + +reg [7:0] data_mem_grain9[0:511]; +reg [8:0] memadr_11; +always @(posedge sys_clk) begin + if (main_data_port_we[9]) + data_mem_grain9[main_data_port_adr] <= main_data_port_dat_w[79:72]; + memadr_11 <= main_data_port_adr; +end + +assign main_data_port_dat_r[79:72] = data_mem_grain9[memadr_11]; + +reg [7:0] data_mem_grain10[0:511]; +reg [8:0] memadr_12; +always @(posedge sys_clk) begin + if (main_data_port_we[10]) + data_mem_grain10[main_data_port_adr] <= main_data_port_dat_w[87:80]; + memadr_12 <= main_data_port_adr; +end + +assign main_data_port_dat_r[87:80] = data_mem_grain10[memadr_12]; + +reg [7:0] data_mem_grain11[0:511]; +reg [8:0] memadr_13; +always @(posedge sys_clk) begin + if (main_data_port_we[11]) + data_mem_grain11[main_data_port_adr] <= main_data_port_dat_w[95:88]; + memadr_13 <= main_data_port_adr; +end + +assign main_data_port_dat_r[95:88] = data_mem_grain11[memadr_13]; + +reg [7:0] data_mem_grain12[0:511]; +reg [8:0] memadr_14; +always @(posedge sys_clk) begin + if (main_data_port_we[12]) + data_mem_grain12[main_data_port_adr] <= main_data_port_dat_w[103:96]; + memadr_14 <= main_data_port_adr; +end + +assign main_data_port_dat_r[103:96] = data_mem_grain12[memadr_14]; + +reg [7:0] data_mem_grain13[0:511]; +reg [8:0] memadr_15; +always @(posedge sys_clk) begin + if (main_data_port_we[13]) + data_mem_grain13[main_data_port_adr] <= main_data_port_dat_w[111:104]; + memadr_15 <= main_data_port_adr; +end + +assign main_data_port_dat_r[111:104] = data_mem_grain13[memadr_15]; + +reg [7:0] data_mem_grain14[0:511]; +reg [8:0] memadr_16; +always @(posedge sys_clk) begin + if (main_data_port_we[14]) + data_mem_grain14[main_data_port_adr] <= main_data_port_dat_w[119:112]; + memadr_16 <= main_data_port_adr; +end + +assign main_data_port_dat_r[119:112] = data_mem_grain14[memadr_16]; + +reg [7:0] data_mem_grain15[0:511]; +reg [8:0] memadr_17; +always @(posedge sys_clk) begin + if (main_data_port_we[15]) + data_mem_grain15[main_data_port_adr] <= main_data_port_dat_w[127:120]; + memadr_17 <= main_data_port_adr; +end + +assign main_data_port_dat_r[127:120] = data_mem_grain15[memadr_17]; + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE ( + .C(sys_clk), + .CE(1'd1), + .D(1'd0), + .PRE(builder_xilinxasyncresetsynchronizerimpl0), + .Q(builder_xilinxasyncresetsynchronizerimpl0_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_1 ( + .C(sys_clk), + .CE(1'd1), + .D(builder_xilinxasyncresetsynchronizerimpl0_rst_meta), + .PRE(builder_xilinxasyncresetsynchronizerimpl0), + .Q(sys_rst) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_2 ( + .C(sys4x_clk), + .CE(1'd1), + .D(1'd0), + .PRE(builder_xilinxasyncresetsynchronizerimpl1), + .Q(builder_xilinxasyncresetsynchronizerimpl1_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_3 ( + .C(sys4x_clk), + .CE(1'd1), + .D(builder_xilinxasyncresetsynchronizerimpl1_rst_meta), + .PRE(builder_xilinxasyncresetsynchronizerimpl1), + .Q(builder_xilinxasyncresetsynchronizerimpl1_expr) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_4 ( + .C(sys4x_dqs_clk), + .CE(1'd1), + .D(1'd0), + .PRE(builder_xilinxasyncresetsynchronizerimpl2), + .Q(builder_xilinxasyncresetsynchronizerimpl2_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_5 ( + .C(sys4x_dqs_clk), + .CE(1'd1), + .D(builder_xilinxasyncresetsynchronizerimpl2_rst_meta), + .PRE(builder_xilinxasyncresetsynchronizerimpl2), + .Q(builder_xilinxasyncresetsynchronizerimpl2_expr) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_6 ( + .C(clk200_clk), + .CE(1'd1), + .D(1'd0), + .PRE(builder_xilinxasyncresetsynchronizerimpl3), + .Q(builder_xilinxasyncresetsynchronizerimpl3_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_7 ( + .C(clk200_clk), + .CE(1'd1), + .D(builder_xilinxasyncresetsynchronizerimpl3_rst_meta), + .PRE(builder_xilinxasyncresetsynchronizerimpl3), + .Q(clk200_rst) +); + +endmodule