From 169fb7b8625189915c1fd7fabc02b8b0141baa25 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 7 Dec 2017 02:12:49 +0100 Subject: [PATCH] Add CLBL?_?.SLICE?_X?.?FF.DMUX database entries Signed-off-by: Clifford Wolf Signed-off-by: Tim 'mithro' Ansell --- fuzzers/015-clbnffmux/Makefile | 1 + fuzzers/015-clbnffmux/generate.py | 47 +++++++++++++++++++++------- htmlgen/htmlgen.py | 51 +++++++++++++++++++------------ utils/dbfixup.py | 24 +++++++++++++-- 4 files changed, 89 insertions(+), 34 deletions(-) diff --git a/fuzzers/015-clbnffmux/Makefile b/fuzzers/015-clbnffmux/Makefile index cdd3cf23..14918675 100644 --- a/fuzzers/015-clbnffmux/Makefile +++ b/fuzzers/015-clbnffmux/Makefile @@ -10,6 +10,7 @@ pushdb: ${XRAY_MERGEDB} clbll_r seg_clblx.segbits ${XRAY_MERGEDB} clblm_l seg_clblx.segbits ${XRAY_MERGEDB} clblm_r seg_clblx.segbits + ${$XRAY_DBFIXUP} $(SPECIMENS_OK): bash generate.sh $(subst /OK,,$@) diff --git a/fuzzers/015-clbnffmux/generate.py b/fuzzers/015-clbnffmux/generate.py index 5b6e22ba..a559aada 100644 --- a/fuzzers/015-clbnffmux/generate.py +++ b/fuzzers/015-clbnffmux/generate.py @@ -1,11 +1,12 @@ #!/usr/bin/env python3 -import sys, re +import sys, os, re sys.path.append("../../../utils/") from segmaker import segmaker segmk = segmaker("design.bits") +cache = dict() print("Loading tags") ''' @@ -17,11 +18,11 @@ clb_NFFMUX_O6,SLICE_X14Y100,3 f = open('params.csv', 'r') f.readline() for l in f: - module,loc,n = l.split(',') + src,loc,n = l.split(',') n = int(n) which = chr(ord('A') + n) # clb_NFFMUX_AX => AX - module = module.replace('clb_NFFMUX_', '') + src = src.replace('clb_NFFMUX_', '') ''' AFFMUX @@ -33,14 +34,38 @@ for l in f: XOR 1 O6 1 ''' - # TODO: this needs to be converted to PIP type format - if 0: - # Although F78 is special, if it doesn't show up, we don't care - segmk.addtag(loc, "%cFF.DMUX.B0" % which, module in ('F78', 'CY', 'O5')) - segmk.addtag(loc, "%cFF.DMUX.B1" % which, module in ('F78', 'AX')) - segmk.addtag(loc, "%cFF.DMUX.B2" % which, module in ('CY', 'XOR')) - segmk.addtag(loc, "%cFF.DMUX.B3" % which, module in ('O5', 'O6')) -segmk.compile() + if loc not in cache: + cache[loc] = set("ABCD") + + if src == "F78": + if which in "AC": + src = "F7" + elif which == "B": + src = "F8" + else: + assert 0 + + if src == "AX": + src = which + "X" + + tag = "%sFF.DMUX.%s" % (which, src) + segmk.addtag(loc, tag, 1) + cache[loc].remove(which) + +for loc, muxes in cache.items(): + for which in muxes: + for src in "F7 F8 CY O5 AX XOR O6".split(): + if src == "F7" and which not in "AC": continue + if src == "F8" and which not in "B": continue + if src == "AX": src = which + "X" + tag = "%sFF.DMUX.%s" % (which, src) + segmk.addtag(loc, tag, 0) + +def bitfilter(frame_idx, bit_idx): + assert os.getenv("XRAY_DATABASE") == "artix7" + return frame_idx in [30, 31] + +segmk.compile(bitfilter=bitfilter) segmk.write() diff --git a/htmlgen/htmlgen.py b/htmlgen/htmlgen.py index 5ab8ee57..cce0acfe 100644 --- a/htmlgen/htmlgen.py +++ b/htmlgen/htmlgen.py @@ -112,32 +112,40 @@ for segname, segdata in grid["segments"].items(): for t in segdata["tiles"]: segtiles[segtype].add(grid["tiles"][t]["type"]) + def add_pip_bits(line): + bit_name, *bit_pos = line.split() + for bit in bit_pos: + if bit[0] == "!": + if bit[1:] not in routezbits[segtype]: + routezbits[segtype][bit[1:]] = set() + routezbits[segtype][bit[1:]].add(bit_name) + else: + if bit not in routebits[segtype]: + routebits[segtype][bit] = set() + routebits[segtype][bit].add(bit_name) + + def add_single_bit(line): + bit_name, bit_pos = line.split() + assert bit_pos[0] != "!" + segbits[segtype][bit_name] = bit_pos + segbits_r[segtype][bit_pos] = bit_name + if segtype not in ["hclk_l", "hclk_r"]: print("Loading %s segbits." % segtype) with open("../database/%s/segbits_%s.db" % (os.getenv("XRAY_DATABASE"), segtype)) as f: for line in f: - bit_name, bit_pos = line.split() - assert bit_pos[0] != "!" - segbits[segtype][bit_name] = bit_pos - segbits_r[segtype][bit_pos] = bit_name + if ".DMUX." in line: + add_pip_bits(line) + else: + add_single_bit(line) print("Loading %s segbits." % re.sub("clbl[lm]", "int", segtype)) with open("../database/%s/segbits_%s.db" % (os.getenv("XRAY_DATABASE"), re.sub("clbl[lm]", "int", segtype))) as f: for line in f: - bit_name, *bit_pos = line.split() - if segtype in ["hclk_l", "hclk_r"] and ".ENABLE_BUFFER." in bit_name: - segbits[segtype][bit_name] = bit_pos[0] - segbits_r[segtype][bit_pos[0]] = bit_name + if segtype in ["hclk_l", "hclk_r"] and ".ENABLE_BUFFER." in line: + add_single_bit(line) else: - for bit in bit_pos: - if bit[0] == "!": - if bit[1:] not in routezbits[segtype]: - routezbits[segtype][bit[1:]] = set() - routezbits[segtype][bit[1:]].add(bit_name) - else: - if bit not in routebits[segtype]: - routebits[segtype][bit] = set() - routebits[segtype][bit].add(bit_name) + add_pip_bits(line) print("Loading %s maskbits." % segtype) with open("../database/%s/mask_%s.db" % (os.getenv("XRAY_DATABASE"), segtype)) as f: @@ -384,6 +392,9 @@ function oml() { elif re.match("^INT_[LR].LH", bn): bgcolor = "#4466bb" label = "LH" + elif re.match("^CLBL[LM]_[LR].SLICE[LM]_X[01].[ABCD]FF.DMUX", bn): + bgcolor = "#88aaff" + label = "DMUX" elif re.match("^HCLK_[LR]", bn) and "_B_BOT" in bn: bgcolor = "#4466bb" label = "BOT" @@ -454,7 +465,7 @@ function oml() { for bit, pips in routebits_routezbits: for pip in pips: - grp = pip.split('.')[1] + grp = ".".join(pip.split('.')[:-1]) ruf.union(grp, bit) rgroups = dict() @@ -462,7 +473,7 @@ function oml() { for bit, pips in routebits_routezbits: for pip in pips: - grp_name = pip.split('.')[1] + grp_name = ".".join(pip.split('.')[:-1]) grp = ruf.find(grp_name) if grp not in rgroup_names: rgroup_names[grp] = set() @@ -476,7 +487,7 @@ function oml() { shared_bits = dict() for bit, pips in routebits_routezbits: for pip in pips: - grp_name = pip.split('.')[1] + grp_name = ".".join(pip.split('.')[:-1]) if bit not in shared_bits: shared_bits[bit] = set() shared_bits[bit].add(grp_name) diff --git a/utils/dbfixup.py b/utils/dbfixup.py index 6f897ce8..73011721 100644 --- a/utils/dbfixup.py +++ b/utils/dbfixup.py @@ -9,6 +9,16 @@ zero_db = [ "00_13 01_17 00_15 00_17|00_18 00_19 01_13 00_14", "00_34 00_38 01_33 01_37|00_35 00_39 01_38 01_40", "00_33 00_41 01_32 01_34|00_37 00_42 01_36 01_41", + + # CLBL?_?.SLICE?_X?.?FF.DMUX + "30_00 30_01 30_02 30_03", + "30_24 30_25 30_26 30_27", + "30_35 30_36 30_37 30_38", + "30_59 30_60 30_61 30_62", + "30_04 31_00 31_01 31_02", + "31_24 31_25 31_26 31_27", + "31_35 31_36 31_37 31_38", + "30_58 31_60 31_61 31_62", ] def add_zero_bits(tile_type): @@ -33,9 +43,13 @@ def add_zero_bits(tile_type): if bit not in bits: bits.add("!" + bit) for zdb in zero_db: - a, b = zdb.split("|") - a = a.split() - b = b.split() + if "|" in zdb: + a, b = zdb.split("|") + a = a.split() + b = b.split() + else: + a = zdb.split() + b = a match = False for bit in a: if bit in bits: @@ -70,6 +84,10 @@ def update_mask(mask_db, *src_dbs): add_zero_bits("int_l") add_zero_bits("int_r") +add_zero_bits("clbll_l") +add_zero_bits("clbll_r") +add_zero_bits("clblm_l") +add_zero_bits("clblm_r") update_mask("clbll_l", "clbll_l", "int_l") update_mask("clbll_r", "clbll_r", "int_r")