From 15cfb5bd46e4c9e17cf6b3f6fb8205914cdd4193 Mon Sep 17 00:00:00 2001 From: Jake Mercer Date: Sun, 27 Oct 2019 18:38:29 +0000 Subject: [PATCH] FUZZER - DSP - Add Ports & ROI Module Added code for ports to the DSP48E1 instances. Moved DSP instances inside an ROI module and using the verilog top harness as in other fuzzers. Signed-off-by: Jake Mercer --- fuzzers/100-dsp-mskpat/generate.py | 23 +++++--- fuzzers/100-dsp-mskpat/generate.tcl | 9 ++++ fuzzers/100-dsp-mskpat/top.py | 83 +++++++++++++++++++++++------ prjxray/verilog.py | 2 + 4 files changed, 96 insertions(+), 21 deletions(-) diff --git a/fuzzers/100-dsp-mskpat/generate.py b/fuzzers/100-dsp-mskpat/generate.py index 6f879a88..7f976dc0 100644 --- a/fuzzers/100-dsp-mskpat/generate.py +++ b/fuzzers/100-dsp-mskpat/generate.py @@ -5,6 +5,7 @@ from prjxray.verilog import to_int from prjxray.verilog import quote import json + def bits_in(value, width): bits = [] for i in range(width): @@ -14,7 +15,7 @@ def bits_in(value, width): def add(segmk, site, dsp, tag, bit, value, invert): - tag = dsp + '.' + '%s' % ('Z' if invert else '') + tag + '[%u]' % bit + tag = dsp + '.' + '%s' % ('Z' if invert else '') + tag + '[%u]' % bit value = (~value if invert else value) value >>= bit return segmk.add_site_tag(site, tag, value & 1) @@ -47,7 +48,9 @@ def run(): add(segmk, site, dsp, 'BCASCREG', i, to_int(params['BCASCREG']), 1) add(segmk, site, dsp, 'CARRYINREG', 0, to_int(params['CARRYINREG']), 1) - add(segmk, site, dsp, 'CARRYINSELREG', 0, to_int(params['CARRYINSELREG']), 1) + add( + segmk, site, dsp, 'CARRYINSELREG', 0, + to_int(params['CARRYINSELREG']), 1) add(segmk, site, dsp, 'CREG', 0, to_int(params['CREG']), 1) add(segmk, site, dsp, 'DREG', 0, to_int(params['DREG']), 0) @@ -91,8 +94,12 @@ def run(): AUTORESET[quote('RESET_NOT_MATCH')] = 1 AUTORESET[quote('RESET_MATCH')] = 2 - add(segmk, site, dsp, 'AUTORESET_PATDET', 0, AUTORESET[params['AUTORESET_PATDET']], 0) - add(segmk, site, dsp, 'AUTORESET_PATDET', 1, AUTORESET[params['AUTORESET_PATDET']], 1) + add( + segmk, site, dsp, 'AUTORESET_PATDET', 0, + AUTORESET[params['AUTORESET_PATDET']], 0) + add( + segmk, site, dsp, 'AUTORESET_PATDET', 1, + AUTORESET[params['AUTORESET_PATDET']], 1) for i in range(48): add(segmk, site, dsp, 'MASK', i, to_int(params['MASK']), 0) @@ -107,13 +114,17 @@ def run(): SEL_MASK[quote('ROUNDING_MODE2')] = 3 for i in range(2): - add(segmk, site, dsp, 'SEL_MASK', i, SEL_MASK[params['SEL_MASK']], 0) + add( + segmk, site, dsp, 'SEL_MASK', i, SEL_MASK[params['SEL_MASK']], + 0) USE_PATTERN_DETECT = {} USE_PATTERN_DETECT[quote('NO_PATDET')] = 0 USE_PATTERN_DETECT[quote('PATDET')] = 1 - add(segmk, site, dsp, 'USE_PATTERN_DETECT', 0, USE_PATTERN_DETECT[params['USE_PATTERN_DETECT']], 0) + add( + segmk, site, dsp, 'USE_PATTERN_DETECT', 0, + USE_PATTERN_DETECT[params['USE_PATTERN_DETECT']], 0) segmk.compile() segmk.write() diff --git a/fuzzers/100-dsp-mskpat/generate.tcl b/fuzzers/100-dsp-mskpat/generate.tcl index 9e8cab8a..ee2542fe 100644 --- a/fuzzers/100-dsp-mskpat/generate.tcl +++ b/fuzzers/100-dsp-mskpat/generate.tcl @@ -5,10 +5,19 @@ proc run {} { read_verilog top.v synth_design -top top + set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] + set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports di] + set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports do] + set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports stb] + set_property CFGBVS VCCO [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] + set_param tcl.collectionResultDisplayLimit 0 + + set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] + place_design route_design diff --git a/fuzzers/100-dsp-mskpat/top.py b/fuzzers/100-dsp-mskpat/top.py index 66a119ba..a480ebb6 100644 --- a/fuzzers/100-dsp-mskpat/top.py +++ b/fuzzers/100-dsp-mskpat/top.py @@ -30,30 +30,84 @@ def fuzz(*args): def run(): + verilog.top_harness(48, 48) + + print('module roi(input clk, input [47:0] din, output [47:0] dout);') + data = {} data['instances'] = [] - print('module top();') - sites = list(gen_sites()) - for (tile, site) in sites: + for i, (tile, site) in enumerate(sites): synthesis = '(* KEEP, DONT_TOUCH, LOC = "%s" *)' % (site) module = 'DSP48E1' instance = 'INST_%s' % (site) ports = {} params = {} + ports['A'] = '{30{1\'b1}}' + ports['ACIN'] = '{30{1\'b1}}' + ports['ACOUT'] = '30\'b0' + ports['ALUMODE'] = '4\'b1' + ports['B'] = '{18{1\'b1}}' + ports['BCIN'] = '{18{1\'b1}}' + ports['BCOUT'] = '18\'b0' + ports['C'] = '{48{1\'b1}}' + ports['CARRYCASCIN'] = '1\'b1' + ports['CARRYCASCOUT'] = '1\'b0' + ports['CARRYIN'] = '1\'b1' + ports['CARRYINSEL'] = '3\'b000' + ports['CARRYOUT'] = '4\'b0' + ports['CEA1'] = '1\'b1' + ports['CEA2'] = '1\'b1' + ports['CEAD'] = '1\'b1' + ports['CEALUMODE'] = '1\'b1' + ports['CEB1'] = '1\'b1' + ports['CEB2'] = '1\'b1' + ports['CEC'] = '1\'b1' + ports['CECARRYIN'] = '1\'b1' + ports['CECTRL'] = '1\'b1' + ports['CED'] = '1\'b1' + ports['CEINMODE'] = '1\'b1' + ports['CEM'] = '1\'b1' + ports['CEP'] = '1\'b1' + ports['CLK'] = '1\'b1' + ports['D'] = '{25{1\'b1}}' + ports['INMODE'] = '5\'b11111' + #ports['MULTISIGNIN'] = '1\'b1' + #ports['MULTISIGNOUT'] = '1\'b0' + ports['OPMODE'] = '7\'b1111111' + ports['OVERFLOW'] = '1\'b0' + ports['P'] = '48\'b0' + ports['PATTERNBDETECT'] = '1\'b0' + ports['PATTERNDETECT'] = '1\'b0' + ports['PCIN'] = '{48{1\'b1}}' + ports['PCOUT'] = '48\'b0' + ports['RSTA'] = '1\'b1' + ports['RSTALLCARRYIN'] = '1\'b1' + ports['RSTALUMODE'] = '1\'b1' + ports['RSTB'] = '1\'b1' + ports['RSTC'] = '1\'b1' + ports['RSTCTRL'] = '1\'b1' + ports['RSTD'] = '1\'b1' + ports['RSTINMODE'] = '1\'b1' + ports['RSTM'] = '1\'b1' + ports['RSTP'] = '1\'b1' + ports['UNDERFLOW'] = '1\'b0' + params['ADREG'] = fuzz((0, 1)) params['ALUMODEREG'] = fuzz((0, 1)) - # AREG/BREG requires inputs to be connected when configured with a value - # of 2, constraining to 0 and 1 for now. - params['AREG'] = fuzz((0, 1)) - params['ACASCREG'] = params['AREG'] if params[ - 'AREG'] == 0 or params['AREG'] == 1 else fuzz((1, 2)) - params['BREG'] = fuzz((0, 1)) - params['BCASCREG'] = params['BREG'] if params[ - 'BREG'] == 0 or params['BREG'] == 1 else fuzz((1, 2)) + params['AREG'] = fuzz((0, 1, 2)) + if params['AREG'] == 0 or params['AREG'] == 1: + params['ACASCREG'] = params['AREG'] + else: + params['ACASCREG'] = fuzz((1, 2)) + params['BREG'] = fuzz((0, 1, 2)) + if params['BREG'] == 0 or params['BREG'] == 1: + params['BCASCREG'] = params['BREG'] + else: + params['BCASCREG'] = fuzz((1, 2)) params['CARRYINREG'] = fuzz((0, 1)) params['CARRYINSELREG'] = fuzz((0, 1)) params['CREG'] = fuzz((0, 1)) @@ -64,11 +118,10 @@ def run(): params['A_INPUT'] = verilog.quote(fuzz(('DIRECT', 'CASCADE'))) params['B_INPUT'] = verilog.quote(fuzz(('DIRECT', 'CASCADE'))) params['USE_DPORT'] = verilog.quote(fuzz(('TRUE', 'FALSE'))) - params['USE_SIMD'] = verilog.quote( - fuzz(('ONE48', 'TWO24', 'FOUR12'))) + params['USE_SIMD'] = verilog.quote(fuzz(('ONE48', 'TWO24', 'FOUR12'))) params['USE_MULT'] = verilog.quote( - 'NONE' if params['USE_SIMD'] != verilog.quote('ONE48') else - fuzz(('NONE', 'MULTIPLY', 'DYNAMIC'))) + 'NONE' if params['USE_SIMD'] != verilog.quote('ONE48') else fuzz( + ('NONE', 'MULTIPLY', 'DYNAMIC'))) params['MREG'] = 0 if params['USE_MULT'] == verilog.quote( 'NONE') else fuzz((0, 1)) params['AUTORESET_PATDET'] = verilog.quote( diff --git a/prjxray/verilog.py b/prjxray/verilog.py index 0ca4f6f4..de3895e9 100644 --- a/prjxray/verilog.py +++ b/prjxray/verilog.py @@ -65,6 +65,7 @@ def unquote(s): assert s[0] == '"' and s[-1] == '"' return s[1:-1] + def to_int(s): value = 0 @@ -95,6 +96,7 @@ def to_int(s): return value + def parsei(s): if s == "1'b0": return 0