diff --git a/fuzzers/047-hclk-ioi-pips/Makefile b/fuzzers/047-hclk-ioi-pips/Makefile index 29d68354..a2dacd91 100644 --- a/fuzzers/047-hclk-ioi-pips/Makefile +++ b/fuzzers/047-hclk-ioi-pips/Makefile @@ -3,12 +3,12 @@ PIP_TYPE?=hclk_ioi3 PIPLIST_TCL=$(FUZDIR)/hclk_ioi3_pip_list.tcl TODO_RE=".*" # FIXME Modify fuzzer to solve PIPs that drive the BUFIO and BUFR from ILOGIC clock or through the IOI tile. -EXCLUDE_RE=".*\.HCLK_IOI_((RCLK_IMUX[0-3])|(I2IOCLK))" +EXCLUDE_RE=".*\.HCLK_IOI_((I2IOCLK)|(IDELAYCTRL))" MAKETODO_FLAGS= --sides "" --pip-type ${PIP_TYPE} --seg-type ${PIP_TYPE} --re $(TODO_RE) --exclude-re $(EXCLUDE_RE) N = 50 -SEGMATCH_FLAGS=-c 3 -m 15 -M 45 +SEGMATCH_FLAGS=-c 2 -m 15 -M 45 SPECIMENS_DEPS=build/cmt_regions.csv A_PIPLIST=hclk_ioi3.txt diff --git a/fuzzers/047-hclk-ioi-pips/generate.tcl b/fuzzers/047-hclk-ioi-pips/generate.tcl index c680e900..69617361 100644 --- a/fuzzers/047-hclk-ioi-pips/generate.tcl +++ b/fuzzers/047-hclk-ioi-pips/generate.tcl @@ -19,6 +19,17 @@ proc load_todo {{dir "dst"}} { return $todo_map } +proc shuffle_list {list} { + set l [llength $list] + for {set i 0} {$i<=$l} {incr i} { + set x [lindex $list [set p [expr {int(rand()*$l)}]]] + set list [lreplace $list $p $p] + set list [linsert $list [expr {int(rand()*$l)}] $x] + } + + return $list +} + # Get the dictionary of nets with one corresponding source wire # of a PIP from the todo list proc get_nets_with_todo_pip_wires {direction net_regexp wire_regexp used_destinations {verbose false}} { @@ -155,10 +166,18 @@ proc route_todo {} { lappend todos $dst_wire } + set todos_length [llength $todos] + if {$todos_length == 0} { + continue + } + puts "All todos for $tile_type / $wire" foreach dst_wire $todos { puts " - $dst_wire" } + + set todos [shuffle_list $todos] + set origin_node [get_nodes -of_objects [get_site_pins -filter {DIRECTION == OUT} -of_objects $net]] puts "Origin node: $origin_node" route_design -unroute -nets $net @@ -204,16 +223,16 @@ proc route_todo {} { } set todo_map [load_todo "srcs"] - set idelayctrl_nets [get_nets_with_todo_pip_wires "srcs" "IDELAYCTRL" "HCLK_IOI_IDELAYCTRL_REFCLK" $used_destinations] - puts "Idelayctrl nets: $idelayctrl_nets" - dict for {net tile_wire} $idelayctrl_nets { + set before_div_nets [get_nets_with_todo_pip_wires "srcs" "I_BUFR" "HCLK_IOI_RCLK_BEFORE_DIV" $used_destinations] + puts "Before div nets: $before_div_nets" + dict for {net tile_wire} $before_div_nets { set tile [lindex $tile_wire 0] set wire [lindex $tile_wire 1] set srcs [dict get $todo_map $wire] set tile_type [get_property TILE_TYPE [get_tiles $tile]] set todos {} - set old_origin_wire [get_wires -of_objects $net -filter {TILE_NAME =~ "*HCLK_IOI*" && NAME =~ "*HCLK_IOI_LEAF_GCLK_*"}] + set old_origin_wire [get_wires -of_objects $net -filter {TILE_NAME =~ "*HCLK_IOI*" && NAME =~ "*HCLK_IOI_RCLK_IMUX*"}] if {$old_origin_wire == {}} { continue } @@ -222,7 +241,7 @@ proc route_todo {} { puts "Previous target wire: $old_origin_wire" set old_origin_node [get_nodes -of_objects $old_origin_wire] - if [regexp "HCLK_IOI_LEAF_GCLK_\(\(TOP\)|\(BOT\)\).*" $old_origin_wire match group] { + if [regexp "HCLK_IOI_RCLK_IMUX.*" $old_origin_wire match group] { set old_target_side $group } foreach src $srcs { @@ -234,7 +253,7 @@ proc route_todo {} { set src_wire [lindex $src 1] set is_gclk_net 0 - if [regexp "HCLK_IOI_LEAF_GCLK_\(\(TOP\)|\(BOT\)\).*" $src_wire match group] { + if [regexp "HCLK_IOI_RCLK_IMUX.*" $src_wire match group] { set is_gclk_net 1 } @@ -245,10 +264,18 @@ proc route_todo {} { lappend todos $src_wire } + set todos_length [llength $todos] + if {$todos_length == 0} { + continue + } + puts "All todos for $tile_type / $wire" foreach src_wire $todos { puts " - $src_wire" } + + set todos [shuffle_list $todos] + set target_node [get_nodes -of_objects [get_site_pins -filter {DIRECTION == IN} -of_objects $net]] puts "Target node: $target_node" route_design -unroute -nets $net diff --git a/fuzzers/047-hclk-ioi-pips/top.py b/fuzzers/047-hclk-ioi-pips/top.py index 7d7da1eb..9eb6d92b 100644 --- a/fuzzers/047-hclk-ioi-pips/top.py +++ b/fuzzers/047-hclk-ioi-pips/top.py @@ -417,24 +417,33 @@ module top(); # BUFRs for _, site in gen_sites('BUFR'): if random.random() < 0.5: - wire_name = cmt_fast_clock_sources.get_random_source( - site_to_cmt[site], no_repeats=False) - if wire_name is None: - continue - src_cmt = cmt_fast_clock_sources.source_to_cmt[wire_name] - wire_name = check_cmt_clk_src(wire_name, src_cmt) - if wire_name is None: - continue + if random.random() < 0.7: + wire_name = luts.get_next_output_net() + else: + wire_name = cmt_fast_clock_sources.get_random_source( + site_to_cmt[site], no_repeats=False) + if wire_name is None: + continue + src_cmt = cmt_fast_clock_sources.source_to_cmt[wire_name] + wire_name = check_cmt_clk_src(wire_name, src_cmt) + if wire_name is None: + continue bufr_clock_sources.add_clock_source( 'O_{site}'.format(site=site), site_to_cmt[site]) + + # Add DIVIDE + divide = "BYPASS" + if random.random() < 0.8: + divide = "{}".format(random.randint(2, 8)) + print( """ assign I_{site} = {clock_source}; (* KEEP, DONT_TOUCH, LOC = "{site}" *) - BUFR bufr_{site} ( + BUFR #(.BUFR_DIVIDE("{divide}")) bufr_{site} ( .O(O_{site}), .I(I_{site}) - );""".format(site=site, clock_source=wire_name), + );""".format(site=site, clock_source=wire_name, divide=divide), file=bufs) for _, site in gen_sites('MMCME2_ADV'): @@ -450,6 +459,9 @@ module top(); print(bufs.getvalue()) + for l in luts.create_wires_and_luts(): + print(l) + print("endmodule")