From 10e2cd6cabbd2d1886d4410cf831d1155fe581d4 Mon Sep 17 00:00:00 2001 From: Tim 'mithro' Ansell Date: Mon, 5 Feb 2018 16:41:10 -0800 Subject: [PATCH] Rename flip-flop muxes to make Vivado GUI names. CLBLL_L.SLICEL_X0.AFF.DMUX -> CLBLL_L.SLICEL_X0.AFFMUX CLBLL_L.SLICEL_X0.AMUX -> CLBLL_L.SLICEL_X0.AOUTMUX Signed-off-by: Tim 'mithro' Ansell --- fuzzers/015-clbnffmux/README.md | 66 +++++++++++++++--------------- fuzzers/015-clbnffmux/generate.py | 4 +- fuzzers/016-clbnoutmux/README.md | 66 +++++++++++++++--------------- fuzzers/016-clbnoutmux/generate.py | 4 +- 4 files changed, 70 insertions(+), 70 deletions(-) diff --git a/fuzzers/015-clbnffmux/README.md b/fuzzers/015-clbnffmux/README.md index 820fcf39..f67ed3b6 100644 --- a/fuzzers/015-clbnffmux/README.md +++ b/fuzzers/015-clbnffmux/README.md @@ -1,42 +1,42 @@ Purpose: -Document AFFMUX family of CLB muxes +Document nFFMUX family of CLB muxes Algorithm: Outcome: -CLB.SLICE_X0.AFF.DMUX.B0 30_00 -CLB.SLICE_X0.AFF.DMUX.B1 30_01 -CLB.SLICE_X0.AFF.DMUX.B2 30_02 -CLB.SLICE_X0.AFF.DMUX.B3 30_03 -CLB.SLICE_X0.BFF.DMUX.B0 30_27 -CLB.SLICE_X0.BFF.DMUX.B1 30_26 -CLB.SLICE_X0.BFF.DMUX.B2 30_25 -CLB.SLICE_X0.BFF.DMUX.B3 30_24 -CLB.SLICE_X0.CFF.DMUX.B0 30_35 -CLB.SLICE_X0.CFF.DMUX.B1 30_36 -CLB.SLICE_X0.CFF.DMUX.B2 30_37 -CLB.SLICE_X0.CFF.DMUX.B3 30_38 -CLB.SLICE_X0.DFF.DMUX.B0 30_62 -CLB.SLICE_X0.DFF.DMUX.B1 30_61 -CLB.SLICE_X0.DFF.DMUX.B2 30_60 -CLB.SLICE_X0.DFF.DMUX.B3 30_59 -CLB.SLICE_X1.AFF.DMUX.B0 31_00 -CLB.SLICE_X1.AFF.DMUX.B1 31_01 -CLB.SLICE_X1.AFF.DMUX.B2 31_02 -CLB.SLICE_X1.AFF.DMUX.B3 30_04 -CLB.SLICE_X1.BFF.DMUX.B0 31_25 -CLB.SLICE_X1.BFF.DMUX.B1 31_27 -CLB.SLICE_X1.BFF.DMUX.B2 31_26 -CLB.SLICE_X1.BFF.DMUX.B3 31_24 -CLB.SLICE_X1.CFF.DMUX.B0 31_35 -CLB.SLICE_X1.CFF.DMUX.B1 31_38 -CLB.SLICE_X1.CFF.DMUX.B2 31_37 -CLB.SLICE_X1.CFF.DMUX.B3 31_36 -CLB.SLICE_X1.DFF.DMUX.B0 30_58 -CLB.SLICE_X1.DFF.DMUX.B1 31_61 -CLB.SLICE_X1.DFF.DMUX.B2 31_62 -CLB.SLICE_X1.DFF.DMUX.B3 31_60 +CLB.SLICE_X0.AFFMUX.B0 30_00 +CLB.SLICE_X0.AFFMUX.B1 30_01 +CLB.SLICE_X0.AFFMUX.B2 30_02 +CLB.SLICE_X0.AFFMUX.B3 30_03 +CLB.SLICE_X0.BFFMUX.B0 30_27 +CLB.SLICE_X0.BFFMUX.B1 30_26 +CLB.SLICE_X0.BFFMUX.B2 30_25 +CLB.SLICE_X0.BFFMUX.B3 30_24 +CLB.SLICE_X0.CFFMUX.B0 30_35 +CLB.SLICE_X0.CFFMUX.B1 30_36 +CLB.SLICE_X0.CFFMUX.B2 30_37 +CLB.SLICE_X0.CFFMUX.B3 30_38 +CLB.SLICE_X0.DFFMUX.B0 30_62 +CLB.SLICE_X0.DFFMUX.B1 30_61 +CLB.SLICE_X0.DFFMUX.B2 30_60 +CLB.SLICE_X0.DFFMUX.B3 30_59 +CLB.SLICE_X1.AFFMUX.B0 31_00 +CLB.SLICE_X1.AFFMUX.B1 31_01 +CLB.SLICE_X1.AFFMUX.B2 31_02 +CLB.SLICE_X1.AFFMUX.B3 30_04 +CLB.SLICE_X1.BFFMUX.B0 31_25 +CLB.SLICE_X1.BFFMUX.B1 31_27 +CLB.SLICE_X1.BFFMUX.B2 31_26 +CLB.SLICE_X1.BFFMUX.B3 31_24 +CLB.SLICE_X1.CFFMUX.B0 31_35 +CLB.SLICE_X1.CFFMUX.B1 31_38 +CLB.SLICE_X1.CFFMUX.B2 31_37 +CLB.SLICE_X1.CFFMUX.B3 31_36 +CLB.SLICE_X1.DFFMUX.B0 30_58 +CLB.SLICE_X1.DFFMUX.B1 31_61 +CLB.SLICE_X1.DFFMUX.B2 31_62 +CLB.SLICE_X1.DFFMUX.B3 31_60 diff --git a/fuzzers/015-clbnffmux/generate.py b/fuzzers/015-clbnffmux/generate.py index 38fd2a80..79b49912 100644 --- a/fuzzers/015-clbnffmux/generate.py +++ b/fuzzers/015-clbnffmux/generate.py @@ -52,7 +52,7 @@ for l in f: src = which + "X" # add the 1-tag for this connection - tag = "%sFF.DMUX.%s" % (which, src) + tag = "%sFFMUX.%s" % (which, src) segmk.addtag(loc, tag, 1) # remove this MUX from the cache, preventing generation of 0-tags for this MUX @@ -65,7 +65,7 @@ for loc, muxes in cache.items(): if src == "F7" and which not in "AC": continue if src == "F8" and which not in "B": continue if src == "AX": src = which + "X" - tag = "%sFF.DMUX.%s" % (which, src) + tag = "%sFFMUX.%s" % (which, src) segmk.addtag(loc, tag, 0) diff --git a/fuzzers/016-clbnoutmux/README.md b/fuzzers/016-clbnoutmux/README.md index 6bcb8088..d0e31619 100644 --- a/fuzzers/016-clbnoutmux/README.md +++ b/fuzzers/016-clbnoutmux/README.md @@ -1,43 +1,43 @@ Purpose: -Document AOUTMUX family of CLB muxes +Document nOUTMUX family of CLB muxes TODO: document O6 Algorithm: Outcome: -CLB.SLICE_X0.AMUX.B0 30_11 -CLB.SLICE_X0.AMUX.B1 30_08 -CLB.SLICE_X0.AMUX.B2 30_06 -CLB.SLICE_X0.AMUX.B3 30_07 -CLB.SLICE_X0.BMUX.B0 30_20 -CLB.SLICE_X0.BMUX.B1 30_21 -CLB.SLICE_X0.BMUX.B2 30_22 -CLB.SLICE_X0.BMUX.B3 30_23 -CLB.SLICE_X0.CMUX.B0 30_45 -CLB.SLICE_X0.CMUX.B1 30_44 -CLB.SLICE_X0.CMUX.B2 30_40 -CLB.SLICE_X0.CMUX.B3 30_43 -CLB.SLICE_X0.DMUX.B0 30_56 -CLB.SLICE_X0.DMUX.B1 30_51 -CLB.SLICE_X0.DMUX.B2 30_52 -CLB.SLICE_X0.DMUX.B3 30_57 -CLB.SLICE_X1.AMUX.B0 31_09 -CLB.SLICE_X1.AMUX.B1 31_07 -CLB.SLICE_X1.AMUX.B2 31_10 -CLB.SLICE_X1.AMUX.B3 30_05 -CLB.SLICE_X1.BMUX.B0 31_20 -CLB.SLICE_X1.BMUX.B1 30_28 -CLB.SLICE_X1.BMUX.B2 31_21 -CLB.SLICE_X1.BMUX.B3 30_29 -CLB.SLICE_X1.CMUX.B0 31_43 -CLB.SLICE_X1.CMUX.B1 30_42 -CLB.SLICE_X1.CMUX.B2 31_40 -CLB.SLICE_X1.CMUX.B3 30_41 -CLB.SLICE_X1.DMUX.B0 31_56 -CLB.SLICE_X1.DMUX.B1 30_53 -CLB.SLICE_X1.DMUX.B2 31_57 -CLB.SLICE_X1.DMUX.B3 31_53 +CLB.SLICE_X0.AOUTMUX.B0 30_11 +CLB.SLICE_X0.AOUTMUX.B1 30_08 +CLB.SLICE_X0.AOUTMUX.B2 30_06 +CLB.SLICE_X0.AOUTMUX.B3 30_07 +CLB.SLICE_X0.BOUTMUX.B0 30_20 +CLB.SLICE_X0.BOUTMUX.B1 30_21 +CLB.SLICE_X0.BOUTMUX.B2 30_22 +CLB.SLICE_X0.BOUTMUX.B3 30_23 +CLB.SLICE_X0.COUTMUX.B0 30_45 +CLB.SLICE_X0.COUTMUX.B1 30_44 +CLB.SLICE_X0.COUTMUX.B2 30_40 +CLB.SLICE_X0.COUTMUX.B3 30_43 +CLB.SLICE_X0.DOUTMUX.B0 30_56 +CLB.SLICE_X0.DOUTMUX.B1 30_51 +CLB.SLICE_X0.DOUTMUX.B2 30_52 +CLB.SLICE_X0.DOUTMUX.B3 30_57 +CLB.SLICE_X1.AOUTMUX.B0 31_09 +CLB.SLICE_X1.AOUTMUX.B1 31_07 +CLB.SLICE_X1.AOUTMUX.B2 31_10 +CLB.SLICE_X1.AOUTMUX.B3 30_05 +CLB.SLICE_X1.BOUTMUX.B0 31_20 +CLB.SLICE_X1.BOUTMUX.B1 30_28 +CLB.SLICE_X1.BOUTMUX.B2 31_21 +CLB.SLICE_X1.BOUTMUX.B3 30_29 +CLB.SLICE_X1.COUTMUX.B0 31_43 +CLB.SLICE_X1.COUTMUX.B1 30_42 +CLB.SLICE_X1.COUTMUX.B2 31_40 +CLB.SLICE_X1.COUTMUX.B3 30_41 +CLB.SLICE_X1.DOUTMUX.B0 31_56 +CLB.SLICE_X1.DOUTMUX.B1 30_53 +CLB.SLICE_X1.DOUTMUX.B2 31_57 +CLB.SLICE_X1.DOUTMUX.B3 31_53 From manual O6 testing diff --git a/fuzzers/016-clbnoutmux/generate.py b/fuzzers/016-clbnoutmux/generate.py index 7c8dda15..ede555f0 100644 --- a/fuzzers/016-clbnoutmux/generate.py +++ b/fuzzers/016-clbnoutmux/generate.py @@ -52,7 +52,7 @@ for l in f: src = which + "5Q" # add the 1-tag for this connection - tag = "%sMUX.%s" % (which, src) + tag = "%sOUTMUX.%s" % (which, src) segmk.addtag(loc, tag, 1) # remove this MUX from the cache, preventing generation of 0-tags for this MUX @@ -65,7 +65,7 @@ for loc, muxes in cache.items(): if src == "F7" and which not in "AC": continue if src == "F8" and which not in "B": continue if src == "5Q": src = which + "5Q" - tag = "%sMUX.%s" % (which, src) + tag = "%sOUTMUX.%s" % (which, src) segmk.addtag(loc, tag, 0)